M48T86PC ,5V PC REAL TIME CLOCKLogic Diagram– End-of-Clock Update Cycle■ PROGRAMMABLE SQUARE WAVE OUTPUT■ SELF-CONTAINED BATTERY a ..
M48T86PC1 ,5 VOLT PC REAL TIME CLOCKFEATURES SUMMARY■ DROP-IN REPLACEMENT FOR PC Figure 1. 24-pin PCDIP, CAPHAT™ PackageCOMPUTER CLOCK/ ..
M48Z02-150PC1 ,16 KBIT (2KB X 8) ZEROPOWER SRAMTABLE OF CONTENTSSUMMARY DESCRIPTION . . . 3Figure 2.
M48Z02-150PC1. ,16 KBIT (2KB X 8) ZEROPOWER SRAMLogic Diagram Table 1. Signal NamesA0-A10 Address InputsVCCDQ0-DQ7 Data Inputs / Outputs11 8E Chip ..
M48Z02-150PC6 ,CMOS 2K x 8 zeropower SRAM, 150nsBlock DiagramA0-A10LITHIUMDQ0-DQ7CELLPOWER2K x 8SRAM ARRAYVOLTAGE SENSEANDESWITCHING VPFDCIRCUITRYW ..
M48Z02-200PC1 ,16 KBIT (2KB X 8) ZEROPOWER SRAMLogic Diagram . . 3Table 1. Signal Names . . . 3Figure 3. DIP Connections 3Fig ..
M61523FP , Electronic Volume with Scf Type Tone Control To 6 Speakers
M61523FP , Electronic Volume with Scf Type Tone Control To 6 Speakers
M61538FP , 6-Channel Electronic Volume
M61538FP , 6-Channel Electronic Volume
M61545AFP , Serial Data Control Dual Electronic Volume
M61545AFP , Serial Data Control Dual Electronic Volume
M48T86PC
5V PC REAL TIME CLOCK
1/23May 2000
M48T865V PC REAL TIME CLOCK DROP-IN REPLACEMENT for PC
COMPUTER CLOCK/CALENDAR COUNTS SECONDS, MINUTES, HOURS,
DAYS, DAY of the WEEK, DATE, MONTH and
YEAR with LEAP YEAR COMPENSATION INTERFACED WITH SOFTWARE AS 128
RAM LOCATIONS: 14 Bytes of Clock and Control Registers 114 Bytes of General Purpose RAM SELECTABLE BUS TIMING (Intel/Motorola) THREE INTERRUPTS are SEPARATELY
SOFTWARE-MASKABLE and TESTABLE Time-of-Day Alarm (Once/Second to
Once/Day) Periodic Rates from 122μs to 500ms End-of-Clock Update Cycle PROGRAMMABLE SQUARE WAVE OUTPUT SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT® TOP
(to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP
CONTAINS the BATTERY and CRYSTAL PIN and FUNCTION COMPATIBLE with
bq3285/7A and DS128887
M48T86
Table 1. Signal Names
DESCRIPTIONThe M48T86 is an industry standard real time
clock (RTC).The M48T86 is composed of a lithium
energy source, quartz crystal, write-protection cir-
cuitry, and a 128 byte RAM array. This provides
the user with a complete subsystem packaged in
either a 24-pin DIP CAPHAT or 28-pin SNAPHAT
SOIC. Functions available to the user include a
non-volatile time-of-day clock, alarm interrupts, a
one-hundred-year clock with programmable inter-
rupts, square wave output, and 128 bytes of non-
volatile static RAM.
The 24 pin 600mil DIP CAPHAT™ houses the
M48T86 silicon with a quartz crystal and a long life
lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape & Reel
form.
3/23
M48T86
Table 2. Absolute Maximum Ratings (1)Note:1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.For the 28 lead SOIC, the battery/crystal package
part number is "M4T28-BR12SH1".
Automatic deselection of the device provides in-
surance that data integrity is not compromised
should VCC fall below specified Power-fail Dese-
lect Voltage (VPFD) levels. The automatic deselec-
tion of the device remains in effect upon power up
for a period of 200ms (max) after VCC rises above
VPFD, provided that the Real Time Clock is running
and the count down chain is not reset. This allows
sufficient time for VCC to stabilize and gives the
system clock a wake up period so that a valid sys-
tem reset can be established.
The block diagram in Figure 3 shows the pin con-
nections and the major internal functions of the
M48T86.
SIGNAL DESCRIPTION
VCC, VSS. DC power is provided to the device on
these pins.The M48T86 utilizes a 5V VCC.
SQW (Square Wave Output). During normal op-
eration (i.e. valid VCC), the SQW pin can output a
signal from one of 13 taps.The frequency of the
SQW pin can be changed by programming Regis-
ter A as shown in Table 10. The SQW signal can
be turned on and off using the SQWE bit (Register
B; bit 3). The SQW signal is not available when
VCC is less than VPFD.
AD0-AD7 (Multiplexed Bi-Directional Address/
Data Bus). The M48T86 provides a multiplexed
bus in which address and data information share
the same signal path. The bus cycle consists of
two stages; first the address is latched, followed by
the data. Address/Data multiplexing does not slow
the access time of the M48T86, since the bus
change from address to data occurs during the in-
ternal RAM access time. Addresses must be valid
prior to the falling edge of AS, at which time the
M48T86 latches the address present on AD0-
AD7. Valid write data must be present and held
stable during the latter portion of the R/W pulse. In
a read cycle, the M48T86 outputs 8 bits of data
during the latter portion of the DS pulse. The read
cycle is terminated and the bus returns to a high
impedance state upon a high transition on R/W.
AS (Address Strobe Input). A positive going
pulse on the Address Strobe (AS) input serves to
demultiplex the bus. The falling edge of AS causes
the address present on AD0-AD7 to be latched
within the M48T86.
MOT (Mode Select). The MOT pin offers the flex-
ibility to choose between two bus types. When
connected to VCC, Motorola bus timing is selected.
When connected to VSS or left disconnected, Intel
bus timing is selected. The pin has an internal pull-
down resistance of approximately 20K ohms.
M48T86
DS (Data Strobe Input). The DS pin is also re-
ferred to as Read (RD). A falling edge transition on
the Data Strobe (DS) input enables the output dur-
ing a a read cycle. This is very similar to an Output
Enable (G) signal on other memory devices.
E (Chip Enable Input). The Chip Enable pin
must be asserted low for a bus cycle in the
M48T86 to be accessed. Bus cycles which take
place without asserting E will latch the addresses
present, but no data access will occur.
IRQ (Interrupt Request Output). The IRQ pin is
an open drain output that can be used as an inter-
rupt input to a processor. The IRQ output remains
low as long as the status bit causing the interrupt
is present and the corresponding interrupt-enable
bit is set. IRQ returns to a high impedance state
whenever Register C is read. The RST pin can
also be used to clear pending interrupts. Because
the IRQ bus is an open drain output, it requires an
external pull-up resistor to VCC.
5/23
M48T86
RST (Reset Input). The M48T86 is reset when
the RST input is pulled low. With a valid VCC ap-
plied and a low on RST, the following events oc-
cur: Periodic Interrupt Enable (PIE) bit is cleared to
a zero. (Register B; Bit 6) Alarm Interrupt Enable (AIE) bit is cleared to a
zero.(Register B; bit 5) Update Ended Interrupt Request (UF) bit is
cleared to a zero. (Register C; Bit 4) Interrupt Request (IRQF) bit is cleared to a zero.
(Register C Bit 7) Periodic Interrupt Flag (PF) bit is cleared to a
zero. (Register C; Bit 6) The device is not accessible until RST is re-
turned high. Alarm Interrupt Flag (AF) bit is cleared to a zero.
(Register C; Bit 5) The IRQ pin is in the high impedance state. Square Wave Output Enable (SQWE) bit is
cleared to zero. (Register B; Bit 3).
10.Update Ended Interrupt Enable (UIE) is cleared
to a zero. (Register B; Bit 4)
RCL (RAM Clear). The RCL pin is used to clear
all 114 storage bytes, excluding clock and control
registers, of the array to FF(hex) value. The array
will be cleared when the RCL pin is held low for at
least 100ms with the oscillator running. Usage of
this pin does not affect battery load. This function
is applicable only when VCC is applied.
R/W (Read/Write Input). The R/W pin is utilized
to latch data into the M48T86 and provides func-
tionality similar to W in other memory systems.
ADDRESS MAPThe address map of the M48T86 is shown in Fig-
ure 9. It consists of 114 bytes of user RAM, 10
bytes of RAM that contain the RTC time, calendar
and alarm data, and 4 bytes which are used for
control and status. All bytes can be read or written
to except for the following: Registers C & D are read-only. Bit 7 of Register A is read-only.
The contents of the four Registers A, B, C, and D
are described in the "Registers" section.
M48T86
Table 3. Time, Calendar and Alarm Formats
TIME, CALENDAR, AND ALARM LOCATIONSThe time and calendar information is obtained by
reading the appropriate memory bytes. The time,
calendar, and alarm registers are set or initialized
by writing the appropriate RAM bytes. The con-
tents of the time, calendar, and alarm bytes can be
either Binary or Binary-Coded Decimal (BCD) for-
mat. Before writing the internal time, calendar, and
alarm register, the SET bit (Register B; Bit 7)
should be written to a logic "1". This will prevent
updates from occurring while access is being at-
tempted. In addition to writing the time, calendar,
and alarm registers in a selected format (binary or
BCD), the Data Mode (DM) bit (Register B; Bit 2),
must be set to the appropriate logic level ("1" sig-
nifies binary data; "0" signifies Binary Coded Dec-
imal (BCD data). All time, calendar, and alarm
bytes must use the same data mode. The SET bit
should be cleared after the Data Mode bit has
been written to allow the Real Time Clock to up-
date the time and calendar bytes. Once initialized,
the Real Time Clock makes all updates in the se-
lected mode. The data mode cannot be changed
without reinitializing the ten data bytes. Table 3
shows the binary and BCD formats of the time, cal-
endar, and alarm locations. The 24/12 bit (Regis-
ter B; Bit 1) cannot be changed without
reinitializing the hour locations. When the 12-hour
format is selected, a logic one in the high order bit
of the hours byte represents PM. The time, calen-
dar, and alarm bytes are always accessible be-
cause they are double buffered. Once per second
the ten bytes are advanced by one second and
checked for an alarm condition. If a read of the
time and calendar data occurs during an update, a
problem exists where seconds, minutes, hours,
etc. may not correlate. However, the probability of
reading incorrect time and calendar data is low.
Methods of avoiding possible incorrect time and
calendar reads are reviewed later in this text.
NON-VOLATILE RAMThe 114 general purpose non-volatile RAM bytes
are not dedicated to any special function within the
M48T86. They can be used by the processor pro-
gram as non-volatile memory and are fully acces-
sible during the update cycle.
7/23
M48T86
Table 4. AC Measurement ConditionsNote that Output Hi-Z is defined as the point where data is no longer driven.
Table 5. Capacitance (1, 2) (TA = 25 °C, f = 1 MHz)
Note:1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. Outputs deselected.
Table 6. DC Characteristics (1)(TA = 0 to 70 °C; VCC = 4.5V to 5.5V)
Note:1. Outputs deselected.
M48T86
Table 7. Power Down/Up Trip Points DC Characteristics (1)(TA = 0 to 70 °C)
Note:1. All voltages referenced to VSS. At 25°C.
Table 8. Power Down/Up Mode AC Characteristics(TA = 0 to 70°C)
Note:1. VCC fall time of less than tF may result in deselection/write protection not occurring until 200μs after VCC passes VPFD.
INTERRUPTSThe RTC plus RAM includes three separate, fully
automatic sources of interrupt (alarm, periodic, up-
date-in-progress) available to a processor. The
alarm interrupt can be programmed to occur at
rates from once per second to once per day. The
periodic interrupt can be selected from rates of
500ms to 122μs. The update-ended interrupt can
be used to indicate that an update cycle has com-
pleted.
The processor program can select which inter-
rupts, if any, are going to be used. Three bits in
Register B enable the interrupts. Writing a logic "1"
to an interrupt-enable bit (Register B; Bit 6= PIE;
Bit 5= AIE; Bit 4= UIE) permits an interrupt to be
initialized when the event occurs. A zero in an in-
terrupt-enable bit prohibits the IRQ pin from being
asserted from that interrupt condition. If an inter-
rupt flag is already set when an interrupt is en-
abled, IRQ is immediately set at an active level,
although the interrupt initiating the event may have
occurred much earlier. As a result, there are cases
where the program should clear such earlier initi-
ated interrupts before first enabling new interrupts.
9/23
M48T86
Table 9. AC Characteristics (TA = 0 to 70 °C; VCC = 4.5V to 5.5V)
Note:1. See Table 10.
When an interrupt event occurs, the related flag bit
(Register C; Bit 6 = PF; Bit 5 = AF; Bit 4 = UF) is
set to a logic "1". These flag bits are set indepen-
dent of the state of the corresponding enable bit in
Register B and can be used in a polling mode with-
out enabling the corresponding enable bits. The
interrupt flag bits are status bits which software
can interrogate as necessary.
When a flag is set, an indication is given to soft-
ware that an interrupt event has occurred since the
flag bit was last read; however, care should be tak-
en when using the flag bits as all are cleared each
time Register C is read. Double latching is includ-
ed with Register C so that bits which are set, re-
main stable throughout the read cycle. All bits
which are set high are cleared when read. Any
new interrupts which are pending during the read
cycle are held until after the cycle is completed.
One, two, or three bits can be set when reading
Register C. Each utilized flag bit should be exam-
ined when read to ensure that no interrupts are
lost.
The second flag bit usage method is with fully en-
abled interrupts. When an interrupt flag bit is set
and the corresponding enable bit is also set, the
IRQ pin is asserted low. IRQ is asserted as long as
at least one of the three interrupt sources has its
flag and enable bits both set. The IRQF bit (Regis-
ter C; Bit 7) is a "1" whenever the IRQ pin is being
driven low. Determination that the RTC initiated an
interrupt is accomplished by reading Register C.A
logic "1" in the IRQF bit indicates that one or more
interrupts have been initiated by the M48T86. The
act of reading Register C clears all active flag bits
and the IRQF bit.
M48T86
11/23
M48T86
PERIODIC INTERRUPTThe periodic interrupt will cause the IRQ pin to go
to an active state from once every 500ms to once
every 122μs. This function is separate from the
alarm interrupt which can be output from once per
second to once per day. The periodic interrupt rate
is selected using the same Register A bits which
select the square wave frequency (see Table 10).
Changing the Register A bits affects both the
square wave frequency and the periodic interrupt
output. However, each function has a separate en-
able bit in Register B. The periodic interrupt is en-
abled by the PIE bit (Register B; Bit 6). The
periodic interrupt can be used with software
counters to measure inputs, create output inter-
vals, or await the next needed software function.
ALARM INTERRUPTThe alarm interrupt provides the system processor
with an interrupt when a match is made between
the RTC's hours, minutes, and seconds bytes and
the corresponding alarm bytes.
The three alarm bytes can be used in two ways.
First, when the alarm time is written in the appro-
priate hours, minutes, and seconds alarm loca-
tions, the alarm interrupt is initiated at the specified
time each day if the Alarm Interrupt Enable bit
(Register B; Bit 5) is high. The second use is to in-
sert a "don't care" state in one or more of the three
alarm bytes. The "don't care" code is any hexadec-
imal value from C0 to FF. The two most significant
bits of each byte set the "don't care" condition
when at logic "1". An alarm will be generated each
hour when the "don't care" is are set in the hours
byte. Similarly, an alarm is generated every minute
with "don't care" codes in the hour and minute
alarm bytes. The "don't care" codes in all three
alarm bytes create an interrupt every second.
M48T86
UPDATE CYCLE INTERRUPTAfter each update cycle, the update cycle ended
flag bit (UF) (Register C; Bit 4) is set to a "1". If the
update interrupt enable bit (UIE) (Register B; Bit 4)
is set to a "1", and the SET bit (Register B; Bit 7) is
a "0", then an interrupt request is generated at the
end of each update cycle.
SQUARE WAVE OUTPUT SELECTIONThirteen of the 15 divider taps are made available
to a 1-of-15 selector, as shown in the block dia-
gram of Figure 3. The purpose of selecting a divid-
er tap is to generate a square wave output signal
on the SQW pin. The RS3-RS0 bits in Register A
establish the square wave output frequency.
These frequencies are listed in Table 10. The
SQW frequency selection shares the 1-of-15 se-
lector with the periodic interrupt generator. Once
the frequency is selected, the output of the SQW
pin can be turned on and off under program control
with the square wave enabled (SQWE).
OSCILLATOR CONTROL BITSWhen the M48T86 is shipped from the factory the
internal oscillator is turned off. This feature pre-
vents the lithium energy cell from being dis-
charged until it is installed in a system. A pattern of
"010" in Bits 4-6 of Register A will turn the oscilla-
tor on and enable the countdown chain. A pattern
of "11X" will turn the oscillator on, but holds the
countdown chain of the oscillator in reset. All other
combinations of Bits 4-6 keep the oscillator off.
