M48T86PC1 ,5 VOLT PC REAL TIME CLOCKFEATURES SUMMARY■ DROP-IN REPLACEMENT FOR PC Figure 1. 24-pin PCDIP, CAPHAT™ PackageCOMPUTER CLOCK/ ..
M48Z02-150PC1 ,16 KBIT (2KB X 8) ZEROPOWER SRAMTABLE OF CONTENTSSUMMARY DESCRIPTION . . . 3Figure 2.
M48Z02-150PC1. ,16 KBIT (2KB X 8) ZEROPOWER SRAMLogic Diagram Table 1. Signal NamesA0-A10 Address InputsVCCDQ0-DQ7 Data Inputs / Outputs11 8E Chip ..
M48Z02-150PC6 ,CMOS 2K x 8 zeropower SRAM, 150nsBlock DiagramA0-A10LITHIUMDQ0-DQ7CELLPOWER2K x 8SRAM ARRAYVOLTAGE SENSEANDESWITCHING VPFDCIRCUITRYW ..
M48Z02-200PC1 ,16 KBIT (2KB X 8) ZEROPOWER SRAMLogic Diagram . . 3Table 1. Signal Names . . . 3Figure 3. DIP Connections 3Fig ..
M48Z02-200PC1 ,16 KBIT (2KB X 8) ZEROPOWER SRAMBlock Diagram . . 4MAXIMUM RATING . 4Table 2.
M61523FP , Electronic Volume with Scf Type Tone Control To 6 Speakers
M61523FP , Electronic Volume with Scf Type Tone Control To 6 Speakers
M61538FP , 6-Channel Electronic Volume
M61538FP , 6-Channel Electronic Volume
M61545AFP , Serial Data Control Dual Electronic Volume
M61545AFP , Serial Data Control Dual Electronic Volume
M48T86MH1-M48T86-MH1-M48T86MH1E-M48T86MH1F-M48T86-MH1F-M48T86PC1
5 VOLT PC REAL TIME CLOCK
1/29April 2004
M48T865.0V PC Real-Time Clock
FEATURES SUMMARY DROP-IN REPLACEMENT FOR PC
COMPUTER CLOCK/CALENDAR COUNTS SECONDS, MINUTES, HOURS,
DAYS, DAY OF THE WEEK, DATE, MONTH,
and YEAR WITH LEAP YEAR
COMPENSATION INTERFACED WITH SOFTWARE AS 128
RAM LOCATIONS: 14 Bytes of Clock and Control Registers 114 Bytes of General Purpose RAM SELECTABLE BUS TIMING (Intel/Motorola) THREE INTERRUPTS ARE SEPARATELY
SOFTWARE-MASKABLE and TESTABLE Time-of-Day Alarm (Once/Second to
Once/Day) Periodic Rates from 122µs to 500ms End-of-Clock Update Cycle PROGRAMMABLE SQUARE WAVE
OUTPUT 10 YEARS OF DATA RETENTION AND
CLOCK OPERATION IN THE ABSENCE OF
POWER SELF-CONTAINED BATTERY AND
CRYSTAL IN THE CAPHAT DIP PACKAGE PACKAGING INCLUDES A 28-LEAD SOIC
and SNAPHAT® TOP (to be ordered
separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
CONTAINS THE BATTERY AND CRYSTAL PIN AND FUNCTION COMPATIBLE WITH
bq3285/7A and DS12887
M48T86
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 24-pin PCDIP, CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. 24-pin DIP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 5. 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7VCC, VSS.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
SQW (Square Wave Output). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
AD0-AD7 (Multiplexed Bi-Directional Address/Data Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
AS (Address Strobe Input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
MOT (Mode Select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
DS (Data Strobe Input).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
E (Chip Enable Input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
IRQ (Interrupt Request Output). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
RST (Reset Input).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
RCL (RAM Clear). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
R/W (READ/WRITE Input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Non-Volatile RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 7. Intel Bus READ AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 8. Intel Bus WRITE Mode AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 9. Motorola Bus READ/WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 2. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Time, Calendar, and Alarm Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 10.Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 3. Time, Calendar, and Alarm Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Periodic Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Alarm Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Update Cycle Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Oscillator Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Update Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Square Wave Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 4. Square Wave Frequency/Periodic Interrupt Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3/29
M48T86
Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
UIP. Update in Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
OSC0, OSC1, OSC2. Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
RS3, RS2, RS1, RS0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 5.
REGISTER A MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 11.Update Period Timing and UIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PIE: Periodic Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
AIE: Alarm Interrupt Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
UIE: Update Ended Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
SQWE: Square Wave Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DM: Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
24/12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DSE. Daylight Savings Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 6.
REGISTER B MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 12.Update-ended/Periodic Interrupt Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Register C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18IRQF: Interrupt Request Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PF: Periodic Interrupt Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
AF: Alarm Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
UF: Update Ended Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
BIT 0 through 3: Unused Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Register D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18VRT: Valid Ram And Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
BIT 0 through 6: Unused Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 7.
REGISTER C MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 8.
REGISTER D MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Figure 13.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 10. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 14.AC Testing Load Circuit (No IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 15.AC Testing Load Circuit (with IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 11. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 12. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 16.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 13. Power Down/Up Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 14.
Power Down/Up Trip Points DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Figure 17.PCDIP24 – 24-pin Plastic DIP, battery CAPHAT, Package Outline . . . . . . . . . . . . . . . .23
M48T86Table 15. PCDIP24 – 24-pin Plastic DIP, battery CAPHAT, Package Mechanical Data. . . . . . . . .23
Figure 18.SOH28 – 28-lead Plastic Small Outline, 4-socket SNAPHAT, Package Outline. . . . . . .24
Table 16. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Pack. Mech. Data24
Figure 19.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . .25
Table 17. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . .25
Figure 20.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . .26
Table 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . .26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 20. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5/29
M48T86
SUMMARY DESCRIPTIONThe M48T86 is an industry standard Real Time
Clock (RTC). The M48T86 is composed of a lithi-
um energy source, quartz crystal, write protection
circuitry, and a 128-byte RAM array. This provides
the user with a complete subsystem packaged in
either a 24-pin DIP CAPHAT™ or 28-pin
SNAPHAT® SOIC. Functions available to the user
include a non-volatile time-of-day clock, alarm in-
terrupts, a one-hundred-year clock with program-
mable interrupts, square wave output, and 128
bytes of non-volatile static RAM.
The 24-pin, 600mil DIP CAPHAT houses the
M48T86 silicon with a quartz crystal and a long-life
lithium button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT® housing con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape & Reel
form.
For the 28-lead SOIC, the battery/crystal package
part number is “M4T28-BR12SH” (see Table
20., page 27).
Table 1. Signal Names
M48T86
Figure 6. Block Diagram
7/29
M48T86
OPERATION
Automatic deselection of the device ensures the
data integrity is not compromised should VCC fall
below specified Power-fail Deselect Voltage
(VPFD) levels (see Figure 16., page 22). The auto-
matic deselection of the device remains in effect
upon power up for a period of 200ms (max) after
VCC rises above VPFD, provided that the Real
Time Clock is running and the count-down chain is
not reset. This allows sufficient time for VCC to sta-
bilize and gives the system clock a wake-up period
so that a valid system reset can be established.
The block diagram in Figure 6., page 6 shows the
pin connections and the major internal functions of
the M48T86.
Signal Description
VCC, VSS. DC power is provided to the device on
these pins.The M48T86 uses a 5V VCC.
SQW (Square Wave Output). During normal op-
eration (e.g., valid VCC), the SQW pin can output a
signal from one of 13 taps. The frequency of the
SQW pin can be changed by programming Regis-
ter A as shown in Table 4., page 14. The SQW sig-
nal can be turned on and off using the SQWE Bit
(Register B; Bit 3). The SQW signal is not avail-
able when VCC is less than VPFD.
AD0-AD7 (Multiplexed Bi-Directional Address/
Data Bus). The M48T86 provides a multiplexed
bus in which address and data information share
the same signal path. The bus cycle consists of
two stages; first the address is latched, followed by
the data. Address/Data multiplexing does not slow
the access time of the M48T86, because the bus
change from address to data occurs during the in-
ternal RAM access time. Addresses must be valid
prior to the falling edge of AS (see Figure
7., page 8), at which time the M48T86 latches the
address present on AD0-AD7. Valid WRITE data
must be present and held stable during the latter
portion of the R/W pulse (see Figure 8., page 9). In
a READ cycle, the M48T86 outputs 8 bits of data
during the latter portion of the DS pulse. The
READ cycle is terminated and the bus returns to a
high impedance state upon a high transition on R/
AS (Address Strobe Input). A positive going
pulse on the Address Strobe (AS) input serves to
demultiplex the bus. The falling edge of AS causes
the address present on AD0-AD7 to be latched
within the M48T86.
MOT (Mode Select). The MOT pin offers the flex-
ibility to choose between two bus types (see Fig-
ure 9., page 9). When connected to VCC, Motorola
bus timing is selected. When connected to VSS or
left disconnected, Intel bus timing is selected. The
pin has an internal pull-down resistance of approx-
imately 20KΩ.
DS (Data Strobe Input). The DS pin is also re-
ferred to as READ (RD). A falling edge transition
on the Data Strobe (DS) input enables the output
during a a READ cycle. This is very similar to an
Output Enable (G) signal on other memory devic-
es.
M48T86
E (Chip Enable Input). The Chip Enable pin
must be asserted low for a bus cycle in the
M48T86 to be accessed. Bus cycles which take
place without asserting E will latch the addresses
present, but no data access will occur.
IRQ (Interrupt Request Output). The IRQ pin is
an open drain output that can be used as an inter-
rupt input to a processor. The IRQ output remains
low as long as the status bit causing the interrupt
is present and the corresponding interrupt-enable
bit is set. IRQ returns to a high impedance state
whenever Register C is read. The RST pin can
also be used to clear pending interrupts. The IRQ
bus is an open drain output so it requires an exter-
nal pull-up resistor to VCC.
RST (Reset Input). The M48T86 is reset when
the RST input is pulled low. With a valid VCC ap-
plied and a low on RST, the following events oc-
cur: Periodic Interrupt Enable (PIE) Bit is cleared to
a zero (Register B; Bit 6); Alarm Interrupt Enable (AIE) Bit is cleared to a
zero (Register B; Bit 5); Update Ended Interrupt Request (UF) Bit is
cleared to a zero (Register C; Bit 4); Interrupt Request (IRQF) Bit is cleared to a
zero (Register C Bit 7); Periodic Interrupt Flag (PF) Bit is cleared to a
zero (Register C; Bit 6); The device is not accessible until RST is re-
turned high; Alarm Interrupt Flag (AF) Bit is cleared to a
zero (Register C; Bit 5); The IRQ pin is in the high impedance state Square Wave Output Enable (SQWE) Bit is
cleared to zero (Register B; Bit 3); and
10. Update Ended Interrupt Enable (UIE) is
cleared to a zero (Register B; Bit 4).
RCL (RAM Clear). The RCL pin is used to clear
all 114 storage bytes, excluding clock and control
registers, of the array to FF(hex) value. The array
will be cleared when the RCL pin is held low for at
least 100ms with the oscillator running. Usage of
this pin does not affect battery load. This function
is applicable only when VCC is applied.
R/W (READ/WRITE Input). The R/W pin is used
to latch data into the M48T86 and provides func-
tionality similar to W in other memory systems.
Non-Volatile RAM
The 114 general-purpose non-volatile RAM bytes
are not dedicated to any special function within the
M48T86. They can be used by the processor pro-
gram as non-volatile memory and are fully acces-
sible during the update cycle.
Figure 7. Intel Bus READ AC Waveform
9/29
M48T86
M48T86
Table 2. AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V (except where noted). See Table 4., page14.
11/29
M48T86
CLOCK OPERATIONS
Address Map
The address map of the M48T86 is shown in Fig-
ure 10. It consists of 114 bytes of user RAM, 10
bytes of RAM that contain the RTC time, calendar
and alarm data, and 4 bytes which are used for
control and status. All bytes can be read or written
to except for the following: Registers C & D are “Read only.” Bit 7 of Register A is “Read only.”
The contents of the four Registers A, B, C, and D
are described in the “Registers” section.
Time, Calendar, and Alarm Locations
The time and calendar information is obtained by
reading the appropriate memory bytes. The time,
calendar, and alarm registers are set or initialized
by writing the appropriate RAM bytes. The con-
tents of the time, calendar, and alarm bytes can be
either Binary or Binary-Coded Decimal (BCD) for-
mat. Before writing the internal time, calendar, and
alarm register, the SET Bit (Register B; Bit 7)
should be written to a logic '1.' This will prevent up-
dates from occurring while access is being at-
tempted. In addition to writing the time, calendar,
and alarm registers in a selected format (binary or
BCD), the Data Mode (DM) Bit (Register B; Bit 2),
must be set to the appropriate logic level ('1' signi-
fies binary data; '0' signifies Binary Coded Decimal
(BCD data). All time, calendar, and alarm bytes
must use the same data mode. The SET Bit
should be cleared after the Data Mode Bit has
been written to allow the Real Time Clock to up-
date the time and calendar bytes. Once initialized,
the Real Time Clock makes all updates in the se-
lected mode. The data mode cannot be changed
without reinitializing the ten data bytes. Table
3., page 12 shows the binary and BCD formats of
the time, calendar, and alarm locations. The 24/12
Bit (Register B; Bit 1) cannot be changed without
reinitializing the hour locations. When the 12-hour
format is selected, a logic '1' in the high order bit of
the hours byte represents PM. The time, calendar,
and alarm bytes are always accessible because
they are double-buffered. Once per second the ten
bytes are advanced by one second and checked
for an alarm condition. If a READ of the time and
calendar data occurs during an update, a problem
exists where data such as seconds, minutes, or
hours may not correlate. However, the probability
of reading incorrect time and calendar data is low.
Methods of avoiding possible incorrect time and
calendar READs are reviewed later in this text.
M48T86
Table 3. Time, Calendar, and Alarm Formats
Interrupts
The RTC plus RAM includes three separate, fully
automatic sources of interrupt (alarm, periodic, up-
date-in-progress) available to a processor. The
alarm interrupt can be programmed to occur at
rates from once per second to once per day. The
periodic interrupt can be selected from rates of
500ms to 122µs. The update-ended interrupt can
be used to indicate that an update cycle has com-
pleted.
The processor program can select which inter-
rupts, if any, are going to be used. Three bits in
Register B enable the interrupts. Writing a logic '1'
to an interrupt-enable bit (Register B; Bit 6= PIE;
Bit 5= AIE; Bit 4= UIE) permits an interrupt to be
initialized when the event occurs. A '0' in an inter-
rupt-enable bit prohibits the IRQ pin from being as-
serted from that interrupt condition. If an interrupt
flag is already set when an interrupt is enabled,
IRQ is immediately set at an active level, although
the interrupt initiating the event may have occurred
much earlier. As a result, there are cases where
the program should clear such earlier initiated in-
terrupts before first enabling new interrupts.
When an interrupt event occurs, the related flag bit
(Register C; Bit 6 = PF; Bit 5 = AF; Bit 4 = UF) is
set to a logic '1.' These flag bits are set indepen-
dent of the state of the corresponding enable bit in
Register B and can be used in a polling mode with-
out enabling the corresponding enable bits. The
interrupt flag bits are status bits which software
can interrogate as necessary.
When a flag is set, an indication is given to soft-
ware that an interrupt event has occurred since the
flag bit was last read; however, care should be tak-
en when using the flag bits as all are cleared each
time Register C is read. Double latching is includ-
ed with Register C so that bits which are set re-
main stable throughout the READ cycle. All bits
which are set high are cleared when read. Any
new interrupts which are pending during the READ
cycle are held until after the cycle is completed.
One, two, or three bits can be set when reading
Register C. Each utilized flag bit should be exam-
ined when read to ensure that no interrupts are
lost.
The second flag bit usage method is with fully en-
abled interrupts. When an interrupt flag bit is set
and the corresponding enable bit is also set, the
IRQ pin is asserted low. IRQ is asserted as long as
at least one of the three interrupt sources has its
flag and enable bits both set. The IRQF Bit (Reg-
ister C; Bit 7) is a '1' whenever the IRQ pin is being
driven low. Determination that the RTC initiated an
interrupt is accomplished by reading Register C. A
logic '1' in the IRQF Bit indicates that one or more
interrupts have been initiated by the M48T86. The
act of reading Register C clears all active flag bits
and the IRQF Bit.
13/29
M48T86
Periodic Interrupt
The periodic interrupt will cause the IRQ pin to go
to an active state from once every 500ms to once
every 122µs. This function is separate from the
alarm interrupt which can be output from once per
second to once per day. The periodic interrupt rate
is selected using the same Register A bits which
select the square wave frequency (see Table
4., page 14). Changing the Register A bits affects
both the square wave frequency and the periodic
interrupt output. However, each function has a
separate enable bit in Register B. The periodic in-
terrupt is enabled by the PIE Bit (Register B; Bit 6).
The periodic interrupt can be used with software
counters to measure inputs, create output inter-
vals, or await the next needed software function.
Alarm Interrupt
The alarm interrupt provides the system processor
with an interrupt when a match is made between
the RTC's hours, minutes, and seconds bytes and
the corresponding alarm bytes.
The three alarm bytes can be used in two ways.
First, when the alarm time is written in the appro-
priate hours, minutes, and seconds alarm loca-
tions, the alarm interrupt is initiated at the specified
time each day if the Alarm Interrupt Enable Bit
(Register B; Bit 5) is high. The second use is to in-
sert a “Don't care” state in one or more of the three
alarm bytes. The “Don't care” code is any hexa-
decimal value from C0 to FF. The two most signif-
icant bits of each byte set the “Don't care”
condition when at logic '1.' An alarm will be gener-
ated each hour when the “Don't care” is are set in
the hours byte. Similarly, an alarm is generated
every minute with “Don't care” codes in the hour
and minute alarm bytes. The “Don't care” codes in
all three alarm bytes create an interrupt every sec-
ond.
Update Cycle Interrupt
After each update cycle, the Update Cycle Ended
Flag Bit (UF) (Register C; Bit 4) is set to a '1.' If the
Update Interrupt Enable Bit (UIE) (Register B; Bit
4) is set to a '1,' and the SET Bit (Register B; Bit 7)
is a '0,' then an interrupt request is generated at
the end of each update cycle.
Oscillator Control Bits
When the M48T86 is shipped from the factory the
internal oscillator is turned off. This feature pre-
vents the lithium energy cell from being dis-
charged until it is installed in a system. A pattern of
“010” in Bits 4-6 of Register A will turn the oscillator
on and enable the countdown chain. A pattern of
“11X” will turn the oscillator on, but holds the
countdown chain of the oscillator in reset. All other
combinations of Bits 4-6 keep the oscillator off.
Update Cycle
The M48T86 executes an update cycle once per
second regardless of the SET Bit (Register B; Bit
7). When the SET Bit is asserted, the user copy of
the double buffered time, calendar, and alarm
bytes is frozen and will not update as the time in-
crements. However, the time countdown chain
continues to update the internal copy of the buffer.
This feature allows accurate time to be main-
tained, independent of reading and writing the
time, calendar, and alarm buffers. This also guar-
antees that the time and calendar information will
be consistent. The update cycle also compares
each alarm byte with the corresponding time byte
and issues an alarm if a match or if a “Don't care”
code is present in all three positions.
There are three methods of accessing the real
time clock that will avoid any possibility of obtain-
ing inconsistent time and calendar data. The first
method uses the update-ended interrupt. If en-
abled, an interrupt occurs after every update cycle
which indicates that over 999ms are available to
read valid time and date information. If this inter-
rupt is used, the IRQF Bit (Register C; Bit 7) should
be cleared before leaving the interrupt routine.
A second method uses the Update-In-Progress
(UIP) Bit (Register A; Bit 7) to determine if the up-
date cycle is in progress. The UIP Bit will pulse
once per second. After the UIP Bit goes high, the
update transfer occurs 244µs later. If a low is read
on the UIP Bit, the user has at least 244µs before
the time/calendar data will be changed. Therefore,
the user should avoid interrupt service routines
that would cause the time needed to read valid
time/calendar data to exceed 244µs.
The third method uses a periodic interrupt to deter-
mine if an update cycle is in progress. The UIP Bit
is set high between the setting of the PF Bit (Reg-
ister C; Bit 6). Periodic interrupts that occur at a
rate greater than tBUC allow valid time and date in-
formation to be reached at each occurrence of the
periodic interrupt.The READs should be complet-
ed within 1/(tPL/2 + tBUC) to ensure that data is not
read during the update cycle.
M48T86
Square Wave Output Selection
Thirteen of the 15 divider taps are made available
to a 1-of-15 selector, as shown in the block dia-
gram of Figure 6., page 6. The purpose of select-
ing a divider tap is to generate a square wave
output signal on the SQW pin. The RS3-RS0 bits
in Register A establish the square wave output fre-
quency. These frequencies are listed in Table
4., page 14. The SQW frequency selection shares
the 1-of-15 selector with the periodic interrupt gen-
erator. Once the frequency is selected, the output
of the SQW pin can be turned on and off under
program control with the Square Wave Enabled
(SQWE) Bit.
Table 4. Square Wave Frequency/Periodic Interrupt Rate
15/29
M48T86
Register A
UIP. Update in Progress. The Update in
Progress (UIP) Bit is a status flag that can be mon-
itored. When the UIP Bit is '1,' the update transfer
will soon occur (see Figure 11). When UIP is a '0,'
the update transfer will not occur for at least
244µs. The time, calendar, and alarm information
in RAM is fully available for access when the UIP
Bit is '0.' The UIP Bit is “Read only” and is not af-
fected by RST. Writing the SET Bit in Register B to
a '1' inhibits any update transfer and clears the UIP
Status Bit.
OSC0, OSC1, OSC2. Oscillator Control. These
three bits are used to control the oscillator and re-
set the countdown chain. A pattern of “010” en-
ables operation by turning on the oscillator and
enabling the divider chain. A pattern of 11X turns
the oscillator on, but keeps the frequency divider
disabled. When “010” is written, the first update
begins after 500ms.
RS3, RS2, RS1, RS0. These four rate-selection
bits select one of the 13 taps on the 15-stage di-
vider or disable the divider output. The tap select-
ed may be used to generate an output square
wave (SQW pin) and/or a periodic interrupt. The
user may do one of the following: Enable the interrupt with the PIE Bit; Enable the SQW output with the SQWE Bit; Enable both at the same time and same rate;
or Enable neither.
Table 4., page 14 lists the periodic interrupt rates
and the square wave frequencies that may be cho-
sen with the RS Bits. These four READ/WRITE
bits are not affected by RST.
