M48T86 ,5 VOLT PC REAL TIME CLOCKAbsolute Maximum Ratings(Table2.) .... ...... ....... ...... ....... ...... ...... .....6DC AND AC ..
M48T86MH1 ,5 VOLT PC REAL TIME CLOCKBlock Diagram . . 6OPERATION . . . . . . 7Signal Description . . . . . . 7V , ..
M48T86-MH1 ,5 VOLT PC REAL TIME CLOCKFEATURES SUMMARY■ DROP-IN REPLACEMENT FOR PC Figure 1. 24-pin PCDIP, CAPHAT™ PackageCOMPUTER CLOCK/ ..
M48T86-MH1 ,5 VOLT PC REAL TIME CLOCKAbsolute Maximum Ratings . . . . . . . 20DC AND AC PARAMETERS . 21Table 10. Operating and ..
M48T86-MH1 ,5 VOLT PC REAL TIME CLOCKLogic Diagram . . 5Table 1. Signal Names . . 5Figure 4. 24-pin DIP Connections . ..
M48T86MH1E ,5 VOLT PC REAL TIME CLOCKM48T865.0V PC Real-Time Clock
M61516FP , MITSUBISHI SOUND PROCESSOR ICs 7.1ch ELECTRONIC VOLUME WITH 10 INPUT SELECTOR
M61516FP , MITSUBISHI SOUND PROCESSOR ICs 7.1ch ELECTRONIC VOLUME WITH 10 INPUT SELECTOR
M61523FP , Electronic Volume with Scf Type Tone Control To 6 Speakers
M61523FP , Electronic Volume with Scf Type Tone Control To 6 Speakers
M61538FP , 6-Channel Electronic Volume
M61538FP , 6-Channel Electronic Volume
M48T86
5 VOLT PC REAL TIME CLOCK
1/28May 2002
M48T865.0V PC REAL TIME CLOCK
FEATURES SUMMARY DROP-IN REPLACEMENT FOR PC
COMPUTER CLOCK/CALENDAR COUNTS SECONDS, MINUTES, HOURS,
DAYS, DAY OF THE WEEK, DATE, MONTH,
and YEAR WITH LEAP YEAR
COMPENSATION INTERFACED WITH SOFTWARE AS 128
RAM LOCATIONS: 14 Bytesof Clock and Control Registers 114 Bytesof General Purpose RAM SELECTABLE BUS TIMING (Intel/Motorola) THREE INTERRUPTS ARE SEPARATELY
SOFTWARE-MASKABLE and TESTABLE Time-of-Day Alarm (Once/Secondto
Once/Day) Periodic Rates from 122μsto 500ms End-of-Clock Update Cycle PROGRAMMABLE SQUARE WAVE OUTPUT 10 YEARS OF DATA RETENTION AND
CLOCK OPERATIONIN THE ABSENCE OF
POWER SELF-CONTAINED BATTERY and CRYSTAL THE CAPHAT DIP PACKAGE PACKAGINGINCLUDESA 28-LEAD SOIC and
SNAPHAT® TOP(tobe Ordered Separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION FORA SNAPHAT TOP
CONTAINS THE BATTERY and CRYSTAL PIN and FUNCTION COMPATIBLE WITH
bq3285/7A and DS12887
M48T862/28
TABLE OF CONTENTS
SUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... .....4Logic Diagram (Figure 3.). ...... ....... ...... ....... ...... ....... ...... ...... .....4
Signal Names (Table1.).. ...... ....... ...... ....... ...... ....... ...... ...... .....4
24-pin DIP Connections (Figure 4.)....... ...... ....... ...... ....... ...... ...... .....5
28-pin SOIC Connections (Figure5.) ..... ...... ....... ...... ....... ...... ...... .....5
Block Diagram (Figure6.). ...... ....... ...... ....... ...... ....... ...... ...... .....5
MAXIMUM RATING... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....6Absolute Maximum Ratings (Table2.) .... ...... ....... ...... ....... ...... ...... .....6
AND AC PARAMETERS.. ...... ....... ...... ....... ...... ....... ...... ...... .....7Operating and AC Measurement Conditions (Table 3.) .... ...... ....... ...... ...... .....7 Testing Load Circuit (No IRQ) (Figure 7.) ..... ....... ...... ....... ...... ...... .....7 Testing Load Circuit (with IRQ) (Figure8.) .... ....... ...... ....... ...... ...... .....7
Capacitance (Table4.)... ...... ....... ...... ....... ...... ....... ...... ...... .....7 Characteristics (Table5.) .... ....... ...... ....... ...... ....... ...... ...... .....8
OPERATION. ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....8Signal Description. ...... ...... ....... ...... ....... ...... ....... ...... ...... .....8
Non-Volatile RAM. ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Intel Bus READ AC Waveform (Figure 9.).. ...... ....... ...... ....... ...... ...... .....9
Intel Bus WRITE Mode AC Waveform (Figure 10.). ....... ...... ....... ...... ...... ....10
Motorola BusREAD/WRITE Mode AC Waveforms(Figure 11.) .... ....... ...... ...... ....10 Characteristics(Table 6.) .... ....... ...... ....... ...... ....... ...... ...... ....11
CLOCKOPERATIONS ...... ...... ....... ...... ....... ...... ....... ...... ...... ....12Address Map ..... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....12
Time, Calendar, and Alarm Locations ..... ...... ....... ...... ....... ...... ...... ....12
Address Map (Figure 12.). ...... ....... ...... ....... ...... ....... ...... ...... ....12
Time, Calendar, and Alarm Formats (Table 7.).... ....... ...... ....... ...... ...... ....13
Interrupts. ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....13
PeriodicInterrupt.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....14
Alarm Interrupt.... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....14
Update Cycle Interrupt.... ...... ....... ...... ....... ...... ....... ...... ...... ....14
Oscillator Control Bits .... ...... ....... ...... ....... ...... ....... ...... ...... ....14
Update Cycle ..... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....14
Power Down/Up Mode AC Waveforms (Figure 13.) ....... ...... ....... ...... ...... ....15
Power Down/Up Mode AC Characteristics(Table 8.) ...... ...... ....... ...... ...... ....15
Power Down/Up Trip Points DC Characteristics (Table 9.).. ...... ....... ...... ...... ....15
Square Wave Output Selection ... ....... ...... ....... ...... ....... ...... ...... ....16
Square Wave Frequency/Periodic Interrupt Rate (Table 10.) ...... ....... ...... ...... ....16
3/28
M48T86RegisterA ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....17
REGISTERA (Table 11.). ...... ....... ...... ....... ...... ....... ...... ...... ....17
Update Period Timing and UIP (Figure 14.) ...... ....... ...... ....... ...... ...... ....17
RegisterB ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....18
24/12 .... ....... ...... ...... ....... ...... ....... ...... ....... ........ .... ....18
DSE. Daylight Savings Enable... ....... ...... ....... ...... ....... ...... ...... ....18
REGISTERB (Table 12.). ...... ....... ...... ....... ...... ....... ...... ...... ....18
Update-ended/Periodic Interrupt Relationship (Figure 15.).. ...... ....... ...... ...... ....19
RegisterC ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....20
RegisterD ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....20
REGISTER C(Table 13.). ...... ....... ...... ....... ...... ....... ...... ...... ....20
REGISTER D(Table 14.). ...... ....... ...... ....... ...... ....... ...... ...... ....20
VCC Noise And Negative Going Transients. ...... ....... ...... ....... ...... ...... ....21
Supply Voltage Protection (Figure 16.) .... ...... ....... ...... ....... ...... ...... ....21
PART NUMBERING.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....22SNAPHAT BatteryTable (Table 16.)...... ...... ....... ...... ....... ...... ...... ....22
PACKAGE MECHANICAL INFORMATION... ...... ....... ...... ....... ...... ...... ....23
REVISION HISTORY.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....27
M48T864/28
SUMMARY DESCRIPTIONThe M48T86is an industry standard Real Time
Clock (RTC). The M48T86is composedofa lithi- energy source, quartz crystal, write protection
circuitry, anda 128-byte RAM array. This provides
the user witha complete subsystem packagedin
either a 24-pin DIP CAPHAT™ or 28-pin
SNAPHAT® SOIC. Functions availableto the user
includea non-volatile time-of-day clock, alarmin-
terrupts,a one-hundred-year clock with program-
mable interrupts, square wave output, and 128
bytesof non-volatile static RAM.
The 24-pin, 600mil DIP CAPHAT houses the
M48T86 silicon witha quartz crystal anda long-life
lithium button cellina single package.
The 28-pin, 330mil SOIC provides sockets with
gold plated contactsat both ends for direct con-
nectiontoa separate SNAPHAT® housing con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on topof the SOIC package after the
completionof the surface mount process.
Insertionof the SNAPHAT housing after reflow
prevents potential battery and crystal damage due the high temperatures required for device sur-
face-mounting. The SNAPHAT housingis keyed prevent reverse insertion.
The SOIC and battery packages are shipped sep-
aratelyin plastic anti-static tubesorin Tape& Reel
form.
For the 28-lead SOIC, the battery/crystal package
part numberis “M4T28-BR12SH” (see Table 16,
page 22).
Table1. Signal Names
5/28
M48T86
Figure6. Block Diagram
M48T86
6/28
MAXIMUM RATING
Stressing the deviceabove therating listedinthe
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operationof the deviceat
theseor any other conditions above those indicat-in the Operating sectionsof this specificationis
not implied. Exposureto Absolute Maximum Rat-
ing conditionsfor extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table2. Absolute Maximum Ratings
Note:1. ForDIP package: Soldering temperaturenotto exceed 260°Cfor 10seconds (total thermal budgetnotto exceed 150°Cfor longer
than30 seconds). ForSO package: Reflowat peak temperatureof 215°Cto 225°Cfor<60 seconds (total thermal budgetnotto exceed 180°Cfor
between90to 120 seconds).
CAUTION: Negative undershoots below –0.3Varenot allowedonanypin whileinthe Battery Back-up mode.
CAUTION:Do NOT wave solder SOICto avoid damaging SNAPHAT sockets.
7/28
M48T86 AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristicsof the device. The parametersin
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listedin the relevant tables. De-
signers should check that the operating conditions their projects match the measurement condi-
tions when using the quoted parameters.
Table3. Operating and AC Measurement Conditions
Note: Output Hi-Zis definedasthe point where dataisno longer driven.
Table4. Capacitance
Note:1. Effective capacitance measured with power supplyat5V; sampled only,not 100% tested.At 25°C,f= 1MHz. Outputs deselected.
M48T86
8/28
Table5. DC Characteristics
Note:1. Validfor Ambient Operating Temperature:TA =0to 70°C; VCC=4.5to 5.5V (except where noted). Outputs deselected.
OPERATION
Automatic deselectionof the device ensures the
data integrityis not compromised should VCC fall
below specified Power-fail Deselect Voltage
(VPFD) levels (see Figure 13, page 15). The auto-
matic deselectionof the device remainsin effect
upon power up fora periodof 200ms (max) after
VCC rises above VPFD, provided that the Real
Time Clockis running and the count-down chainis
not reset. This allows sufficient timefor VCCto sta-
bilize and gives the system clocka wake-up period thata valid system reset canbe established.
The block diagramin Figure6, page5 shows the
pin connections and the major internal functionsof
the M48T86.
Signal Description
VCC,VSS. DC poweris providedto the deviceon
these pins.The M48T86 usesa 5V VCC.
SQW (Square Wave Output). During normal op-
eration (e.g., valid VCC), the SQW pin can outputa
signal from oneof 13 taps. The frequencyof the
SQW pin canbe changedby programming Regis-
terAas shownin Table 10, page 16. The SQW
signal can be turnedon and off using the SQWE
Bit (RegisterB;Bit3). The SQW signalis not avail-
able when VCCis less than VPFD.
AD0-AD7 (Multiplexed Bi-Directional Address/
Data Bus). The M48T86 providesa multiplexed
busin which address and data information share
the same signal path. The bus cycle consistsof
two stages; first the addressis latched, followedby
the data. Address/Data multiplexing does not slow
the access timeof the M48T86, because the bus
change from addressto data occurs during thein-
ternal RAM access time. Addresses mustbe valid
priorto the falling edgeof AS (see Figure9, page
9),at which time the M48T86 latches the address
presenton AD0-AD7. Valid WRITE data mustbe
present and held stable during the latter portionof
the R/W pulse (see Figure 10, page 10).Ina
READ cycle, the M48T86 outputs8 bitsof data
during the latter portionof the DS pulse. The
READ cycleis terminated and the bus returnstoa
high impedance state upona high transitiononR/ (Address Strobe Input).A positive going
pulse on the Address Strobe (AS) input servesto
demultiplex the bus. The falling edgeof AS causes
the address present on AD0-AD7to be latched
within the M48T86.
MOT (Mode Select). TheMOT pinoffers theflex-
ibilityto choose between two bus types (see Fig-
ure 11, page 10). When connected to VCC,
Motorola bus timingis selected. When connected VSSor left disconnected, Intel bus timingis se-
lected. The pin has an internal pull-down resis-
tanceof approximately 20KΩ. (Data Strobe Input). The DS pinis also re-
ferredtoas READ (RD).A falling edge transition the Data Strobe (DS) input enables the output
duringaa READ cycle. Thisis very similartoan
Output Enable (G) signalon other memory devic-
es.
9/28
M48T86 (Chip Enable Input). The Chip Enable pin
must be asserted low fora bus cyclein the
M48T86to be accessed. Bus cycles which take
place without assertingE will latch the addresses
present, butno data access will occur.
IRQ (Interrupt Request Output). The IRQ pinis open drain output that canbe usedasan inter-
rupt inputtoa processor. The IRQ output remains
lowas longas the statusbit causing the interrupt present and the corresponding interrupt-enable
bitis set. IRQ returnstoa high impedance state
whenever RegisterCis read. The RST pin can
alsobe usedto clear pending interrupts. The IRQ
busisan open drain outputsoit requiresan exter-
nal pull-up resistorto VCC.
RST (Reset Input). The M48T86is reset when
the RST inputis pulled low. Witha valid VCC ap-
plied anda low on RST, the following events oc-
cur: Periodic Interrupt Enable (PIE) Bitis clearedto zero (RegisterB;Bit6); Alarm Interrupt Enable (AIE) Bitis clearedtoa
zero (RegisterB; Bit5); Update Ended Interrupt Request (UF) Bitis
clearedtoa zero (RegisterC;Bit 4); Interrupt Request (IRQF)Bitis clearedtoa zero
(RegisterCBit 7); Periodic Interrupt Flag (PF) Bitis clearedtoa
zero (RegisterC;Bit6); The deviceis not accessible until RSTis re-
turned high; Alarm Interrupt Flag (AF)Bitis clearedtoa zero
(RegisterC;Bit5); The IRQ pinisin the high impedance state Square Wave Output Enable (SQWE) Bitis
clearedto zero (RegisterB;Bit 3); and
10.Update Ended Interrupt Enable (UIE)is cleared azero(RegisterB;Bit4).
RCL (RAM Clear). The RCL pinis usedtoclear
all 114 storage bytes, excluding clock and control
registers,of the arrayto FF(hex) value. The array
willbe cleared when the RCL pinis held lowforat
least 100ms with the oscillator running. Usageof
this pin does not affect battery load. This function applicable only when VCCis applied.
R/W (READ/WRITE Input). The R/W pinis used latch data into the M48T86 and provides func-
tionality similartoWin other memory systems.
Non-Volatile RAM
The 114 general-purpose non-volatile RAM bytes
are not dedicatedto any special function within the
M48T86. They canbe usedby the processor pro-
gramas non-volatile memory and are fully acces-
sible during the update cycle.
Figure9. Intel Bus READ AC Waveform
M48T86
10/28
11/28
M48T86
Table6. AC Characteristics
Note:1. Validfor Ambient Operating Temperature:TA =0to 70°C; VCC=4.5to 5.5V (except where noted). See Table10, page16.
M48T86
12/28
CLOCK OPERATIONS
Address Map
The address mapof the M48T86is shownin Fig-
ure 12.It consistsof 114 bytesof user RAM, 10
bytesof RAM that contain the RTC time, calendar
and alarm data, and4 bytes which are used for
control and status.All bytes canbe reador written except for the following: RegistersC&D are “Read only.”Bit7of RegisterAis “Read only.”
The contentsof the four RegistersA,B,C, andD
are describedin the “Registers” section.
Time, Calendar, and Alarm Locations
The time and calendar informationis obtainedby
reading the appropriate memory bytes. The time,
calendar, and alarm registers are setor initialized writing the appropriate RAM bytes. The con-
tentsof the time, calendar, and alarm bytes canbe
either Binaryor Binary-Coded Decimal (BCD) for-
mat. Before writing the internal time, calendar, and
alarm register, the SET Bit (Register B; Bit7)
shouldbe writtentoa logic '1.' This will prevent up-
dates from occurring while accessis being at-
tempted.In additionto writing the time, calendar,
and alarm registersina selected format (binaryor
BCD), the Data Mode (DM) Bit (RegisterB; Bit2),
mustbe setto the appropriate logic level ('1' signi-
fies binary data;'0' signifies Binary Coded Decimal
(BCD data). All time, calendar, and alarm bytes
must use the same data mode. The SET Bit
should be cleared after the Data Mode Bit has
been writtento allow the Real Time Clockto up-
date the time and calendar bytes. Once initialized,
the Real Time Clock makesall updatesin the se-
lected mode. The data mode cannotbe changed
without reinitializing the ten data bytes. Table7,
page13 shows the binary and BCD formatsof the
time, calendar, and alarm locations. The 24/12Bit
(RegisterB;Bit1) cannotbe changed without rein-
itializing the hour locations. When the 12-hour for-
matis selected,a logic'1'in the high order bitof
the hours byte represents PM. The time, calendar,
and alarm bytes are always accessible because
they are double-buffered. Once per second the ten
bytes are advancedby one second and checked
for an alarm condition.Ifa READof the time and
calendar data occurs duringan update,a problem
exists where data such as seconds, minutes,or
hours may not correlate. However, the probability reading incorrect time and calendar datais low.
Methodsof avoiding possible incorrect time and
calendar READs are reviewed laterin this text.
13/28
M48T86
Table7. Time, Calendar, and Alarm Formats
Interrupts
The RTC plus RAM includes three separate, fully
automatic sourcesof interrupt (alarm, periodic, up-
date-in-progress) availabletoa processor. The
alarm interrupt can be programmedto occurat
rates from once per secondto once per day. The
periodic interrupt can be selected from ratesof
500msto 122μs. The update-ended interrupt can usedto indicate thatan update cycle has com-
pleted.
The processor program can select which inter-
rupts,if any, are goingto be used. Three bitsin
RegisterB enable the interrupts. Writinga logic'1'an interrupt-enablebit (RegisterB; Bit6= PIE;
Bit5= AIE; Bit4= UIE) permitsan interrupttobe
initialized when the event occurs.A'0'in an inter-
rupt-enablebit prohibits the IRQ pin from being as-
serted from that interrupt condition.Ifan interrupt
flagis already set when an interruptis enabled,
IRQis immediately setatan active level, although
the interrupt initiating the event may have occurred
much earlier. Asa result, there are cases where
the program should clear such earlier initiatedin-
terrupts before first enabling new interrupts.
Whenan interrupt event occurs, the related flagbit
(RegisterC; Bit6= PF; Bit5= AF; Bit4= UF)is
settoa logic '1.' These flag bits are set indepen-
dentof the stateof the corresponding enablebitin
RegisterB and canbe usedina polling mode with-
out enabling the corresponding enable bits. The
interrupt flag bits are status bits which software
can interrogateas necessary.
Whena flagis set, an indicationis givento soft-
ware thatan interrupt event has occurred since the
flagbit was last read; however, care shouldbe tak- when using the flag bitsasall are cleared each
time RegisterCis read. Double latchingis includ- with RegisterCso that bits which are set re-
main stable throughout the READ cycle. All bits
which are set high are cleared when read. Any
new interrupts which are pending during the READ
cycle are held until after the cycleis completed.
One, two,or three bits can be set when reading
RegisterC. Each utilized flagbit should be exam-
ined when readto ensure that no interrupts are
lost.
The second flagbit usage methodis with fully en-
abled interrupts. When an interrupt flagbitis set
and the corresponding enable bitis also set, the
IRQ pinis asserted low. IRQis assertedas longas least oneof the three interrupt sources hasits
flag and enable bits both set. The IRQF Bit (Reg-
isterC;Bit7)isa'1' whenever the IRQ pinis being
driven low. Determination that the RTC initiatedan
interruptis accomplishedby reading RegisterC.A
logic'1'in the IRQF Bit indicates that oneor more
interrupts have been initiatedby the M48T86. The
actof reading RegisterC clearsall active flag bits
and the IRQF Bit.
M48T86
14/28
Periodic Interrupt
The periodic interrupt will cause the IRQ pintogoan active state from once every 500msto once
every 122μs. This functionis separate from the
alarm interrupt which canbe output from once per
secondto once per day. The periodic interrupt rate selected using the same RegisterA bits which
select the square wave frequency (see Table 10,
page 16). Changing the RegisterA bits affects
both the square wave frequency and the periodic
interrupt output. However, each function hasa
separate enablebitin RegisterB. The periodicin-
terruptis enabledby the PIEBit (RegisterB;Bit6).
The periodic interrupt can be used with software
countersto measure inputs, create output inter-
vals,or await the next needed software function.
Alarm Interrupt
The alarm interrupt provides the system processor
with an interrupt whena matchis made between
the RTC's hours, minutes, and seconds bytes and
the corresponding alarm bytes.
The three alarm bytes can be usedin two ways.
First, when the alarm timeis writtenin the appro-
priate hours, minutes, and seconds alarm loca-
tions, the alarm interruptis initiatedat the specified
time each dayif the Alarm Interrupt Enable Bit
(RegisterB;Bit5)is high. The second useistoin-
serta “Don't care” statein oneor moreof the three
alarm bytes. The “Don't care” codeis any hexa-
decimal value from C0to FF. The two most signif-
icant bits of each byte set the “Don't care”
condition whenat logic '1.' An alarm willbe gener-
ated each hour when the “Don't care”is are setin
the hours byte. Similarly, an alarmis generated
every minute with “Don't care” codesin the hour
and minute alarm bytes. The “Don't care” codesin
all three alarm bytes createan interrupt every sec-
ond.
Update Cycle Interrupt
After each update cycle, the Update Cycle Ended
FlagBit (UF) (RegisterC;Bit4)is settoa '1.'If the
Update Interrupt Enable Bit (UIE) (RegisterB; Bitis settoa'1,' and the SETBit (RegisterB;Bit7)a '0,' then an interrupt requestis generatedat
the endof each update cycle.
Oscillator Control Bits
When the M48T86is shipped from the factory the
internal oscillatoris turned off. This feature pre-
vents the lithium energy cell from being dis-
charged untilitis installedina system.A patternof
“010”in Bits 4-6of RegisterA will turn the oscillator and enable the countdown chain.A patternof
“11X” will turn the oscillator on, but holds the
countdown chainof the oscillatorin reset.All other
combinationsof Bits 4-6 keep the oscillator off.
Update Cycle
The M48T86 executesan update cycle once per
second regardlessof the SET Bit (RegisterB; Bit
7). When the SET Bitis asserted, the user copyof
the double buffered time, calendar, and alarm
bytesis frozen and will not updateas the timein-
crements. However, the time countdown chain
continuesto update the internal copyof the buffer.
This feature allows accurate timeto be main-
tained, independentof reading and writing the
time, calendar, and alarm buffers. This also guar-
antees that the time and calendar information will consistent. The update cycle also compares
each alarm byte with the corresponding time byte
and issuesan alarmifa matchorifa “Don't care”
codeis presentinall three positions.
There are three methodsof accessing the real
time clock that will avoid any possibilityof obtain-
ing inconsistent time and calendar data. The first
method uses the update-ended interrupt.If en-
abled,an interrupt occurs after every update cycle
which indicates that over 999ms are availableto
read valid time and date information.If this inter-
ruptis used, the IRQFBit (RegisterC;Bit7) should cleared before leaving the interrupt routine. second method uses the Update-In-Progress
(UIP)Bit (RegisterA;Bit7)to determineif the up-
date cycleisin progress. The UIP Bit will pulse
once per second. After the UIP Bit goes high, the
update transfer occurs 244μs later.Ifa lowis read the UIP Bit, the user hasat least 244μs before
the time/calendar data willbe changed. Therefore,
the user should avoid interrupt service routines
that would cause the time neededto read valid
time/calendar datato exceed 244μs.
The third method usesa periodic interruptto deter-
mineifan update cycleisin progress. The UIPBit set high between the settingof the PFBit (Reg-
isterC; Bit 6). Periodic interrupts that occurata
rate greater than tBUC allow valid time and datein-
formationtobe reachedat each occurrenceof the
periodic interrupt.The READs should be complet- within 1/(tPL/2 +tBUC)to ensure that datais not
read during the update cycle.
