M48T59Y-70PC1D ,64 Kbit (8Kb X8) TIMEKEEPER SRAMFEATURES SUMMARY . . . . . 1Figure 1. 28-pin PCDIP, CAPHAT™ Package . 1Figure 2. 28-pin ..
M48T59Y-70PC1DS ,64 Kbit (8Kb X8) TIMEKEEPER SRAMFEATURES SUMMARY■ INTEGRATED ULTRA LOW POWER SRAM, Figure 1. 28-pin PCDIP, CAPHAT™ PackageREAL TIME ..
M48T86 ,5 VOLT PC REAL TIME CLOCKAbsolute Maximum Ratings(Table2.) .... ...... ....... ...... ....... ...... ...... .....6DC AND AC ..
M48T86MH1 ,5 VOLT PC REAL TIME CLOCKBlock Diagram . . 6OPERATION . . . . . . 7Signal Description . . . . . . 7V , ..
M48T86-MH1 ,5 VOLT PC REAL TIME CLOCKFEATURES SUMMARY■ DROP-IN REPLACEMENT FOR PC Figure 1. 24-pin PCDIP, CAPHAT™ PackageCOMPUTER CLOCK/ ..
M48T86-MH1 ,5 VOLT PC REAL TIME CLOCKAbsolute Maximum Ratings . . . . . . . 20DC AND AC PARAMETERS . 21Table 10. Operating and ..
M61511FP , AUDIO SIGNAL PROCESSOR
M61511FP , AUDIO SIGNAL PROCESSOR
M61512FP , 5.1ch Electronic Volume
M61512FP , 5.1ch Electronic Volume
M61516FP , MITSUBISHI SOUND PROCESSOR ICs 7.1ch ELECTRONIC VOLUME WITH 10 INPUT SELECTOR
M61516FP , MITSUBISHI SOUND PROCESSOR ICs 7.1ch ELECTRONIC VOLUME WITH 10 INPUT SELECTOR
M48T59Y-70MH1-M48T59Y-70PC1-M48T59Y-70PC1D-M48T59Y-70PC1DS
64 Kbit (8Kb X8) TIMEKEEPER SRAM
1/29November 2004
M48T59
M48T59Y, M48T59V*5.0 or 3.3V, 64 Kbit (8 Kbit x8) TIMEKEEPER® SRAM
* Contact local ST sales office for availability of 3.3V version.
FEATURES SUMMARY INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, AND BATTERY FREQUENCY TEST OUTPUT FOR REAL
TIME CLOCK SOFTWARE CALIBRATION AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage): M48T59: VCC = 4.75 to 5.5V
4.5V ≤ VPFD ≤ 4.75V M48T59Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V M48T59V*: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V SELF-CONTAINED BATTERY AND
CRYSTAL IN THE CAPHAT™ DIP
PACKAGE PACKAGING INCLUDES A 28-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY AND
CRYSTAL MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT
ACTIVE IN THE BATTERY BACK-UP MODE BATTERY LOW FLAG
M48T59, M48T59Y, M48T59V*
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 28-pin PCDIP, CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. PCDIP28 CAPHAT Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Figure 10.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 11.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 12.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 6. Alarm Repeat Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 13.Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Programmable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Battery Low Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table 7. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 14.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3/29
M48T59, M48T59Y, M48T59V*
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 15.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 16.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 12. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 13. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Figure 17.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline . . . . . . . . . . . . . . . .23
Table 14. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data. . . . . . . . .23
Figure 18.SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline . . . . . . . .24
Table 15. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Pack. Mech. Data . . . . . . .24
Figure 19.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . .25
Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . .25
Figure 20.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . .26
Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . .26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 19. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
M48T59, M48T59Y, M48T59V*
SUMMARY DESCRIPTIONThe M48T59/Y/V TIMEKEEPER® RAM is an Kb x8 non-volatile static RAM and real time
clock. The monolithic chip is available in two spe-
cial packages to provide a highly integrated bat-
tery backed-up memory and real time clock
solution.
The M48T59/Y/V is a non-volatile pin and function
equivalent to any JEDEC standard 8 Kb x8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The 28-pin, 600mil DIP CAPHAT™ houses the
M48T59/Y/V silicon with a quartz crystal and a
long life lithium button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT® housing con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28-lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is “M4T28-BR12SH” or “M4T32-BR12SH”
(see Table 19., page 27).
Caution: Do not place the SNAPHAT battery/crys-tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
Table 1. Signal Names
5/29
M48T59, M48T59Y, M48T59V*
Figure 6. Block Diagram
M48T59, M48T59Y, M48T59V*
OPERATION MODES
As Figure 6., page 5 shows, the static memory ar-
ray and the quartz-controlled clock oscillator of the
M48T59/Y/V are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with
addresses 1FF8h-1FFFh. The clock locations
contain the century, year, month, date, day, hour,
minute, and second in 24 hour BCD format (except
for the century). Corrections for 28, 29 (leap year -
valid until 2100), 30, and 31 day months are made
automatically. Byte 1FF8h is the clock control reg-
ister. This byte controls user access to the clock
information and also stores the clock calibration
setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ READ/WRITE memory
cells. The M48T59/Y/V includes a clock control cir-
cuit which updates the clock bytes with current in-
formation once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T59/Y/V also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single 5V/3.3V supply for an out of
tolerance condition. When VCC is out of tolerance,
the circuit write protects the SRAM, providing a
high degree of data security in the midst of unpre-
dictable system operation brought on by low VCC.
As VCC falls below the Battery Back-up Switchover
Voltage (VSO), the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
Table 2. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. See Table 13., page 22 for details.
7/29
M48T59, M48T59Y, M48T59V*
READ Mode
The M48T59/Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 13 ad-
dress inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (tAVQV) after the last address input signal is
stable, providing that the E and G access times
are also satisfied. If the E and G access times are
not met, valid data will be available after the latter
of the Chip Enable Access time (tELQV) or Output
Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
Figure 7. READ Mode AC Waveforms
Note: WRITE Enable (W) = High.
Table 3. READ Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V, 4.75 to 5.5V, or 3.0 to 3.6V (except where noted). CL = 100pF (see Figure 15., page 20). CL = 5pF (see Figure 15., page 20).
M48T59, M48T59Y, M48T59V*
WRITE Mode
The M48T59/Y/V is in the WRITE Mode whenever
W and E are low. The start of a WRITE is refer-
enced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of tEHAX from Chip Enable or tWHAX
from WRITE Enable prior to the initiation of anoth-
er READ or WRITE cycle. Data-in must be valid
tDVWH prior to the end of WRITE and remain valid
for tWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; however, if
the output bus has been activated by a low on E
and G a low on W will disable the outputs tWLQZ af-
ter W falls.
9/29
M48T59, M48T59Y, M48T59V*
Table 4. WRITE Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V, 4.75 to 5.5V, or 3.0 to 3.6V (except where noted). CL = 5pF (see Figure 15., page 20). If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
M48T59, M48T59Y, M48T59V*
Data Retention Mode
With valid VCC applied, the M48T59/Y/V operates
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
tent. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48T59/Y/V may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T59/Y/V for
an accumulated period of at least 7 years when
VCC is less than VSO. As system power returns
and VCC rises above VSO, the battery is discon-
nected and the power supply is switched to exter-
nal VCC. Deselect continues for trec after VCC
reaches VPFD (max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
11/29
M48T59, M48T59Y, M48T59V*
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER® registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT™ TIME-
KEEPER cells in the RAM array are only data reg-
isters and not the actual clock counters, so
updating the registers can be halted without dis-
turbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control register (1FF8h). As
long as a '1' remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and the time that
were current at the moment the halt command was
issued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a '0.'
Setting the Clock
Bit D7 of the Control register (1FF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 5., page 12). Resetting the
WRITE Bit to a '0' then transfers the values of all
time registers (1FF9h-1FFFh) to the actual TIME-
KEEPER counters and allows normal operation to
resume. After the WRITE Bit is reset, the next
clock update will occur within approximately one
second.
See the Application Note AN923, “TIMEKEEPER
Rolling Into the 21st Century” for information on
Century Rollover.
Note: Upon power-up following a power failure,
both the WRITE Bit and the READ Bit will be reset
to '0.'
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. The M48T59/Y/V in the
DIP package is shipped from STMicroelectronics
with the STOP Bit set to a '1.' When reset to a '0,'
the M48T59/Y/V oscillator starts within one sec-
ond.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT), the STOP Bit (ST) or the CENTURY EN-
ABLE Bit (CEB).
M48T59, M48T59Y, M48T59V*
Table 5. Register Map
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
Y = '1' or '0'
Z = '0' and are Read only
AF = Alarm Flag (Read only)
BL = Battery Low (Read only)
WDS = Watchdog Steering Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable
ABE = Alarm in Battery Back-up Mode Enable
RPT1-RPT4 = Alarm Repeat Mode Bits
WDF = Watchdog Flag (Read only)
CEB = Century Enable Bit
CB = Century Bit
13/29
M48T59, M48T59Y, M48T59V*
Calibrating the Clock
The M48T59/Y/V is driven by a quartz-controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed 35 PPM
(parts per million) oscillator frequency error at
25°C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T59/Y/V improves to better
than +1/–2 PPM at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 10., page 14). Most clock
chips compensate for crystal frequency and tem-
perature shift error with cumbersome “trim” capac-
itors. The M48T59/Y/V design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 11., page 14. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five-bit Calibration byte found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order
bits (D4-D0) in the Control register (1FF8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is the Sign Bit; '1' in-
dicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles; for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 PPM of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768
Hz, each of the 31 increments in the Calibration
Byte would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T59/Y/V may re-
quire. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the fi-
nal product is packaged in a non-user serviceable
enclosure. All the designer has to do is provide a
simple utility that accesses the Calibration Byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512 Hz when the
Stop Bit (D7 of 1FF9h) is '0,' the FT Bit (D6 of
1FFCh) is '1,' the AFE Bit (D7 of 1FF6h) is '0,' and
the Watchdog Steering Bit (D7 of 1FF7h) is '1' or
the Watchdog Register is reset (1FF7h = 0).
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024
Hz would indicate a +20 PPM oscillator frequency
error, requiring a –10 (WR001010) to be loaded
into the Calibration Byte for correction. Note that
setting or changing the Calibration Byte does not
affect the Frequency Test output frequency.
The IRQ/FT pin is an open drain output which re-
quires a pull-up resistor for proper operation. A
500-10kΩ resistor is recommended in order to
control the rise time. The FT Bit is cleared on pow-
er-down.
For more information on calibration, see Applica-
tion Note AN934, “TIMEKEEPER Calibration.”
M48T59, M48T59Y, M48T59V*
15/29
M48T59, M48T59Y, M48T59V*
Setting the Alarm Clock
Registers 1FF5h-1FF2h contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific day of the month or
repeat every month, day, hour, minute, or second.
It can also be programmed to go off while the
M48T59/Y/V is in the battery back-up mode of op-
eration to serve as a system wake-up call.
Bits RPT1-RPT4 put the alarm in the repeat mode
of operation. Table 6., page 15 shows the possible
configurations. Codes not listed in the table default
to the once per second mode to quickly alert the
user of an incorrect alarm setting.
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT1-RPT4, AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT pin. To disable the
alarm, write '0' to the Alarm Date Register and
RPT1-4. The Alarm Flag and the IRQ/FT output
are cleared by a READ to the Flags Register as
shown in Figure 12., page 15. A subsequent
READ of the Flags Register is necessary to see
that the value of the Alarm Flag has been reset to
'0.'
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both the ABE (Alarm in Battery
Back-up Mode Enable) and the AFE are set. The
ABE and AFE bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M48T59/Y/V was in the dese-
lect mode during power-down. Figure
13., page 16 illustrates the back-up mode alarm
timing.
Figure 12. Alarm Interrupt Reset Waveform
Table 6. Alarm Repeat Mode
