M48T59-70PC1 Fast Delivery |IC PHOENIX CO.,LIMITED

M48T59-70PC1 ,64 Kbit 8Kb x8 TIMEKEEPER SRAMAbsolute Maximum Ratings" may cause permanent damage to the device. This is a stressrating only and ..
M48T59-70PC1 ,64 Kbit 8Kb x8 TIMEKEEPER SRAMLogic Diagram®SNAPHAT TOP(to be Ordered Separately)■ SOIC PACKAGE PROVIDES DIRECT CONNECTION for a ..
M48T59Y-70MH1 ,64 Kbit (8Kb X8) TIMEKEEPER SRAMBlock Diagram . . 5OPERATION MODES . . . . . . . 6Table 2. Operating Modes 6RE ..
M48T59Y-70PC1 ,64 Kbit (8Kb X8) TIMEKEEPER SRAMM48T59M48T59Y, M48T59V*®5.0 or 3.3V, 64 Kbit (8 Kbit x8) TIMEKEEPER SRAM
M48T59Y-70PC1D ,64 Kbit (8Kb X8) TIMEKEEPER SRAMFEATURES SUMMARY . . . . . 1Figure 1. 28-pin PCDIP, CAPHAT™ Package . 1Figure 2. 28-pin ..
M48T59Y-70PC1DS ,64 Kbit (8Kb X8) TIMEKEEPER SRAMFEATURES SUMMARY■ INTEGRATED ULTRA LOW POWER SRAM, Figure 1. 28-pin PCDIP, CAPHAT™ PackageREAL TIME ..
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M61516FP , MITSUBISHI SOUND PROCESSOR ICs 7.1ch ELECTRONIC VOLUME WITH 10 INPUT SELECTOR
M61516FP , MITSUBISHI SOUND PROCESSOR ICs 7.1ch ELECTRONIC VOLUME WITH 10 INPUT SELECTOR

M48T59-70PC1
64 Kbit 8Kb x8 TIMEKEEPER SRAM
1/21
PRELIMINARY DATA
October 1999
M48T59
M48T59Y/M48T59V
64 Kbit (8Kb x8) TIMEKEEPER® SRAM INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY FREQUENCY TEST OUTPUT for REAL TIME
CLOCK SOFTWARE CALIBRATION AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage): M48T59: 4.5V ≤ VPFD ≤ 4.75V M48T59Y: 4.2V ≤ VPFD ≤ 4.5V M48T59V: 2.7V ≤ VPFD ≤ 3.0V SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE PACKAGING INCLUDES a 28-LEAD SOIC and
SNAPHAT® TOP
(to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACK-UP MODE BATTERY LOW FLAG
Table 1. Signal Names
M48T59, M48T59Y, M48T59V
Table 2. Absolute Maximum Ratings (1)
Note:1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 3. Operating Modes (1)
Note:1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. See Table 7 for details.
3/21
M48T59, M48T59Y, M48T59V
DESCRIPTION
The M48T59/59Y/59V TIMEKEEPER® RAM is an
8Kb x8 non-volatile static RAM and real time clock.
The monolithic chip is available in two special
packages to provide a highly integrated battery
backed-up memory and real time clock solution.
The M48T59/59Y/59V is a non-volatile pin and
function equivalent to any JEDEC standard 8Kb x8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number of writes
that can be performed.
The 28 pin 600mil DIP CAPHAT™ houses the
M48T59/59Y/59V silicon with a quartz crystal and
a long life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
M48T59, M48T59Y, M48T59V
Table 5. Capacitance (1, 2)
(TA = 25 °C)
Note:1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. Outputs deselected.
Table 6. DC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
Note:1. Outputs deselected. Negative spikes of –1V allowed for up to 10ns once per cycle. The IRQ/FT and RST pins are Open Drain.
Table 7. Power Down/Up Trip Points DC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C)
Note:1. All voltages referenced to VSS. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device).
5/21
M48T59, M48T59Y, M48T59V
Table 8. Power Down/Up AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C)
Note:1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200μs after VCC pass-
es VPFD (min). VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. tREC (min) = 20ms for industrial temperature grade 6 device.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the bat-
tery/crystal package (i.e. SNAPHAT) part number
is "M4T28-BR12SH" or “M4T32-BR12SH”.
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T59/59Y/59V are integrated on one silicon
chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with
addresses 1FF8h-1FFFh. The clock locations
contain the century, year, month, date, day, hour,
minute, and second in 24 hour BCD format (except
for the century). Corrections for 28, 29 (leap year),
30, and 31 day months are made automatically.
Byte 1FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
M48T59, M48T59Y, M48T59V
Table 9. Read Mode AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
Note:1. CL = 100pF (see Fig 4). CL = 5pF (see Fig 4).
7/21
M48T59, M48T59Y, M48T59V
Table 10. Write Mode AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
Note:1. CL = 5pF (see Fig 4). If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ read/write memory cells.
The M48T59/59Y/59V includes a clock control cir-
cuit which updates the clock bytes with current in-
formation once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T59/59Y/59V also has its own Power-fail
Detect circuit. The control circuitry constantly mon-
itors the single 5V supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low VCC. As VCC falls
below approximately 3V, the control circuitry con-
nects the battery which maintains data and clock
operation until valid power returns.
READ MODE
The M48T59/59Y/59V is in the Read Mode when-
ever W (Write Enable) is high and E (Chip Enable)
is low. The unique address specified by the 13 Ad-
dress Inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (tAVQV) after the last address input signal is
stable, providing that the E and G access times
are also satisfied. If the E and G access times are
not met, valid data will be available after the latter
of the Chip Enable Access time (tELQV) or Output
Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
M48T59, M48T59Y, M48T59V
9/21
M48T59, M48T59Y, M48T59V
WRITE MODE
The M48T59/59Y/59V is in the Write Mode when-
ever W and E are low. The start of a write is refer-
enced from the latter occurring falling edge of W or
E. A write is terminated by the earlier rising edge
of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of tEHAX from Chip Enable or tWHAX
from Write Enable prior to the initiation of another
read or write cycle. Data-in must be valid tDVWH
prior to the end of write and remain valid for tWHDX
afterward. G should be kept high during write cy-
cles to avoid bus contention; although, if the output
bus has been activated by a low on E and G a low
on W will disable the outputs tWLQZ after W falls.
DATA RETENTION MODE
With valid VCC applied, the M48T59/59Y/59V op-
erates as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as "don’t care."
Note: A power failure during a write cycle may cor-
rupt data at the currently addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below VPFD (min), the user can be as-
sured the memory will be in a write protected state,
provided the VCC fall time is not less than tF. The
M48T59/59Y/59V may respond to transient noise
spikes on VCC that reach into the deselect window
Table 11. Register Map
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to zero
Y = ’1’ or ’0’
Z = ’0’ and are Read only
AF = Alarm Flag
BL = Battery Low
WDS = Watchdog Steering Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable
ABE = Alarm in Battery Back-up Mode Enable
RPT1-RPT4 = Alarm Repeat Mode Bits
WDF = Watchdog Flag
CEB = Century Enable Bit
CB = Century Bit
M48T59, M48T59Y, M48T59V
condition reset will not occur unless the addresses
are stable at the flag location for at least 15ns
while the divice is in the read mode as shown in
Figure 11.
The IRQ/FT pin is an open drain output and re-
quires a pull-up resistor (10kΩ recommended) to
VCC. The pin remains in the high impedance state
unless an interrupt occurs or the frequency test
mode is enabled.
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control register (1FF8h). As
long as a ’1’ remains in that position, updating is
halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and the time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.
Setting the Clock
Bit D7 of the Control register (1FF8h) is the
WRITE bit. Setting the WRITE bit to a ’1’, like the
READ bit, halts updates to the TIMEKEEPER reg-
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T59/59Y/
59V for an accumulated period of at least 7 years
when VCC is less than VSO. As system power re-
turns and VCC rises above VSO, the battery is dis-
connected, and the power supply is switched to
external VCC. Deselect continues for tREC after
VCC reaches VPFD (max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
POWER-ON RESET
The M48T59/59Y/59V continuously monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for 40ms to 200ms after VCC passes
VPFD. RST is valid for all VCC conditions. The RST
pin is an open drain output and an appropriate re-
sistor to VCC should be chosen to control rise time.
PROGRAMMABLE INTERRUPTS
The M48T59/59Y/59V provides two programma-
ble interrupts; an alarm and a watchdog. When an
interrupt condition occurs, the M48T59/59Y/59V
sets the appropriate flag bit in the flag register
1FF0h. The interrupt enable bits in (AFE and ABE)
in 1FF6h and the Watchdog Steering (WDS) bit in
1FF7h allow the interrupt to activate the IRQ/FT
pin.
The interrupt flags and the IRQ/FT output are
cleared by a read to the flags register. An interrupt
11/21
M48T59, M48T59Y, M48T59V
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 12). Resetting the WRITE bit to
a ’0’ then transfers the values of all time registers
(1FF9h-1FFFh) to the actual TIMEKEEPER
counters and allows normal operation to resume.
After the WRITE bit is reset, the next clock update
will occur within approximately one second.
See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" for information on
Century Rollover.
Note: Upon power-up following a power failure,
both the WRITE bit and the READ bit will be reset
to ‘0’.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. The M48T59/59Y/59V in
the DIP package, is shipped from
STMicroelectronics with the STOP bit set to a '1'.
When reset to a '0', the M48T59/59Y/59V oscilla-
tor starts within one second.
Note: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT), the STOP bit (ST) or the CENTURY EN-
ABLE bit (CEB).
Calibrating the Clock
The M48T59/59Y/59V is driven by a quartz con-
trolled oscillator with a nominal frequency of
32,768Hz. The devices are tested not to exceed
35 ppm (parts per million) oscillator frequency er-
ror at 25°C, which equates to about ±1.53 minutes
per month. With the calibration bits properly set,
the accuracy of each M48T59/59Y/59V improves
to better than +1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 10). Most clock chips
compensate for crystal frequency and tempera-
ture shift error with cumbersome trim capacitors.
The M48T59/59Y/59V design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 9. The number of times pulses are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five bit Calibration byte found in the
Control Register. Adding counts speeds the clock
up, subtracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control register (1FF8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute

Partno	Mfg	Dc	Qty	Available	Descript
M48T59-70PC1 \|M48T5970PC1	ST ?	N/a	30	avai	64 Kbit 8Kb x8 TIMEKEEPER SRAM
M48T59-70PC1 \|M48T5970PC1	ST	N/a	110	avai	64 Kbit 8Kb x8 TIMEKEEPER SRAM