M48T58-70MH1 ,5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER SRAMAbsolute Maximum Ratings" may cause permanent damage to the device. This is astress rating only and ..
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M48T58-70MH1
64 Kbit 8Kb x8 TIMEKEEPER SRAM
M48T58
M48T58Y64 Kbit (8Kb x8) TIMEKEEPER® SRAM
July 1999 1/17
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
BYTEWIDE RAM-LIKE CLOCK ACCESS
BCD CODED YEAR, MONTH, DAY , DATE,
HOURS, MINUTES and SECONDS
FREQUENCY TEST OUTPUT for REAL TIME
CLOCK
AUTOMA TIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage): M48T58: 4.5V ≤ VPFD ≤ 4.75V M48T58Y: 4.2V ≤ VPFD ≤ 4.5V
SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT® TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 8K x 8 SRAMs
DESCRIPTIONThe M48T58/58Y TIMEKEEPER® RAM is an 8K x
8 non-volatile static RAM and real time clock. The
monolithic chip is available in two special packages
to provide a highly integrated battery backed-up
memory and real time clock solution.
Figure 1. Logic Diagram
Table 1. Signal Names
Notes:1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 2. Absolute Maximum Ratings (1)
Notes:1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. See Table 7 for details.
Table 3. Operating Modes (1)
Figure 2A. DIP Pin Connections
Figure 2B. SOIC Pin Connections2/17
M48T58, M48T58Y
Figure 4. AC Testing Load Circuit Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
Figure 3. Block DiagramThe M48T58/58Y is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The 28 pin 600mil DIP CAPHAT houses the
M48T58/58Y silicon with a quartz crystal and a long
life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery and crystal. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and
crystal damage due to the high temperatures re-
quired for device surface-mounting. The SNAPHAT
housing is keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form.
DESCRIPTION (cont’d)3/17
M48T58, M48T58Y
Notes:1. Outputs Deselected.
2. Negative spikes of –1V allowed for up to 10ns once per Cycle. The FT pin is Open Drain.
Table 6. DC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Notes:1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. Outputs deselected
Table 5. Capacitance (1, 2) (TA = 25 °C, f = 1 MHz )
Notes:1. All voltages referenced to VSS.At 25°C
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70°C)
For the 28 lead SOIC, the battery/crystal package
(i.e. SNAPHAT) part number is "M4T28-
BR12SH1".
As Figure 3 shows, the static memory array and the
qua rtz controlled clock oscillator of the
M48T58/58Y are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE clock information in the bytes with
addresses 1FF8h-1FFFh. The clock locations con-
tain the year, month, date, day, hour, minute, and
second in 24 hour BCD format. Corrections for 28,
29 (leap year), 30, and 31 day months are made
automatically. Byte 1FF8h is the clock control reg-
ister. This byte controls user access to the clock
information and also stores the clock calibration
setting.
DESCRIPTION (cont’d)4/17
M48T58, M48T58Y
Notes:1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 μs after
VCC passes VPFD (min). VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Table 8. Power Down/Up Mode AC Characteristics (TA = 0 to 70°C)
Figure 5. Power Down/Up Mode AC Waveforms5/17
M48T58, M48T58Y
Notes:1. CL = 100pF (see Figure 4). CL = 5pF (see Figure 4).
Table 9. Read Mode AC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Figure 6. Read Mode AC Waveforms
Note: Write Enable (W) = High.6/17
M48T58, M48T58Y
Notes:1. CL = 5pF (see Figure 4). If E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state.
Table 10. Write Mode AC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
7/17
M48T58, M48T58Y
Figure 7. Write Enable Controlled, Write AC Waveforms
Figure 8. Chip Enable Controlled, Write AC Waveforms8/17
M48T58, M48T58Y
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT read/write memory cells.
The M48T58/58Y includes a clock control circuit
which updates the clock bytes with current informa-
tion once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array.
The M48T58/58Y also has its own Power-fail De-
tect circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
tion. When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
eration brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
READ MODEThe M48T58/58Y is in the Read Mode whenever
W (Write Enable) is high, E1 (Chip Enable 1) is low,
and E2 (Chip Enable 2) is high. The unique address
specified by the 13 Address Inputs defines which
one of the 8,192 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E1,
E2, and G access times are also satisfied. If the E1,
E2 and G access times are not met, valid data will
be available after the latter of the Chip Enable
Access times (tE1LQV or tE2HQV) or Output Enable
Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E1, E2 and G. If the outputs are
activated before tAVQV, the data lines will be driven
to an indeterminate state until tAVQV. If the Address
Inputs are changed while E1, E2 and G remain
active, output data will remain valid for Output Data
Hold time (tAXQX) but will go indeterminate until the
next Address Access.
WRITE MODEThe M48T58/58Y is in the Write Mode whenever W
and E1 are low and E2 is high. The start of a write
is referenced from the latter occurring falling edge
of W or E1, or the rising edge of E2. A write is
terminated by the earlier rising edge of W or E1, or
the falling edge of E2. The addresses must be held
valid throughout the cycle. E1 or W must return high
or E2 low for a minimum of tE1HAX or tE2LAX from
Chip Enable or tWHAX from Write Enable prior to the
initiation of another read or write cycle. Data-in
must be valid tDVWH prior to the end of write and
remain valid for tWHDX afterward. G should be kept
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on E1 and G and a high on E2, a low on W will
disable the outputs tWLQZ after W falls.
DESCRIPTION (cont’d)
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit (Must be set to ’0’ upon power, for normal clock operation)
R = READ Bit = WRITE Bit
ST = STOP Bit
0 = Must be set to ’0’
Table 11. Register Map9/17
M48T58, M48T58Y
