M48T512Y-70PM1 ,3.3V-5V 4 MB (512K X 8) TIMEKEEPER SRAMAbsolute Maximum Ratings . . . . . . . 14DC AND AC PARAMETERS . 15Table 7. Operating and ..
M48T559Y-MH1 ,64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXEDAbsolute Maximum Ratings" may cause permanent damage to the device. This is a stressrating only and ..
M48T559Y-MH1TR ,64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXEDLogic Diagram■ WRITE PROTECT VOLTAGE(V = Power-fail Deselect Voltage):PFD– M48T559Y: 4.2V ≤ V ≤ 4.5 ..
M48T58-70MH1 ,5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER SRAMAbsolute Maximum Ratings" may cause permanent damage to the device. This is astress rating only and ..
M48T58-70PC1 ,64 KBIT (8KB X 8) TIMEKEEPER SRAMLogic Diagram Table 1. Signal NamesV A0-A12 Address InputsCCDQ0-DQ7 Data Inputs / Outputs13 8Freque ..
M48T58Y-70 MH1TR ,64 KBIT (8KB X 8) TIMEKEEPER SRAMFEATURES SUMMARY . . . . . 1Figure 1. 28-pin PCDIP, CAPHAT™ Package . 1Figure 2. 28-pin ..
M-614T , DC Line Fileters
M-614T , DC Line Fileters
M61511FP , AUDIO SIGNAL PROCESSOR
M61511FP , AUDIO SIGNAL PROCESSOR
M61512FP , 5.1ch Electronic Volume
M61512FP , 5.1ch Electronic Volume
M48T512Y-70PM1
3.3V-5V 4 MB (512K X 8) TIMEKEEPER SRAM
1/21February 2005
M48T512Y
M48T512V*5.0 or 3.3V, 4 Mbit (512 Kbit x 8) TIMEKEEPER® SRAM
* Contact local ST sales office for availability of 3.3V version.
FEATURES SUMMARY INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, BATTERY, AND
CRYSTAL BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, AND SECONDS AUTOMATIC POWER-FAIL CHIP
DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES:
(VPFD = Power-fail Deselect Voltage) M48T512Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V M48T512V*: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS 10 YEARS OF DATA RETENTION AND
CLOCK OPERATION IN THE ABSENCE OF
POWER PIN AND FUNCTION COMPATIBLE WITH
INDUSTRY STANDARD 512K x 8 SRAMS SELF-CONTAINED BATTERY AND
CRYSTAL IN DIP PACKAGE
M48T512Y, M48T512V*
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 32-pin, PMDIP Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. 32-pin DIP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 6. WRITE AC Waveforms, WRITE Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 7. WRITE AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Figure 8. Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 9. Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Figure 10.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 11.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 12.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 11. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3/21
M48T512Y, M48T512V*
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 13.PMDIP32 – 32-pin Plastic Module DIP, Package Outline . . . . . . . . . . . . . . . . . . . . . . . .18
Table 12. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data . . . . . . . . . . . . . . . .18
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
M48T512Y, M48T512V*
SUMMARY DESCRIPTIONThe M48T512Y/V TIMEKEEPER® RAM is a
512Kb x 8 non-volatile static RAM and real time
clock organized as 524,288 words by 8 bits. The
special DIP package provides a fully integrated
battery back-up memory and real time clock solu-
tion.
The M48T512Y/V directly replaces industry stan-
dard 512Kb x 8 SRAMs. It also provides the non-
volatility of Flash without any requirement for spe-
cial WRITE timing or limitations on the number of
WRITEs that can be performed.
Table 1. Signal Names
5/21
M48T512Y, M48T512V*
M48T512Y, M48T512V*
OPERATING MODES
The 32-pin, 600mil DIP Hybrid houses a controller
chip, SRAM, quartz crystal, and a long life lithium
button cell in a single package. Figure
11., page 15 illustrates the static memory array
and the quartz controlled clock oscillator. The
clock locations contain the year, month, date, day,
hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year - compliant until
the year 2100), 30, and 31 day months are made
automatically. Byte 7FFF8h is the clock control
register (see Table 5., page 11). This byte controls
user access to the clock information and also
stores the clock calibration setting. The seven
clock bytes (7FFFFh-7FFF9h) are not the actual
clock counters, they are memory locations consist-
ing of BiPORT™ READ/WRITE memory cells
within the static RAM array. The M48T512Y/V in-
cludes a clock control circuit which updates the
clock bytes with current information once per sec-
ond. The information can be accessed by the user
in the same manner as any other location in the
static memory array. The M48T512Y/V also has its
own Power-Fail Detect circuit. This control circuitry
constantly monitors the supply voltage for an out
of tolerance condition. When VCC is out of toler-
ance, the circuit write protects the TIMEKEEPER
register data and SRAM, providing data security in
the midst of unpredictable system operation. As
VCC falls, the control circuitry automatically switch-
es to the battery, maintaining data and clock oper-
ation until valid power is restored.
Table 2. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. See Table 10., page 17 for details.
7/21
M48T512Y, M48T512V*
READ Mode
The M48T512Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 19 Ad-
dress Inputs defines which one of the 524,288
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within Address Ac-
cess Time (tAVQV) after the last address input sig-
nal is stable, providing the E and G access times
are also satisfied. If the E and G access times are
not met, valid data will be available after the latter
of the Chip Enable Access Times (tELQV) or Output
Enable Access Time (tGLQV). The state of the eight
three-state Data I/O signals is controlled by E and
G. If the outputs are activated before tAVQV, the
data lines will be driven to an indeterminate state
until tAVQV. If the Address Inputs are changed
while E and G remain active, output data will re-
main valid for Output Data Hold Time (tAXQX) but
will go indeterminate until the next Address Ac-
cess.
M48T512Y, M48T512V*
WRITE Mode
The M48T512Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a WRITE is referenced from the latter
occurring falling edge of W or E. A WRITE is termi-
nated by the earlier rising edge of W or E. The ad-
dresses must be held valid throughout the cycle. E
or W must return high for a minimum of tEHAX from
Chip Enable or tWHAX from WRITE Enable prior to
the initiation of another READ or WRITE cycle.
Data-in must be valid tDVWH prior to the end of
WRITE and remain valid for tWHDX afterward. G
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs tWLQZ after W falls.
9/21
M48T512Y, M48T512V*
Table 4. WRITE Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). CL = 5pF. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
M48T512Y, M48T512V*
Data Retention Mode
With valid VCC applied, the M48T512Y/V operates
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically deselect, write protecting itself when
VCC falls between VPFD (max), VPFD (min) win-
dow. All outputs become high impedance and all
inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the current addressed location, but
does not jeopardize the rest of the RAM's content.
At voltages below VPFD (min), the memory will be
in a write protected state, provided the VCC fall
time is not less than tF. The M48T512Y/V may re-
spond to transient noise spikes on VCC that cross
into the deselect window during the time the de-
vice is sampling VCC.Therefore, decoupling of the
power supply lines is recommended. When VCC
drops below VSO, the control circuit switches pow-
er to the internal battery, preserving data and pow-
ering the clock. The internal energy source will
maintain data in the M48T512Y/V for an accumu-
lated period of at least 10 years at room tempera-
ture. As system power rises above VSO, the
battery is disconnected, and the power supply is
switched to external VCC. Write protection contin-
ues until VCC reaches VPFD (min) plus tREC (min).
Normal RAM operation can resume tREC after VCC
exceeds VPFD (max). Refer to Application Note
(AN1012) on the ST Web Site for more information
on battery life.
11/21
M48T512Y, M48T512V*
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER® registers should
be halted before clock data is read to prevent
reading data in transition (see Table 5.). The Bi-
PORT™ TIMEKEEPER cells in the RAM array are
only data registers and not the actual clock
counters, so updating the registers can be halted
without disturbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register (7FFF8h). As
long as a '1' remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and time that were
current at the moment the halt command was is-
sued. All of the TIMEKEEPER registers are updat-
ed simultaneously. A halt will not interrupt an
update in progress. Updating occurs 1 second af-
ter the READ Bit is reset to a '0.'
Setting the Clock
Bit D7 of the Control Register (7FFF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 5., page 11). Resetting the
WRITE Bit to a '0' then transfers the values of all
time registers 7FFFFh-7FFF9h to the actual TIME-
KEEPER counters and allows normal operation to
resume. After the WRITE Bit is reset, the next
clock update will occur approximately one second
later. See Application Note, AN923, “TIMEKEEP-® Rolling Into the 21st Century” on the ST Web
Site for more information on Century Rollover.
Note: Upon power-up, both the WRITE Bit and the
READ Bit will be reset to '0.'
Stopping and Starting the Oscillator.
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is located at Bit D7 within 7FFF9h. Setting it to
a '1' stops the oscillator. The M48T512Y/V is
shipped from STMicroelectronics with the STOP
bit set to a '1.' When reset to a '0,' the M48T512Y/
V oscillator starts after approximately one second.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
Table 5. Register Map
Keys: S = SIGN Bit
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
