M48T37V-10MH1E ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMM48T37YM48T37V® 5.0 or 3.3V, 256 Kbit (32 Kbit x8) TIMEKEEPER SRAM
M48T37V-10MH1TR ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMFEATURES SUMMARY■ INTEGRATED ULTRA-LOW POWER SRAM, Figure 1. PackageREAL TIME CLOCK, POWER-FAIL CON ..
M48T37V-10MH6 ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMAbsolute Maximum Ratings . . . . . . . 202/29M48T37Y, M48T37VDC AND AC PARAMETERS . 21Tab ..
M48T37V-10MH6E ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMFEATURES SUMMARY . . . . . 1Figure 1. Package . . . . . . . 1SUMMARY DESCRIPTION ..
M48T37Y-70MH1 ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. SOIC Connections . . . . ..
M48T37Y-70MH1E ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMFEATURES SUMMARY . . . . . 1Figure 1. Package . . . . . . . 1SUMMARY DESCRIPTION ..
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61324SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61324SP , WIDE FREQUENCY BAND ANALOG SWITCH
M-614T , DC Line Fileters
M48T37V-10MH1-M48T37V-10MH1E-M48T37V-10MH1TR-M48T37V-10MH6-M48T37V-10MH6E-M48T37Y-70MH1-M48T37Y-70MH1E-M48T37Y-70MH6E
3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAM
1/29April 2004
M48T37Y
M48T37V5.0 or 3.3V, 256 Kbit (32 Kbit x8) TIMEKEEPER® SRAM
FEATURES SUMMARY INTEGRATED ULTRA-LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, AND BATTERY FREQUENCY TEST OUTPUT FOR REAL
TIME CLOCK SOFTWARE CALIBRATION YEAR 2000 COMPLIANT AUTOMATIC POWER-FAIL CHIP
DESELECT and WRITE PROTECTION WATCHDOG TIMER WRITE PROTECT VOLTAGE
(VPFD = Power-Fail Deselect Voltage): M48T37Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V M48T37V: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V PACKAGING INCLUDES A 44-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY AND
CRYSTAL MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT
ACTIVE IN THE BATTERY BACK-UP MODE BATTERY LOW FLAG
M48T37Y, M48T37V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 6. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 7. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Figure 8. Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 6. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 9. Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Programmable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Battery Low Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 7. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 10.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 12.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3/29
M48T37Y, M48T37V
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 13.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 12. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 13. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Figure 15.SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Outline. . . . . . .24
Table 14. SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Mech. Data . . .24
Figure 16.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . .25
Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . .25
Figure 17.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . .26
Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . .26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 18. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Table 19. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
M48T37Y, M48T37V
SUMMARY DESCRIPTIONThe M48T37Y/V TIMEKEEPER® RAM is a 32 Kb
x8 non-volatile static RAM and real time clock. The
monolithic chip is available in a special package
which provides a highly integrated battery backed-
up memory and real time clock solution.
The 44-lead, 330mil SOIC package provides sock-
ets with gold-plated contacts at both ends for di-
rect connection to a separate SNAPHAT housing
containing the battery and crystal. The unique de-
sign allows the SNAPHAT® battery/crystal pack-
age to be mounted on top of the SOIC package
after the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape &Reel
form. For the 44-lead SOIC, the battery/crystal
package (e.g., SNAPHAT) part number is “M4T28-
BR12SH” or “M4T32-BR12SH” (see Table
18., page 27).
Caution: Do not place the SNAPHAT battery/crys-tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
Table 1. Signal Names
5/29
M48T37Y, M48T37V
Figure 3. SOIC Connections
M48T37Y, M48T37V
7/29
M48T37Y, M48T37V
OPERATION MODES
As Figure 4., page 6 shows, the static memory ar-
ray and the quartz controlled clock oscillator of the
M48T37Y/V are integrated on one silicon chip.
The memory locations that provide user accessi-
ble BYTEWIDE™ clock information are in the
bytes with addresses 7FF1 and 7FF9h-7FFFh (lo-
cated in Table 5., page 13). The clock locations
contain the century, year, month, date, day, hour,
minute, and second in 24 hour BCD format. Cor-
rections for 28, 29 (leap year - valid until the year
2100), 30, and 31 day months are made automat-
ically.
Byte 7FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
Byte 7FF7h contains the watchdog timer setting.
The watchdog timer redirects an out-of-control mi-
croprocessor and provides a reset or interrupt to it.
Bytes 7FF2h-7FF5h are reserved for clock alarm
programming. These bytes can be used to set the
alarm. This will generate an active low signal on
the IRQ/FT pin when the alarm bytes match the
date, hours, minutes, and seconds of the clock.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ READ/WRITE memory
cells. The M48T37Y/V includes a clock control cir-
cuit which updates the clock bytes with current in-
formation once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T37Y/V also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single VCC supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low VCC. As VCC falls
below the Battery Back-up Switchover Voltage
(VSO), the control circuitry connects the battery
which maintains data and clock operation until val-
id power returns.
Table 2. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. See Table 13., page 23 for details.
M48T37Y, M48T37V
READ Mode
The M48T37Y/V is in the READ Mode whenever
WRITE Enable (W) is high and Chip Enable (E) is
low. The unique address specified by the 15 Ad-
dress Inputs defines which one of the 32,752 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (tAVQV) after the last address input signal is
stable, providing that the E and Output Enable (G)
access times are also satisfied. If the E and G ac-
cess times are not met, valid data will be available
after the latter of the Chip Enable Access time
(tELQV) or Output Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV.
If the Address Inputs are changed while E and G
remain active, output data will remain valid for Out-
put Data Hold time (tAXQX) but will be indetermi-
nate until the next Address Access.
Figure 5. READ Mode AC Waveforms
Note: WRITE Enable (W) = High.
Table 3. READ Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). CL = 5pF.
9/29
M48T37Y, M48T37V
WRITE Mode
The M48T37Y/V is in the WRITE Mode whenever
W and E are low. The start of a WRITE is refer-
enced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of tEHAX from Chip Enable or tWHAX
from WRITE Enable prior to the initiation of anoth-
er READ or WRITE cycle. Data-in must be valid tD-
VWH prior to the end of WRITE and remain valid fortWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; however, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ
after W falls.
M48T37Y, M48T37V
Table 4. WRITE Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). CL = 5pF. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
11/29
M48T37Y, M48T37V
Data Retention Mode
With valid VCC applied, the M48T37Y/V operates
as a conventional BYTEWIDE™ static RAM.
Should the Supply Voltage decay, the RAM will
automatically power-fail deselect, write protecting
itself when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
tent. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48T37Y/V may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T37Y/V for
an accumulated period of at least 7 years at room
temperature when VCC is less than VSO. As sys-
tem power returns and VCC rises above VSO, the
battery is disconnected and the power supply is
switched to external VCC. Normal RAM operation
can resume tREC after VCC reaches VPFD (max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
M48T37Y, M48T37V
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER® registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT™ TIME-
KEEPER cells in the RAM array are only data reg-
isters and not the actual clock counters, so
updating the registers can be halted without dis-
turbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register 7FF8h. As
long as a '1' remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and the time that
were current at the moment the halt command was
issued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating will resume within a second af-
ter the bit is reset to a '0.'
Setting the Clock
Bit D7 of the Control Register (7FF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 5., page 13). Resetting the
WRITE Bit to a '0' then transfers the values of all
time registers (7FF1h, 7FF9h-7FFFh) to the actual
TIMEKEEPER counters and allows normal opera-
tion to resume. After the WRITE Bit is reset, the
next clock update will occur in approximately one
second.
Note: Upon power-up following a power failure,
both the WRITE Bit and the READ Bit will be reset
to '0.'
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. When reset to a '0,' the
M48T37Y/V oscillator starts within one second.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
13/29
M48T37Y, M48T37V
Table 5. Register Map
Keys: S = Sign Bit
FT = Frequency Test Bit
R = READ Bit
W = WRITE Bit
ST = Stop Bit
0 = Must be set to '0'
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT4 = Alarm Repeat Mode Bits
WDF = Watchdog Flag (Read only)
AF = Alarm Flag (Read only)
Z = '0' and are Read only
M48T37Y, M48T37V
Setting the Alarm Clock
Registers 7FF5h-7FF2h contain the alarm set-
tings. The alarm can be configured to go off at a
predetermined time on a specific day of the month
or repeat every day, hour, minute, or second. It
can also be programmed to go off while the
M48T37Y/V is in the battery back-up mode of op-
eration to serve as a system wake-up call.
RPT1-RPT4 put the alarm in the repeat mode of
operation. Table 6 shows the possible configura-
tions. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT1-RPT4, AF is set. If AFE is also set, the
alarm condition activates the IRQ/FT pin. To dis-
able alarm, write '0' to the Alarm Date registers
and RPT1-4. The alarm flag and the IRQ/FT out-
put are cleared by a READ to the Flags Register
as shown in Figure 8. A subsequent READ of the
Flags Register is necessary to see that the value
of the Alarm Flag has been reset to '0.'
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both the Alarm in Battery Back-
up Mode Enable (ABE) and the AFE are set. The
ABE and AFE bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M48T37Y/V was in the dese-
lect mode during power-up. Figure 9., page 15 il-
lustrates the back-up mode alarm timing.
Figure 8. Alarm Interrupt Reset Waveform
Table 6. Alarm Repeat Modes
15/29
M48T37Y, M48T37V
Figure 9. Back-up Mode Alarm Waveforms
Calibrating the Clock
The M48T37Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed ±35 PPM
(parts per million) oscillator frequency error at °C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T37Y/V improves to better
than +1/–2 PPM at 25 °C.
The oscillation rate of any crystal changes with
temperature (see Figure 11., page 19). Most clock
chips compensate for crystal frequency and tem-
perature shift error with cumbersome trim capaci-
tors. The M48T37Y/V design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 12., page 19. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five-bit Calibration byte found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is the Sign Bit; '1' in-
dicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125, 829, 120 (64 minutes x 60 seconds/
minute x 32,768 cycles/second) actual oscillator
cycles, that is +4.068 or –2.034 PPM of adjust-
ment per calibration step in the calibration register.
Assuming that the oscillator is in fact running at ex-
actly 32,768 Hz, each of the 31 increments in the
Calibration Byte would represent +10.7 or –5.35
seconds per month which corresponds to a total
range of +5.5 or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T37Y/V may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference (like WWW broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his en-
vironment may require, even after the final product
is packaged in a non-user serviceable enclosure.
All the designer has to do is provide a simple utility
that accesses the Calibration Byte.
