M48T212V85MH1-M48T212V-85MH1-M48T212V85MH1E-M48T212Y70MH1 Fast Delivery |IC PHOENIX CO.,LIMITED

M48T212V85MH1E ,3.3V-5V TIMEKEEPER CONTROLLERLogic Diagram . . 5Table 1. Signal Names . . 5Figure 3. SOIC Connections . . . . ..
M48T212Y70MH1 ,3.3V-5V TIMEKEEPER CONTROLLERAbsolute Maximum Ratings . . . . . . . 23DC AND AC PARAMETERS . 24Table 12. DC and AC Mea ..
M48T251Y-70PM1 ,5.0 OR 3.3V, 4096K TIMEKEEPER%AE SRAM WITH PHANTOMBlock Diagram . . 5OPERATION MODES . . . . . . . 6Table 2. Operating Modes 6RE ..
M48T35-70PC1 ,256 KBIT (32KB X8) TIMEKEEPER SRAMFEATURES SUMMARY■ INTEGRATED, ULTRA LOW POWER SRAM, Figure 1. 28-pin PCDIP, CAPHAT™ PackageREAL TIM ..
M48T35AV-10MH1 ,256 KBIT (32KB X8) TIMEKEEPER SRAMM48T35AYM48T35AV® 5.0 or 3.3V, 256 Kbit (32 Kb x8) TIMEKEEPER SRAM
M48T35AV-10MH6 ,256 KBIT (32KB X8) TIMEKEEPER SRAMBlock Diagram . . 5OPERATION MODES . . . . . . . 6Table 2. Operating Modes 6RE ..
M61283FP , NTSC TV Signal Processor
M61283FP , NTSC TV Signal Processor
M61314SP , I2C BUS CONTROLLED VIDEO PRE-AMP FOR HIGH RESOLUTION COLOR DISPLAY
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH

M48T212V85MH1-M48T212V-85MH1-M48T212V85MH1E-M48T212Y70MH1
3.3V-5V TIMEKEEPER CONTROLLER
1/32April 2004
M48T212Y
M48T212V
5.0V or 3.3V TIMEKEEPER® Supervisor
FEATURES SUMMARY INTEGRATED REAL TIME CLOCK, POWER-
FAIL CONTROL CIRCUIT, BATTERY AND
CRYSTAL CONVERTS LOW POWER SRAM INTO
NVRAMs YEAR 2000 COMPLIANT (4-Digit Year) BATTERY LOW FLAG MICROPROCESSOR POWER-ON RESET PROGRAMMABLE ALARM OUTPUT
ACTIVE IN THE BATTERY BACKED-UP
MODE WATCHDOG TIMER AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION CHOICE OF WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage): M48T212Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V M48T212V: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V PACKAGING INCLUDES A 44-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately)
M48T212Y, M48T212V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 1. 44-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 3. SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 4. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Address Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 3. Truth Table for SRAM Bank Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 5. Chip Enable Control and Bank Select Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 4. Chip Enable Control and Bank Select Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .9
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 6. READ Cycle Timing: RTC Control Signal Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 5. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 7. WRITE Cycle Timing: RTC Control Signal Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 6. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 7. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 8. Alarm Interrupt Reset Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 8. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 9. Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
VCC Switch Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 10.(RSTIN1 & RSTIN2) Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 9. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 10. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3/32
M48T212Y, M48T212V
Figure 12.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 13.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 12. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 14.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 15.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 15. Power Down/Up Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 16.SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline . . . . . . . . . . . . . .27
Table 16. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data . . . . . .27
Figure 17.SH – 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline . . . . . .28
Table 17. SH – 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mech. Data . . .28
Figure 18.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . .29
Table 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . .29
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 19. Ordering Information Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 20. SNAPHAT® Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
M48T212Y, M48T212V
DESCRIPTION
The M48T212Y/V are self-contained devices that
include a real time clock (RTC), programmable
alarms, a watchdog timer, and two external chip
enable outputs which provide control of up to four
(two in parallel) external low-power static RAMs.
Access to all TIMEKEEPER® functions and the
external RAM is the same as conventional byte-
wide SRAM. The 16 TIMEKEEPER Registers offer
Century, Year, Month, Date, Day, Hour, Minute,
Second, Calibration, Alarm, Watchdog, and Flags.
Externally attached static RAMs are controlled by
the M48T212Y/V via the E1CON and E2CON sig-
nals (see Table 3., page8).
The 44-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT® housing con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the-44 lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is “M4TXX-BR12SH” (see Table
20., page 30).
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
5/32
M48T212Y, M48T212V Table 1. Signal Names
M48T212Y, M48T212V
7/32
M48T212Y, M48T212V
Figure 4. Hardware Hookup
Note:1. See description in Power Supply Decoupling and Undershoot Protection. Traces connecting E1CON and E2CON to external SRAM should be as short as possible. If the second chip enable pin (E2) is unused, it should be tied to VOUT.
M48T212Y, M48T212V
OPERATION
Automatic backup and write protection for an ex-
ternal SRAM is provided through VOUT, E1CON
and E2CON pins. (Users are urged to insure that
voltage specifications, for both the SUPERVISOR
chip and external SRAM chosen, are similar). The
SNAPHAT® containing the lithium energy source
used to permanently power the real time clock is
also used to retain RAM data in the absence of
VCC power through the VOUT pin.
The chip enable outputs to RAM (E1CON and
E2CON) are controlled during power transients to
prevent data corruption. The date is automatically
adjusted for months with less than 31 days and
corrects for leap years (valid until 2100). The inter-
nal watchdog timer provides programmable alarm
windows.
The nine clock bytes (Fh-9h and 1h) are not the
actual clock counters, they are memory locations
consisting of BiPORT™ READ/WRITE memory
cells within the static RAM array. Clock circuitry
updates the clock bytes with current information
once per second. The information can be access-
ed by the user in the same manner as any other lo-
cation in the static memory array.
Byte 8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting. Byte 7h con-
tains the watchdog timer setting. The watchdog
timer can generate either a reset or an interrupt,
depending on the state of the Watchdog Steering
Bit (WDS). Bytes 6h-2h include bits that, when
programmed, provide for clock alarm functionality.
Alarms are activated when the register content
matches the month, date, hours, minutes, and
seconds of the clock registers. Byte 1h contains
century information. Byte 0h contains additional
flag information pertaining to the watchdog timer,
alarm and battery status.
The M48T212Y/V also has its own Power-Fail De-
tect circuit. This control circuitry constantly moni-
tors the supply voltage for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the TIMEKEEPER® register data
and external SRAM, providing data security in the
midst of unpredictable system operation. As VCC
falls below VSO, the control circuitry automatically
switches to the battery, maintaining data and clock
operation until valid power is restored.
Address Decoding
The M48T212Y/V accommodates 4 address lines
(A3-A0) which allow access to the sixteen bytes of
the TIMEKEEPER clock registers. All TIMEKEEP-
ER registers reside in the SUPERVISOR chip it-
self. All TIMEKEEPER registers are accessed by
enabling E (Chip Enable).
Table 2. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage See Table 14., page 25 for details.
Table 3. Truth Table for SRAM Bank Select
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage See Table 14., page 25 for details.
9/32
M48T212Y, M48T212V
Figure 5. Chip Enable Control and Bank Select Timing
Table 4. Chip Enable Control and Bank Select Characteristics
M48T212Y, M48T212V
READ Mode
The M48T212Y/V executes a READ cycle when-
ever W (WRITE Enable) is high and E (Chip En-
able) is low. The unique address specified by the
address inputs (A3-A0) defines which one of the
on-chip TIMEKEEPER® registers is to be access-
ed. When the address presented to the
M48T212Y/V is in the range of 0h-Fh, one of the
on-board TIMEKEEPER registers is accessed and
valid data will be available to the eight data output
drivers within tAVQV after the address input signal
is stable, providing that the E and G access times
are also satisfied.If they are not, then data access
must be measured from the latter occurring signal
(E or G) and the limiting parameter is either tELQV
for E or tGLQV for G rather than the address access
time.
When EX input is low, an external SRAM location
will be selected.
Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
Figure 6. READ Cycle Timing: RTC Control Signal Waveforms
Note: EX is assumed High.
Table 5. READ Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). CL = 5pF.
11/32
M48T212Y, M48T212V
WRITE Mode
The M48T212Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are in a
low state after the address inputs are stable. The
start of a WRITE is referenced from the latter oc-
curring falling edge of W or E. A WRITE is termi-
nated by the earlier rising edge of W or E. The
addresses must be held valid throughout the cy-
cle. E or W must return high for a minimum of tE-
HAX from Chip Enable or tWHAX from WRITE
Enable prior to the initiation of another READ or
WRITE cycle. Data-in must be valid tDVWH prior to
the end of WRITE and remain valid for tWHDX af-
terward.
G should be kept high during WRITE cycles to
avoid bus contention; although, if the output bus
has been activated by a low on E and G a low on
W will disable the outputs tWLQZ after W falls.
When E is low during the WRITE, one of the on-
board TIMEKEEPER® registers will be selected
and data will be written into the device. When EX
is low (and E is high) an external SRAM location is
selected.
Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
Figure 7. WRITE Cycle Timing: RTC Control Signal Waveforms
Note: EX is assumed High.
M48T212Y, M48T212V
Table 6. WRITE Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). CL = 5pF If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
13/32
M48T212Y, M48T212V
Data Retention Mode
With valid VCC applied, the M48T212Y/V can be
accessed as described above with READ or
WRITE cycles. Should the supply voltage decay,
the M48T212Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
VCC falls between VPFD (max) and VPFD (min).
This is accomplished by internally inhibiting ac-
cess to the clock registers via the E signal. At this
time, the Reset pin (RST) is driven active and will
remain active until VCC returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing E1CON and E2CON to a high level.
This level is within 0.2 volts of the VBAT. E1CON
and E2CON will remain at this level as long as VCC
remains at an out-of-tolerance condition.
When VCC falls below battery back-up switchover
voltage (VSO), power input is switched from the
VCC pin to the SNAPHAT® battery and the clock
registers and external SRAM are maintained from
the attached battery supply. All outputs become
high impedance. The VOUT pin is capable of sup-
plying 100µA of current to the attached memory
with less than 0.3V drop under this condition. On
power up, when VCC returns to a nominal value,
write protection continues for 200ms (max) by in-
hibiting E1CON or E2CON.
The RST signal also remains active during this
time (see Figure 15., page 26).
Note: Most low power SRAMs on the market to-
day can be used with the M48T212Y/V TIME-
KEEPER® SUPERVISOR. There are, however
some criteria which should be used in making the
final choice of an SRAM to use. The SRAM must
be designed in a way where the chip enable input
disables all other inputs to the SRAM. This allows
inputs to the M48T212Y/V and SRAMs to be
“Don't care” once VCC falls below VPFD(min). The
SRAM should also guarantee data retention down
to VCC = 2.0V. The chip enable access time must
be sufficient to meet the system needs with the
chip enable output propagation delays included.
If the SRAM includes a second chip enable pin
(E2), this pin should be tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use.
The data retention current value of the SRAMs can
then be added to the IBAT value of the M48T212Y/
V to determine the total current requirements for
data retention. The available battery capacity for
the SNAPHAT® of your choice can then be divided
by this current to determine the amount of data re-
tention available (see Table 20., page 30).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
M48T212Y, M48T212V
CLOCK OPERATION
TIMEKEEPER® Registers
The M48T212Y/V offers 16 internal registers
which contain TIMEKEEPER® , Alarm, Watchdog,
Flag, and Control data. These registers are mem-
ory locations which contain external (user accessi-
ble) and internal copies of the data (usually
referred to as BiPORT™ TIMEKEEPER cells).
The external copies are independent of internal
functions except that they are updated periodically
by the simultaneous transfer of the incremented
internal copy. TIMEKEEPER and Alarm Registers
store data in BCD. Control, Watchdog and Flags
Registers store data in Binary Format.
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. The BiPORT TIMEKEEPER
cells in the RAM array are only data registers and
not the actual clock counters, so updating the reg-
isters can be halted without disturbing the clock it-
self.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register (8h). As long
as a '1' remains in that position, updating is halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating occurs 1 second after the
READ Bit is reset to a '0.'
Setting the Clock
Bit D7 of the Control Register (8h) is the WRITE
Bit. Setting the WRITE Bit to a '1,' like the READ
Bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (see
Table 7., page 15).
Resetting the WRITE Bit to a '0' then transfers the
values of all time registers (Fh-9h, 1h) to the actual
TIMEKEEPER counters and allows normal opera-
tion to resume. After the WRITE Bit is reset, the
next clock update will occur one second later.
Note: Upon power-up following a power failure,
the READ Bit will automatically be set to a '1.' This
will prevent the clock from updating the TIME-
KEEPER registers, and will allow the user to read
the exact time of the power-down event.
Resetting the READ Bit to a '0' will allow the clock
to update these registers with the current time.
The WRITE Bit will be reset to a '0' upon power-up.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is located at Bit D7 within the Seconds Register
(9h). Setting it to a '1' stops the oscillator. When re-
set to a '0,' the M48T212Y/V oscillator starts within
one second.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
15/32
M48T212Y, M48T212V
Table 7. TIMEKEEPER® Register Map
Keys: S = Sign Bit
FT = Frequency Test Bit
R = READ Bit
W = WRITE Bit
ST = Stop Bit
0 = Must be set to '0'
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog Flag (Read only)
AF = Alarm Flag (Read only)
Y = '1' or '0'
M48T212Y, M48T212V
Setting the Alarm Clock
Address locations 6h-2h contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every year, month,
day, hour, minute, or second. It can also be pro-
grammed to go off while the M48T212Y/V is in the
battery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 8 shows the possible configu-
rations. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set.
If AFE (Alarm Flag Enable) is also set, the alarm
condition activates the IRQ/FT pin. To disable
alarm, write '0' to the Alarm Date registers and
RPT1-5. The IRQ/FT output is cleared by a READ
to the Flags Register as shown in Figure 8. A sub-
sequent READ of the Flags Register is necessary
to see that the value of the Alarm Flag has been
reset to '0.'
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE Bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T212Y/V was in the deselect mode
during power-up. Figure 9., page 17 illustrates the
back-up mode alarm timing.
Figure 8. Alarm Interrupt Reset Waveforms
Table 8. Alarm Repeat Modes

Partno	Mfg	Dc	Qty	Available	Descript
M48T212V85MH1	ST	N/a	105	avai	3.3V-5V TIMEKEEPER CONTROLLER
M48T212V-85MH1 \|M48T212V85MH1	ST	N/a	11	avai	3.3V-5V TIMEKEEPER CONTROLLER
M48T212V85MH1E	STM	N/a	715	avai	3.3V-5V TIMEKEEPER CONTROLLER
M48T212Y70MH1	ST	N/a	7	avai	3.3V-5V TIMEKEEPER CONTROLLER