M48T201V-85MH1F ,3.3V-5V TIMEKEEPER SupervisorM48T201YM48T201V®5.0 or 3.3V TIMEKEEPER Supervisor
M48T201V85MH1TR ,3.3V-5V TIMEKEEPER SupervisorAbsolute Maximum Ratings . . . . . . . 24DC AND AC PARAMETERS . 25Table 11. DC and AC Mea ..
M48T201Y70MH1 ,3.3V-5V TIMEKEEPER CONTROLLERLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. SOIC Connections . . . . ..
M48T201Y-70MH1 ,3.3V-5V TIMEKEEPER CONTROLLERFEATURES SUMMARY■ CONVERTS LOW POWER SRAM INTO Figure 1. PackageNVRAMs■ YEAR 2000 COMPLIANTSNAPHAT ..
M48T201Y-70MH1TR ,3.3V-5V TIMEKEEPER SupervisorFEATURES SUMMARY . . . . . 1Figure 1. Package . . . . . . . 1DESCRIPTION . . . ..
M48T212V85MH1 ,3.3V-5V TIMEKEEPER CONTROLLERFEATURES SUMMARY■ INTEGRATED REAL TIME CLOCK, POWER- Figure 1. 44-pin SOIC PackageFAIL CONTROL CIRC ..
M61283FP , NTSC TV Signal Processor
M61283FP , NTSC TV Signal Processor
M61314SP , I2C BUS CONTROLLED VIDEO PRE-AMP FOR HIGH RESOLUTION COLOR DISPLAY
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M48T201V85MH1-M48T201V-85MH1-M48T201V-85MH1E-M48T201V-85MH1F-M48T201V85MH1TR-M48T201Y70MH1-M48T201Y-70MH1-M48T201Y-70MH1TR
3.3V-5V TIMEKEEPER Supervisor
1/33September 2004
M48T201Y
M48T201V5.0 or 3.3V TIMEKEEPER® Supervisor
FEATURES SUMMARY CONVERTS LOW POWER SRAM INTO
NVRAMs YEAR 2000 COMPLIANT BATTERY LOW FLAG INTEGRATED REAL TIME CLOCK, POWER-
FAIL CONTROL CIRCUIT, BATTERY AND
CRYSTAL WATCHDOG TIMER CHOICE OF WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage): M48T201Y: VCC = 4.5 to 5.5V
4.1V ≤ VPFD ≤ 4.5V M48T201V: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode.) PROGRAMMABLE ALARM OUTPUT
ACTIVE IN THE BATTERY BACKED-UP
MODE PACKAGING INCLUDES A 44-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT® TOP
WHICH CONTAINS THE BATTERY AND
CRYSTAL
M48T201Y, M48T201V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Address Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 5. GCON Timing When Switching Between RTC and External SRAM. . . . . . . . . . . . . . . . . .8
Figure 6. READ Cycle Timing: RTC and External RAM Control Signals . . . . . . . . . . . . . . . . . . . . .9
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 7. WRITE Cycle Timing: RTC & External RAM Control Signals . . . . . . . . . . . . . . . . . . . . .11
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 5. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Figure 8. Alarm Interrupt Reset Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 6. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 9. Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table 7. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Figure 10.RSTIN1 and RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 8. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 12.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3/33
M48T201Y, M48T201VTable 9. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Figure 13.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Table 10. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Table 11. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 14.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 13. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 15.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 14. Power Down/Up Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Figure 16.SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline . . . . . . . . . . . . . .28
Table 15. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data . . . . . .28
Figure 17.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . .29
Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . .29
Figure 18.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . .30
Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . .30
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Table 18. Ordering Information Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 19. SNAPHAT® Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
M48T201Y, M48T201V
DESCRIPTIONThe M48T201Y/V are self-contained devices that
include a real time clock (RTC), programmable
alarms, a watchdog timer, and a square wave out-
put which provides control of up to 512K x 8 of ex-
ternal low-power static RAM. Access to all RTC
functions and the external RAM is the same as
conventional bytewide SRAM. The 16 TIME-
KEEPER® registers offer year, month, date, day,
hour, minute, second, calibration, alarm, century,
watchdog, and square wave output data. External-
ly attached static RAMs are controlled by the
M48T201Y/V via the GCON and ECON signals.
The 44-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT® housing con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery damage due to the high
temperatures required for device surface-mount-
ing. The SNAPHAT housing is keyed to prevent
reverse insertion. The SOIC and battery packages
are shipped separately in plastic anti-static tubes
or in Tape & Reel form. For the 44-lead SOIC, the
battery/crystal package (e.g., SNAPHAT) part
number is “M4Txx-BR12SH” (see Table
19., page 31).
Caution: Do not place the SNAPHAT battery/crys-tal top in conductive foam as this will drain the lith-
ium button-cell battery.
Table 1. Signal Names
5/33
M48T201Y, M48T201V
M48T201Y, M48T201V
Figure 4. Hardware Hookup
Note:1. If the second chip enable pin (E2) is unused, it should be tied to VOUT.
7/33
M48T201Y, M48T201V
OPERATION
Automatic backup and write protection for an ex-
ternal SRAM is provided through VOUT, ECON, and
GCON pins. (Users are urged to insure that voltage
specifications, for both the SUPERVISOR chip
and external SRAM chosen, are similar.) The
SNAPHAT® containing the lithium energy source
is used to retain the RTC and RAM data in the ab-
sence of VCC power through the VOUT pin. The
chip enable output to RAM (ECON) and the output
enable output to RAM (GCON) are controlled dur-
ing power transients to prevent data corruption.
The date is automatically adjusted for months with
less than 31 days and corrects for leap years (valid
until 2100). The internal watchdog timer provides
programmable alarm windows.
The nine clock bytes (7FFFFh-7FFF9h and
7FFF1h) are not the actual clock counters, they
are memory locations consisting of BiPORT™
READ/WRITE memory cells within the static RAM
array. Clock circuitry updates the clock bytes with
current information once per second. The informa-
tion can be accessed by the user in the same man-
ner as any other location in the static memory
array. Byte 7FFF8h is the clock control register.
This byte controls user access to the clock infor-
mation and also stores the clock calibration set-
ting.
Byte 7FFF7h contains the watchdog timer setting.
The watchdog timer can generate either a reset or
an interrupt, depending on the state of the Watch-
dog Steering Bit (WDS). Bytes 7FFF6h-7FFF2h
include bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
date, hours, minutes, and seconds of the clock
registers. Byte 7FFF1h contains century informa-
tion. Byte 7FFF0h contains additional flag informa-
tion pertaining to the watchdog timer, the alarm
condition, the battery status and square wave out-
put operation. 4 bits are included within this regis-
ter (RS0-RS3) that are used to program the
Square Wave Output Frequency (see Table
7., page 18). The M48T201Y/V also has its own
Power-Fail Detect circuit. This control circuitry
constantly monitors the supply voltage for an out
of tolerance condition. When VCC is out of toler-
ance, the circuit write protects the TIMEKEEPER®
register data and external SRAM, providing data
security in the midst of unpredictable system oper-
ation. As VCC falls below the Battery Back-up
Switchover Voltage (VSO), the control circuitry au-
tomatically switches to the battery, maintaining
data and clock operation until valid power is re-
stored.
Address Decoding
The M48T201Y/V accommodates 19 address
lines (A0-A18) which allow direct connection of up
to 512K bytes of static RAM. Regardless of SRAM
density used, timekeeping, watchdog, alarm, cen-
tury, flag, and control registers are located in the
upper RAM locations. All TIMEKEEPER registers
reside in the upper RAM locations without conflict
by inhibiting the GCON (output enable RAM) signal
during clock access. The RAM's physical locations
are transparent to the user and the memory map
looks continuous from the first clock address to the
upper most attached RAM addresses.
Table 2. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage See Table 14., page 27 for details.
M48T201Y, M48T201V
READ Mode
The M48T201Y/V executes a READ Cycle when-
ever W (WRITE Enable) is high and E (Chip En-
able) is low. The unique address specified by the
address inputs (A0-A18) defines which one of the
on-chip TIMEKEEPER® registers or external
SRAM locations is to be accessed. When the ad-
dress presented to the M48T201Y/V is in the
range of 7FFFFh-7FFF0h, one of the on-board
TIMEKEEPER registers is accessed and valid
data will be available to the eight data output driv-
ers within tAVQV after the address input signal is
stable, providing that the E and G access times
are also satisfied. If they are not, then data access
must be measured from the latter occurring signal
(E or G) and the limiting parameter is either tELQV
for E or tGLQV for G rather than the address access
time. When one of the on-chip TIMEKEEPER reg-
isters is selected for READ, the GCON signal will
remain inactive throughout the READ Cycle.
When the address value presented to the
M48T201Y/V is outside the range of TIMEKEEP-
ER registers, an external SRAM location will be
selected. In this case the G signal will be passed
to the GCON pin, with the specified delay times of
tAOEL or tOERL.
9/33
M48T201Y, M48T201V
M48T201Y, M48T201V
Table 3. READ Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). CL = 5pF.
11/33
M48T201Y, M48T201V
WRITE Mode
The M48T201Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable. The start
of a WRITE is referenced from the latter occurring
falling edge of W or E. A WRITE is terminated by
the earlier rising edge of W or E. The addresses
must be held valid throughout the cycle. E or W
must return high for a minimum of tEHAX from Chip
Enable or tWHAX from WRITE Enable prior to the
initiation of another READ or WRITE Cycle. Data-
in must be valid tDVWH prior to the end of WRITE
and remain valid for tWHDX afterward. G should be
kept high during WRITE Cycles to avoid bus con-
tention; although, if the output bus has been acti-
vated by a low on E and G a low on W will disable
the outputs tWLQZ after W falls.
When the address value presented to the
M48T201Y/V during the WRITE is in the range of
7FFFFh-7FFF0h, one of the on-board TIME-
KEEPER® registers will be selected and data will
be written into the device. When the address value
presented to M48T201Y/V is outside the range of
TIMEKEEPER registers, an external SRAM loca-
tion is selected.
Figure 7. WRITE Cycle Timing: RTC & External RAM Control Signals
M48T201Y, M48T201V
Table 4. WRITE Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). CL = 5pF If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
13/33
M48T201Y, M48T201V
Data Retention Mode
With valid VCC applied, the M48T201Y/V can be
accessed as described above with READ or
WRITE cycles. Should the supply voltage decay,
the M48T201Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
VCC falls between VPFD (max) and VPFD (min).
This is accomplished by internally inhibiting ac-
cess to the clock registers via the E signal. At this
time, the Reset pin (RST) is driven active and will
remain active until VCC returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing ECON to a high level. This level is
within 0.2V of the VBAT. ECON will remain at this
level as long as VCC remains at an out-of-toler-
ance condition. When VCC falls below the level of
the battery (VBAT), power input is switched from
the VCC pin to the SNAPHAT® battery and the
clock registers are maintained from the attached
battery supply. External RAM is also powered by
the SNAPHAT battery. All outputs except GCON,
ECON, RST, IRQ/FT and VOUT, become high im-
pedance. The VOUT pin is capable of supplying
100µA of current to the attached memory with less
than 0.3V drop under this condition. On power up,
when VCC returns to a nominal value, write protec-
tion continues for 200ms (max) by inhibiting ECON.
The RST signal also remains active during this
time (see Figure 15., page 27).
Note: Most low power SRAMs on the market to-
day can be used with the M48T201Y/V TIME-
KEEPER® SUPERVISOR. There are, however
some criteria which should be used in making the
final choice of an SRAM to use.
The SRAM must be designed in a way where the
chip enable input disables all other inputs to the
SRAM. This allows inputs to the M48T201Y/V and
SRAMs to be “Don't care” once VCC falls below
VPFD (min). The SRAM should also guarantee
data retention down to VCC = 2.0V. The chip en-
able access time must be sufficient to meet the
system needs with the chip enable (and output en-
able) output propagation delays included.
M48T201Y, M48T201V
CLOCK OPERATION
TIMEKEEPER® Registers
The M48T201Y/V offers 16 internal registers
which contain TIMEKEEPER® , Alarm, Watchdog,
Flag, and Control data (see Table 5., page 15).
These registers are memory locations which con-
tain external (user accessible) and internal copies
of the data (usually referred to as BiPORT™
TIMEKEEPER cells). The external copies are in-
dependent of internal functions except that they
are updated periodically by the simultaneous
transfer of the incremented internal copy. TIME-
KEEPER and Alarm Registers store data in BCD.
Control, Watchdog and Flags (Bits D0 to D3) Reg-
isters store data in Binary Format.
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. The BiPORT TIMEKEEPER
cells in the RAM array are only data registers and
not the actual clock counters, so updating the reg-
isters can be halted without disturbing the clock it-
self.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register (7FFF8h). As
long as a '1' remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating occurs approximately 1 sec-
ond after the READ Bit is reset to a '0.'
Setting the Clock
Bit D7 of the Control Register (7FFF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24-hour BCD
format (see Table 5., page 15).
Resetting the WRITE Bit to a '0' then transfers the
values of all time registers (7FFFFh-7FFF9h,
7FFF1h) to the actual TIMEKEEPER counters and
allows normal operation to resume. After the
WRITE Bit is reset, the next clock update will occur
approximately one second later.
Note: Upon power-up following a power failure,
both the WRITE Bit and the READ Bit will be reset
to '0.'
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is located at Bit D7 within the Seconds Register
(7FFF9h). Setting it to a '1' stops the oscillator.
When reset to a '0,' the M48T201Y/V oscillator
starts within one second.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
15/33
M48T201Y, M48T201V
Table 5. TIMEKEEPER® Register Map
Keys: S = Sign Bit
FT = Frequency Test Bit
R = READ Bit
W = WRITE Bit
ST = Stop Bit
0 = Must be set to '0'
WDS = Watchdog Steering Bit
AF = Alarm Flag
BL = Battery Low Flag
SQWE = Square Wave Enable Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable Flag
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog Flag
RS0-RS3 = SQW Frequency
M48T201Y, M48T201V
Setting the Alarm Clock
Registers 7FFF6h-7FFF2h contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, day of month,
hour, minute, or second or repeat every month,
day of month, hour, minute, or second.
It can also be programmed to go off while the
M48T201Y/V is in the battery back-up to serve as
a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 6 shows the possible configu-
rations. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT pin. To disable alarm,
write ’0’ to the Alarm-Date register and RPT1-5.
The IRQ/FT output is cleared by a READ to the
Flags Register as shown in Figure 8. A subse-
quent READ of the Flags Register is necessary to
see that the value of the Alarm Flag has been re-
set to '0.'
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE Bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T201Y/V was in the deselect mode
during power-up. Figure 9., page 17 illustrates the
back-up mode alarm timing.
Figure 8. Alarm Interrupt Reset Waveforms
Table 6. Alarm Repeat Modes
17/33
M48T201Y, M48T201V
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address
7FFF7h. Bits BMB4-BMB0 store a binary multiplier
and the two lower order bits RB1-RB0 select the
resolution, where 00 = 1/16 second, 01 = 1/4 sec-
ond, 10 = 1 second, and 11 = 4 seconds. The
amount of time-out is then determined to be the
multiplication of the five-bit multiplier value with the
resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T201Y/V sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. WDF is reset by
reading the Flag Register (Address 7FFF0h).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0', the watchdog will activate the IRQ/FT pin
when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on the RST
pin for tREC. The Watchdog register and the AFE,
SQWE, ABE, and FT Bits will reset to a '0' at the
end of a Watchdog time-out when the WDS Bit is
set to a '1.'
The watchdog timer can be reset by two methods: a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or the microprocessor can perform a WRITE of
the Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to VSS if not used. The watchdog
will be reset on each transition (edge) seen by the
WDI pin.
In order to perform a software reset of the watch-
dog timer, the original time-out period can be writ-
ten into the Watchdog Register, effectively
restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also dis-
able the watchdog function until it is again pro-
grammed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
7FFF0h).
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.
Note: The user must transition the address (or
toggle chip enable) to see the Flag Bit change.
