M48T18-150PC1 ,64K (8K X 8) TIMEKEEPER SRAMFEATURES SUMMARY■ INTEGRATED ULTRA LOW POWER SRAM, Figure 1. 28-pin PCDIP, CAPHAT™ PackageREAL TIME ..
M48T201V ,3.3V-5V TIMEKEEPER CONTROLLERAbsolute Maximum Ratings(Table2.) .... ...... ....... ...... ....... ...... ...... .....7DC AND AC ..
M48T201V85MH1 ,3.3V-5V TIMEKEEPER SupervisorAbsolute Maximum Ratings . . . . . . . 24DC AND AC PARAMETERS . 25Table 11. DC and AC Mea ..
M48T201V85MH1 ,3.3V-5V TIMEKEEPER SupervisorFEATURES SUMMARY . . . . . 1Figure 1. Package . . . . . . . 1DESCRIPTION . . . ..
M48T201V-85MH1 ,3.3V-5V TIMEKEEPER SupervisorLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. SOIC Connections . . . . ..
M48T201V-85MH1E ,3.3V-5V TIMEKEEPER SupervisorFEATURES SUMMARY■ CONVERTS LOW POWER SRAM INTO Figure 1. PackageNVRAMs■ YEAR 2000 COMPLIANTSNAPHAT ..
M61283FP , NTSC TV Signal Processor
M61283FP , NTSC TV Signal Processor
M61314SP , I2C BUS CONTROLLED VIDEO PRE-AMP FOR HIGH RESOLUTION COLOR DISPLAY
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M48T08-100PC1-M48T08-150PC1-M48T08Y-10MH1-M48T08Y-10MH1E-M48T18-100PC1-M48T18-150PC1
64K (8K X 8) TIMEKEEPER SRAM
1/27April 2004
M48T08
M48T08Y, M48T185V, 64 Kbit (8 Kb x8) TIMEKEEPER® SRAM
FEATURES SUMMARY INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, AND BATTERY BYTEWIDE™ RAM-LIKE CLOCK ACCESS BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, and SECONDS TYPICAL CLOCK ACCURACY OF ±1
MINUTE A MONTH, AT 25°C AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage): M48T08: VCC = 4.75 to 5.5V
4.5V ≤ VPFD ≤ 4.75V M48T18/T08Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS SELF-CONTAINED BATTERY AND
CRYSTAL IN THE CAPHAT™ DIP
PACKAGE PACKAGING INCLUDES A 28-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY AND
CRYSTAL PIN AND FUNCTION COMPATIBLE WITH
DS1643 and JEDEC STANDARD 8K x8
SRAMs
M48T08, M48T08Y, M48T18
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 28-pin PCDIP, CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 8. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 9. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Power-fail Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Figure 10.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 11.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Figure 12.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 13.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3/27
M48T08, M48T08Y, M48T18Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 11.
Power Down/Up Trip Points DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Figure 15.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline . . . . . . . . . . . . . . . .21
Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data. . . . . . . . .21
Figure 16.SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline.22
Table 13. SOH28 – 28-lead Plastic SO, 4-socket battery SNAPHAT, Package Mech. Data . . . . .22
Figure 17.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . .23
Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . .23
Figure 18.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . .24
Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . .24
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
M48T08, M48T08Y, M48T18
SUMMARY DESCRIPTIONThe M48T08/18/08Y TIMEKEEPER® RAM is an
8K x 8 non-volatile static RAM and real time clock
which is pin and functional compatible with the
DS1643. The monolithic chip is available in two
special packages to provide a highly integrated
battery backed-up memory and real time clock so-
lution.
The M48T08/18/08Y is a non-volatile pin and func-
tion equivalent to any JEDEC standard 8K x 8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
The 28-pin, 600mil DIP CAPHAT™ houses the
M48T08/18/08Y silicon with a quartz crystal and a
long- life lithium button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT® housing con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is “M4T28-BR12SH” or “M4T32-BR12SH”
(see Table 17., page 25).
Table 1. Signal Names
5/27
M48T08, M48T08Y, M48T18
M48T08, M48T08Y, M48T18
OPERATION MODES
As Figure 6., page 5 shows, the static memory ar-
ray and the quartz-controlled clock oscillator of the
M48T08/18/08Y are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with
addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year - valid until
2100), 30, and 31 day months are made automat-
ically. Byte 1FF8h is the clock control register. This
byte controls user access to the clock information
and also stores the clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ READ/WRITE memory
cells. The M48T08/18/08Y includes a clock control
circuit which updates the clock bytes with current
information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T08/18/08Y also has its own Power-fail
Detect circuit. The control circuitry constantly mon-
itors the single 5V supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low VCC. As VCC falls
below the Battery Back-up Switchover Voltage
(VSO), the control circuitry connects the battery
which maintains data and clock operation until val-
id power returns.
Table 2. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. See Table 11., page 20 for details.
7/27
M48T08, M48T08Y, M48T18
READ Mode
The M48T08/18/08Y is in the READ Mode when-
ever W (WRITE Enable) is high, E1 (Chip Enable
1) is low, and E2 (Chip Enable 2) is high. The de-
vice architecture allows ripple-through access of
data from eight of 65,536 locations in the static
storage array. Thus, the unique address specified
by the 13 address inputs defines which one of the
8,192 bytes of data is to be accessed. Valid data
will be available at the Data I/O pins within address
access time (tAVQV) after the last address input
signal is stable, providing that the E1, E2, and G
access times are also satisfied. If the E1, E2 and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
times (tE1LQV or tE2HQV) or Output Enable Access
time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E1, E2 and G. If the outputs are ac-
tivated before tAVQV, the data lines will be driven to
an indeterminate state until tAVQV. If the address
inputs are changed while E1, E2 and G remain ac-
tive, output data will remain valid for Output Data
Hold time (tAXQX) but will go indeterminate until the
next address access.
Figure 7. READ Mode AC Waveforms
Note: WRITE Enable (W) = High.
M48T08, M48T08Y, M48T18
Table 3. READ Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
9/27
M48T08, M48T08Y, M48T18
WRITE Mode
The M48T08/18/08Y is in the WRITE Mode when-
ever W, E1, and E2 are active. The start of a
WRITE is referenced from the latter occurring fall-
ing edge of W or E1, or the rising edge of E2. A
WRITE is terminated by the earlier rising edge of
W or E1, or the falling edge of E2. The addresses
must be held valid throughout the cycle. E1 or W
must return high or E2 low for a minimum of tE1HAX
or tE2LAX from Chip Enable or tWHAX from WRITE
Enable prior to the initiation of another READ or
WRITE Cycle. Data-in must be valid tDVWH prior to
the end of WRITE and remain valid for tWHDX af-
terward. G should be kept high during WRITE Cy-
cles to avoid bus contention; however, if the output
bus has been activated by a low on E1 and G and
a high on E2, a low on W will disable the outputs
tWLQZ after W falls.
Figure 8. WRITE Enable Controlled, WRITE AC Waveform
M48T08, M48T08Y, M48T18
11/27
M48T08, M48T08Y, M48T18
Table 4. WRITE Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
M48T08, M48T08Y, M48T18
Data Retention Mode
With valid VCC applied, the M48T08/18/08Y oper-
ates as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
tent. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48T08/18/08Y may respond to transient
noise spikes on VCC that reach into the deselect
window during the time the device is sampling
VCC. Therefore, decoupling of the power supply
lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T08/18/
08Y for an accumulated period of at least 10 years
when VCC is less than VSO.
Note: Requires use of M4T32-BR12SH
SNAPHAT® top when using the SOH28 package.
As system power returns and VCC rises above
VSO, the battery is disconnected and the power
supply is switched to external VCC.
Write protection continues until VCC reaches VPFD
(min) plus trec (min). E1 should be kept high or E2
low as VCC rises past VPFD (min) to prevent inad-
vertent WRITE cycles prior to system stabilization.
Normal RAM operation can resume trec after VCC
exceeds VPFD (max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
Power-fail Interrupt Pin
The M48T08/18/08Y continuously monitors VCC.
When VCC falls to the power-fail detect trip point,
an interrupt is immediately generated. An internal
clock provides a delay of between 10µs and 40µs
before automatically deselecting the M48T08/18/
08Y. The INT pin is an open drain output and re-
quires an external pull up resistor, even if the inter-
rupt output function is not being used.
13/27
M48T08, M48T08Y, M48T18
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER® registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT™ TIME-
KEEPER cells in the RAM array are only data reg-
isters and not the actual clock counters, so
updating the registers can be halted without dis-
turbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, the seventh bit in the control register.
As long as a '1' remains in that position, updating
is halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and the time that
were current at the moment the halt command was
issued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a '0.'
Setting the Clock
The eighth bit of the control register is the WRITE
Bit. Setting the WRITE Bit to a '1,' like the READ
Bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (on Ta-
ble 5). Resetting the WRITE Bit to a '0' then trans-
fers the values of all time registers (1FF9h-1FFFh)
to the actual TIMEKEEPER counters and allows
normal operation to resume. The FT Bit and the
bits marked as '0' in Table 5 must be written to '0'
to allow for normal TIMEKEEPER and RAM oper-
ation.
See the Application Note AN923, “TIMEKEEPER®
Rolling Into the 21st Century” for information on
Century Rollover.
Table 5. Register Map
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit (Set to '0' for normal clock operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
M48T08, M48T08Y, M48T18
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit (ST) is the MSB of the seconds register. Setting
it to a '1' stops the oscillator. The M48T08/18/08Y
(in the PCDIP28 package) is shipped from STMi-
croelectronics with the STOP Bit set to a '1.' When
reset to a '0,' the M48T08/18/08Y oscillator starts
within one second.
Note: To guarantee oscillator start-up after initial
power-up, first write the STOP Bit (ST) to '1,' then
reset to '0.'
Calibrating the Clock
The M48T08/18/08Y is driven by a quartz-con-
trolled oscillator with a nominal frequency of
32,768 Hz. A typical M48T08/18/08Y is accurate
within 1 minute per month at 25°C without calibra-
tion. The devices are tested not to exceed ± 35
ppm (parts per million) oscillator frequency error at
25°C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T08/18/08Y improves to
better than +1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with
temperature. Figure 10., page 15 shows the fre-
quency error that can be expected at various tem-
peratures. Most clock chips compensate for
crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T08/18/
08Y design, however, employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the di-
vide by 256 stage, as shown in Figure
11., page 15. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five-bit Calibration Byte
found in the Control Register. Adding counts
speeds the clock up, subtracting counts slows the
clock down.
The Calibration Byte occupies the five lower order
bits in the Control register. This byte can be set to
represent any value between 0 and 31 in binary
form. The sixth bit is the Sign Bit; '1' indicates pos-
itive calibration, '0' indicates negative calibration.
Calibration occurs within a 64 minute cycle. The
first 62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary '1'
is loaded into the register, only the first 2 minutes
in the 64 minute cycle will be modified; if a binary
6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles; that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration Byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T08/18/08Y may re-
quire. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the fi-
nal product is packaged in a non-user serviceable
enclosure. All the designer has to do is provide a
simple utility that accesses the Calibration Byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of
standard test equipment. When the Frequency
Test (FT) Bit, the seventh-most significant bit in
the Day Register, is set to a '1,' and the oscillator
is running at 32,768 Hz, the LSB (DQ0) of the Sec-
onds Register will toggle at 512 Hz. Any deviation
from 512 Hz indicates the degree and direction of
oscillator frequency shift at the test temperature.
For example, a reading of 512.01024 Hz would in-
dicate a +20 ppm oscillator frequency error, requir-
ing a –10 (WR001010) to be loaded into the
Calibration Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency. The device must be selected and ad-
dresses must be stable at Address 1FF9h when
reading the 512 Hz on DQ0.
The LSB of the Seconds Register is monitored by
holding the M48T08/18/08Y in an extended READ
of the Seconds Register, but without having the
READ Bit set. The FT Bit MUST be reset to '0' for
normal clock operations to resume.
For more information on calibration, see the Appli-
cation Note AN934, “TIMEKEEPER® Calibration.”
