M41T94MH6TR ,512 Bit (64 bit X8) Serial RTC (SPI) SRAMBlock Diagram . . 6Figure 7. Hardware Hookup . . . . . . . 6Table 2. Function Table ..
M41T94MQ6 ,512 Bit (64 bit X8) Serial RTC (SPI) SRAMFEATURES SUMMARY■ 2.7 TO 5.5V OPERATING VOLTAGE Figure 1. 16-pin SOIC Package■ SERIAL PERIPHERAL IN ..
M41T94MQ6E ,512 Bit (64 bit X8) Serial RTC (SPI) SRAMFEATURES SUMMARY . . . . . 1Figure 1. 16-pin SOIC Package . . . . 1Figure 2. 28-pin SO ..
M42000000J , Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM
M45026 , 145026 COMPATIBLE 3 STATE 19,683 CODES
M45PE10VMN6 ,1 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 25 MHz SPI Bus InterfaceFEATURES . . . . 7Sharing the Overhead of Modifying Data . . . 7An Easy Way to Modify D ..
M5M5V408BFP-85HI , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V408BKV-85H , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V408BTP-85H , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V408BTP-85H , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V408BTP-85HI , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V416BTP-70H , 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
M41T94MH6-M41T94MH6E-M41T94MH6TR-M41T94MQ6-M41T94MQ6E
512 Bit (64 bit X8) Serial RTC (SPI) SRAM
1/32June 2004
M41T94512 Bit (64 bit x8) Serial RTC (SPI) SRAM
FEATURES SUMMARY 2.7 TO 5.5V OPERATING VOLTAGE SERIAL PERIPHERAL INTERFACE (SPI) 2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY CHOICE OF POWER-FAIL DESELECT
VOLTAGES (VCC = 2.7 to 5.5V):
–THS = VSS; 2.55V ≤ VPFD ≤ 2.70V
–THS = VCC; 4.20V ≤ VPFD ≤ 4.50V COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY 44 BYTES OF GENERAL PURPOSE RAM PROGRAMMABLE ALARM AND
INTERRUPT FUNCTION (VALID EVEN
DURING BATTERY BACK-UP MODE) WATCHDOG TIMER MICROPROCESSOR POWER-ON RESET BATTERY LOW FLAG POWER-DOWN TIME-STAMP (HT Bit) LOW OPERATING CURRENT OF 2.0mA ULTRA-LOW BATTERY SUPPLY CURRENT
OF 500nA (MAX) PACKAGING INCLUDES A 28-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately) or 16-LEAD SOIC 28-LEAD SOIC PACKAGE PROVIDES
DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY
AND CRYSTAL
M41T94
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 16-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. 16-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 2. Function Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 8. Data and Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
SPI Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 9. Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 10.Output Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 3. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
READ and WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 11.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 12.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Power-down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Table 4. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 5. Alarm Repeat Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 13.Alarm Interrupt Reset Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 14.Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 6. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 15.RSTIN1 and RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3/32
M41T94Table 7. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Figure 16.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 17.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
tREC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 8. tREC Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 9. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 10. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 11. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 18.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 13. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 14. Crystal Electrical Characteristics (Externally Supplied). . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 19.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 15. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Figure 20.SO16 – 16-lead Plastic Small Outline Package Outline . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 16. SO16 – 16-lead Plastic Small Outline Package Mechanical Data. . . . . . . . . . . . . . . . . .26
Figure 21.SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline. . . . . . . .27
Table 17. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 27
Figure 22.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . .28
Table 18. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data28
Figure 23.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . .29
Table 19. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . .29
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 21. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Table 22. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
M41T94
SUMMARY DESCRIPTIONThe M41T94 Serial TIMEKEEPER® SRAM is a
low power, 512-bit static CMOS SRAM organized
as 64 words by 8 bits. A built-in 32,768Hz oscilla-
tor (external crystal controlled) and 8 bytes of the
SRAM (see Table 4., page 14) are used for the
clock/calendar function and are configured in bina-
ry coded decimal (BCD) format.
An additional 12 bytes of RAM provide status/con-
trol of Alarm, Watchdog and Square Wave func-
tions. Addresses and data are transferred serially
via a serial SPI interface. The built-in address reg-
ister is incremented automatically after each
WRITE or READ data byte. The M41T94 has a
built-in power sense circuit which detects power
failures and automatically switches to the battery
supply when a power failure occurs. The energy
needed to sustain the SRAM and clock operations
can be supplied by a small lithium button-cell sup-
ply when a power failure occurs. Functions avail-
able to the user include a non-volatile, time-of-day
clock/calendar, Alarm interrupts, Watchdog Timer
and programmable Square Wave output. Other
features include a Power-On Reset as well as two
additional debounced inputs (RSTIN1 and
RSTIN2) which can also generate an output Reset
(RST). The eight clock address locations contain
the century, year, month, date, day, hour, minute,
second and tenths/hundredths of a second in 24
hour BCD format. Corrections for 28, 29 (leap year
- valid until year 2100), 30 and 31 day months are
made automatically. The ninth clock address loca-
tion controls user access to the clock information
and also stores the clock software calibration set-
ting.
The M41T94 is supplied in either a 16-lead plastic
SOIC (requiring user supplied crystal and battery)
or a 28-lead SOIC SNAPHAT® package (which in-
tegrates both crystal and battery in a single
SNAPHAT top). The 28-pin, 330mil SOIC provides
sockets with gold plated contacts at both ends for
direct connection to a separate SNAPHAT hous-
ing containing the battery and crystal. The unique
design allows the SNAPHAT battery/crystal pack-
age to be mounted on top of the SOIC package af-
ter the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28-lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is “M4TXX-BR12SH” (see Table
21., page 30).
Caution: Do not place the SNAPHAT battery/crys-tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
5/32
M41T94
M41T94
Figure 6. Block DiagramNote:1. Open drain output
Figure 7. Hardware HookupNote:1. CPOL (Clock Polarity) and CPHA (Clock Phase) are bits that may be set in the SPI Control Register of the MCU.
7/32
M41T94
Table 2. Function TableNote:1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
Figure 8. Data and Clock Timing
Signal Description
Serial Data Output (SDO). The output pin is
used to transfer data serially out of the Memory.
Data is shifted out on the falling edge of the serial
clock.
Serial Data Input (SDI). The input pin is used to
transfer data serially into the device. Instructions,
addresses, and the data to be written, are each re-
ceived this way. Input is latched on the rising edge
of the serial clock.
Serial Clock (SCL). The serial clock provides the
timing for the serial interface (as shown in Figure
9., page 9 and Figure 10., page 9). The W/R Bit,
addresses, or data are latched, from the input pin,
on the rising edge of the clock input. The output
data on the SDO pin changes state after the falling
edge of the clock input.
The M41T94 can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and out-
put data (SDO) is shifted out on the high-to-low
transition of SCL (see Table 2., page 7 and Figure
8., page7).
Chip Enable (E). When E is high, the memory
device is deselected, and the SDO output pin is
held in its high impedance state.
After power-on, a high-to-low transition on E is re-
quired prior to the start of any operation.
M41T94
OPERATIONThe M41T94 clock operates as a slave device on
the SPI serial bus. Each memory device is access-
ed by a simple serial interface that is SPI bus com-
patible. The bus signals are SCL, SDI and SDO
(see Table 1., page 5 and Figure 7., page 6). The
device is selected when the Chip Enable input (E)
is held low. All instructions, addresses and data
are shifted serially in and out of the chip. The most
significant bit is presented first, with the data input
(SDI) sampled on the first rising edge of the clock
(SCL) after the Chip Enable (E) goes low. The 64
bytes contained in the device can then be access-
ed sequentially in the following order: Tenths/Hundredths of a Second Register Seconds Register Minutes Register Century/Hours Register Day Register Date Register Month Register Year Register Control Register
10. Watchdog Register
11 - 16.Alarm Registers
17 - 19.Reserved
20. Square Wave Register
21 - 64.User RAM
The M41T94 clock continually monitors VCC for an
out-of tolerance condition. Should VCC fall below
VPFD, the device terminates an access in progress
and resets the device address counter. Inputs to
the device will not be recognized at this time to
prevent erroneous data from being written to the
device from a an out-of-tolerance system. When
VCC falls below VSO, the device automatically
switches over to the battery and powers down into
an ultra low current mode of operation to conserve
battery life. As system power returns and VCC ris-
es above VSO, the battery is disconnected, and the
power supply is switched to external VCC.
Write protection continues until VCC reaches
VPFD (min) plus tREC (min). For more information
on Battery Storage Life refer to Application Note
AN1012.
SPI Bus CharacteristicsThe Serial Peripheral interface (SPI) bus is intend-
ed for synchronous communication between dif-
ferent ICs. It consists of four signal lines: Serial
Data Input (SDI), Serial Data Output (SDO), Serial
Clock (SCL) and a Chip Enable (E).
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
The E input is used to initiate and terminate a data
transfer. The SCL input is used to synchronize
data transfer between the master (micro) and the
slave (M41T94) devices.
The SCL input, which is generated by the micro-
controller, is active only during address and data
transfer to any device on the SPI bus (see Figure
7., page6).
The M41T94 can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and out-
put data (SDO) is shifted out on the high-to-low
transition of SCL (see Table 2., page 7 and Figure
8., page7).
There is one clock for each bit transferred. Ad-
dress and data bits are transferred in groups of
eight bits. Due to memory size the second most
significant address bit is a Don’t Care (address bit
6).
9/32
M41T94
M41T94
Table 3. AC CharacteristicsNote:1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted). tCH + tCL ≥ 1/fSCL Value guaranteed by design, not 100% tested in production.
11/32
M41T94
READ and WRITE CyclesAddress and data are shifted MSB first into the Se-
rial Data Input (SDI) and out of the Serial Data
Output (SDO). Any data transfer considers the first
bit to define whether a READ or WRITE will occur.
This is followed by seven bits defining the address
to be read or written. Data is transferred out of the
SDO for a READ operation and into the SDI for a
WRITE operation. The address is always the sec-
ond through the eighth bit written after the Enable
(E) pin goes low. If the first bit is a '1,' one or more
WRITE cycles will occur. If the first bit is a '0,' one
or more READ cycles will occur (see Figure 11
and Figure 12., page 12).
Data transfers can occur one byte at a time or in
multiple byte burst mode, during which the ad-
dress pointer will be automatically incremented.
For a single byte transfer, one byte is read or writ-
ten and then E is driven high. For a multiple byte
transfer all that is required is that E continue to re-
main low. Under this condition, the address pointer
will continue to increment as stated previously. In-
crementing will continue until the device is dese-
lected by taking E high. The address will wrap to
00h after incrementing to 3Fh.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). Although the clock contin-
ues to maintain the correct time, this will prevent
updates of time and date during either a READ or
WRITE of these address locations by the user.
The update will resume either due to a deselect
condition or when the pointer increments to an
non-clock or RAM address (08h to 3Fh).
Note: This is true both in READ and WRITE mode.
Data Retention ModeWith valid VCC applied, the M41T94 can be ac-
cessed as described above with READ or WRITE
cycles. Should the supply voltage decay, the
M41T94 will automatically deselect, write protect-
ing itself when VCC falls between VPFD (max) and
VPFD (min) (see Figure 19., page 25). At this time,
the Reset pin (RST) is driven active and will re-
main active until VCC returns to nominal levels.
When VCC falls below the switch-over voltage
(VSO), power input is switched from the VCC pin to
the SNAPHAT battery (or external battery for
SO16) at this time, and the clock registers are
maintained from the attached battery supply. All
outputs become high impedance. On power up,
when VCC returns to a nominal value, write protec-
tion continues for tREC by internally inhibiting E.
The RST signal also remains active during this
time (see Figure 19., page 25). Before the next ac-
tive cycle, Chip Enable should be taken high for at
least tEHEL, then low.
For a further more detailed review of battery life-
time calculations, please see Application Note
AN1012.
M41T94
13/32
M41T94
CLOCK OPERATIONSThe eight byte clock register (see Table
4., page 14) is used to both set the clock and to
read the date and time from the clock, in a binary
coded decimal format. Tenths/Hundredths of Sec-
onds, Seconds, Minutes, and Hours are contained
within the first four registers. Bits D6 and D7 of
Clock Register 03h (Century/Hours Register) con-
tain the CENTURY ENABLE Bit (CEB) and the
CENTURY Bit (CB). Setting CEB to a '1' will cause
CB to toggle, either from '0' to '1' or from '1' to '0' at
the turn of the century (depending upon its initial
state). If CEB is set to a '0,' CB will not toggle. Bits
D0 through D2 of Register 04h contain the Day
(day of week). Registers 05h, 06h, and 07h con-
tain the Date (day of month), Month and Years.
The ninth clock register is the Control Register
(this is described in the Clock Calibration section).
Bit D7 of Register 01h contains the STOP Bit (ST).
Setting this bit to a '1' will cause the oscillator to
stop. If the device is expected to spend a signifi-
cant amount of time on the shelf, the oscillator may
be stopped to reduce current drain. When reset to
a '0' the oscillator restarts within one second.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 08h) may be accessed in-
dependently. Provision has been made to assure
that a clock update does not occur while any of the
eight clock addresses are being read. If a clock ad-
dress is being read, an update of the clock regis-
ters will be halted. This will prevent a transition of
data during the READ.
Power-down Time-StampWhen a power failure occurs, the Halt Update Bit
(HT) will automatically be set to a '1.' This will pre-
vent the clock from updating the clock registers,
and will allow the user to read the exact time of the
power-down event. Resetting the HT Bit to a '0' will
allow the clock to update the clock registers with
the current time. For more information, see Appli-
cation Note AN1572.
TIMEKEEPER® RegistersThe M41T94 offers 20 internal registers which
contain Clock, Alarm, Watchdog, Flag, Square
Wave and Control data (see Table 4., page 14).
These registers are memory locations which con-
tain external (user accessible) and internal copies
of the data (usually referred to as BiPORT™ TIME-
KEEPER cells). The external copies are indepen-
dent of internal functions except that they are
updated periodically by the simultaneous transfer
of the incremented internal copy. The internal di-
vider (or clock) chain will be reset upon the com-
pletion of a WRITE to any clock address.
The system-to-user transfer of clock data will be
halted whenever the clock addresses (00h to 07h)
are being written. The update will resume either
due to a deselect condition or when the pointer in-
crements to a non-clock or RAM address.
TIMEKEEPER and Alarm Registers store data in
BCD. Control, Watchdog and Square Wave Reg-
isters store data in Binary format.
M41T94
Table 4. TIMEKEEPER® Register MapKeys: S = Sign Bit
FT = Frequency Test Bit
ST = Stop Bit
0 = Must be set to zero
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Century Bit
OUT = Output level
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag (Read only)
AF = Alarm flag (Read only)
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
HT = Halt Update Bit
TR = tREC Bit
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M41T94
Setting Alarm Clock RegistersAddress locations 0Ah-0Eh contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second, or repeat every year, month,
day, hour, minute, or second. It can also be pro-
grammed to go off while the M41T94 is in the bat-
tery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 5., page 15 shows the possible
configurations. Codes not listed in the table default
to the once per second mode to quickly alert the
user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT/OUT pin.
Note: If the address pointer is allowed to incre-ment to the Flag Register address, an alarm con-
dition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different ad-
dress. It should also be noted that if the last ad-
dress written is the “Alarm Seconds,” the address
pointer will increment to the Flag address, causing
this situation to occur.
To disable the alarm, write '0' to the Alarm Date
Register and to RPT1–5. The IRQ/FT/OUT output
is cleared by a READ to the Flags Register. This
READ of the Flags Register will also reset the
Alarm Flag (D6; Register 0Fh). See Figure
13., page 15.
The IRQ/FT/OUT pin can also be activated in the
battery back-up mode. The IRQ/FT/OUT will go
low if an alarm occurs and both ABE (Alarm in Bat-
tery Back-up Mode Enable) and AFE are set. The
ABE and AFE Bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M41T94 was in the deselect
mode during power-up. Figure 14., page 16 illus-
trates the back-up mode alarm timing.
M41T94The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolu-
tion, where 00=1 /16 second, 01=1 /4 second,= 1 second, and 11= 4 seconds. The amount
of time-out is then determined to be the multiplica-
tion of the five-bit multiplier value with the resolu-
tion. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M41T94 sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (0Fh).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0,' the watchdog will activate the IRQ/FT/OUT
pin when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on the RST
pin for tREC. The Watchdog register and the AFE,
ABE, SQWE, and FT Bits will reset to a '0' at the
end of a Watchdog time-out when the WDS Bit is
set to a '1.'
The watchdog timer can be reset by two methods: a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI), or the microprocessor can perform a WRITE of
the Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to VSS if not used. In order to per-
form a software reset of the watchdog timer, the
original time-out period can be written into the
Watchdog Register, effectively restarting the
count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT/OUT pin. This will also
disable the watchdog function until it is again pro-
grammed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT/OUT pin and the Frequency Test (FT)
function is activated, the watchdog function pre-
vails and the Frequency Test function is denied.
