M41T81M6E ,Serial Access Real-Time Clock with AlarmsElectrical Characteristics . . .22Figure 19.Power Down/Up Mode AC Waveforms . . . . . . 23 ..
M41T81M6F ,Serial Access Real-Time Clock with AlarmsM41T81Serial Access Real-Time Clock with Alarms
M41T81M6TR ,Serial Access Real-Time Clock with AlarmsAbsolute Maximum Ratings . . . . . . . 20DC AND AC PARAMETERS . 21Table 7. Operating and ..
M41T81MX6 ,Serial Access Real-Time Clock with AlarmsLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. 8-pin SOIC (M) Connections ..
M41T81S ,Serial Access Real-Time Clock with AlarmsElectrical Characteristics . . .21Figure 17.Power Down/Up Mode AC Waveforms . . . . . . 22 ..
M41T81SM6E ,Serial Access Real-Time Clock with AlarmsBlock Diagram . . 5OPERATION . . . . . . 62-Wire Bus Characteristics . . . . . ..
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208KV-10LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V208KV-12LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V216ATP-55HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V216ATP-70HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M41T81M6-M41T81M6E-M41T81M6F-M41T81M6TR-M41T81MX6
Serial Access Real-Time Clock with Alarms
1/30September 2004
M41T81Serial Access Real-Time Clock with Alarms
FEATURES SUMMARY 2.0 TO 5.5V CLOCK OPERATING VOLTAGE COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY SERIAL INTERFACE SUPPORTS I2 C BUS
(400kHz PROTOCOL) PROGRAMMABLE ALARM AND
INTERRUPT FUNCTION (VALID EVEN
DURING BATTERY BACK-UP MODE) WATCHDOG TIMER POWER-DOWN TIME-STAMP (HT Bit) LOW OPERATING CURRENT OF 400µA BATTERY BACK-UP NOT RECOMMENDED
FOR 3.0V APPLICATIONS (CAPACITOR
BACK-UP ONLY) BATTERY OR SUPER-CAP BACK-UP OPERATING TEMPERATURE OF –40 TO
85°C ULTRA-LOW BATTERY SUPPLY CURRENT
OF 1µA PACKAGE OPTIONS INCLUDE A 28-LEAD
OR 18-LEAD EMBEDDED CRYSTAL SOIC
M41T81
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. 8-pin SOIC (M) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. 28-pin, 300mil SOIC (MX) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. 18-pin, 300mil SOIC (MY) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. Dual Footprint Connections (28-pin to 18-pin). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 8. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 9. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 10.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 11.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 12.Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 13.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Power-down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 2. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Figure 14.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 15.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Figure 16.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 17.Back-up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 3. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table 4. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3/30
M41T81
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Preferred Initial Power-on Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 5. Preferred Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 18.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 10. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 19.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 11. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 12. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 20.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 13. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Figure 21.SO8 – 8-lead Plastic Small Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 14. SO8 – 8-lead Plastic Small Outline (150 mils body width), Package Mechanical Data. .25
Figure 22.SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline.26
Table 15. SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Mech. .26
Figure 23.SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline.27
Table 16. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Mech. .27
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
M41T81
SUMMARY DESCRIPTIONThe M41T81 Serial Access TIMEKEEPER®
SRAM is a low power Serial RTC with a built-in
32.768kHz oscillator (external crystal controlled).
Eight bytes of the SRAM (see Table 2., page 13)
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
An additional 12 bytes of SRAM provide status/
control of Alarm, Watchdog and Square Wave
functions. Addresses and data are transferred se-
rially via a two line, bi-directional I2 C interface. The
built-in address register is incremented automati-
cally after each WRITE or READ data byte.
The M41T81 has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power fail-
ure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
small lithium button supply when a power failure
occurs.
Functions available to the user include a non-vol-
atile, time-of-day clock/calendar, Alarm interrupts,
Watchdog Timer and programmable Square
Wave output. The eight clock address locations
contain the century, year, month, date, day, hour,
minute, second and tenths/hundredths of a sec-
ond in 24 hour BCD format. Corrections for 28, 29
(leap year - valid until year 2100), 30 and 31 day
months are made automatically.
The M41T81 is supplied in either an 8-pin SOIC or
an 18-pin (MY) or 28-pin (MX), 300mil SOIC pack-
age which includes an embedded 32kHz crystal.
The 18-pin and 28-pin, embedded crystal SOIC re-
quires only a user-supplied battery to provide non-
volatile operation.
Table 1. Signal NamesNote:1. For SO8 package only.
5/30
M41T81
M41T81
Figure 7. Block DiagramNote:1. Open drain output Square Wave function has the highest priority on IRQ/FT/OUT/SQW output. VSO = VBAT – 0.5V (typ)
7/30
M41T81
OPERATIONThe M41T81 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (D0h). The 20 bytes contained in the device
can then be accessed sequentially in the following
order: Tenths/Hundredths of a Second Register Seconds Register Minutes Register Century/Hours Register Day Register Date Register Month Register Year Register Control Register
10. Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20. Square Wave Register
The M41T81 clock continually monitors VCC for an
out-of-tolerance condition. Should VCC fall below
VSO, the device terminates an access in progress
and resets the device address counter. Inputs to
the device will not be recognized at this time to
prevent erroneous data from being written to the
device from a an out-of-tolerance system. The de-
vice also automatically switches over to the battery
and powers down into an ultra low current mode of
operation to conserve battery life. As system pow-
er returns and VCC rises above VSO, the battery is
disconnected, and the power supply is switched to
external VCC.
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus CharacteristicsThe bus is intended for communication between
different ICs. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the
bus is not busy. During data transfer, the data line must remain
stable whenever the clock line is High. Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from high to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
M41T81
Figure 8. Serial Bus Data Transfer Sequence
Figure 9. Acknowledgement Sequence
9/30
M41T81
READ ModeIn this mode the master reads the M41T81 slave
after setting the slave address (see Figure
11., page 10). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address 'An' is written to the on-chip address
pointer. Next the START condition and slave ad-
dress are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master trans-
mitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an Acknowledge Bit to
the slave transmitter. The address pointer is only
incremented on reception of an Acknowledge
Clock. The M41T81 slave transmitter will now
place the data byte at address An+1 on the bus,
the master receiver reads and acknowledges the
new byte and the address pointer is incremented
to “An+2.”
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume due
to a Stop Condition or when the pointer increments
to any non-clock address (08h-13h).
Note: This is true both in READ Mode and WRITEMode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41T81 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 12., page 10).
M41T81
11/30
M41T81
WRITE ModeIn this mode the master transmitter transmits to
the M41T81 slave receiver. Bus protocol is shown
in Figure 13., page 11. Following the START con-
dition and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next address location on the reception of an
acknowledge clock. The M41T81 slave receiver
will send an acknowledge clock to the master
transmitter after it has received the slave address
see Figure 10., page 9 and again after it has re-
ceived the word address and each data byte.
Data Retention ModeWith valid VCC applied, the M41T81 can be ac-
cessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the pow-
er input will be switched from the VCC pin to the
battery when VCC falls below the Battery Back-up
Switchover Voltage (VSO). At this time the clock
registers will be maintained by the attached bat-
tery supply. On power-up, when VCC returns to a
nominal value, write protection continues for trec
(see Figure 19., page 23, Table 11., page 23).
For a further, more detailed review of lifetime cal-
culations, please see Application Note AN1012.
M41T81
CLOCK OPERATIONThe 20-byte Register Map (see Table 2., page 13)
is used to both set the clock and to read the date
and time from the clock, in a binary coded decimal
format. Tenths/Hundredths of Seconds, Seconds,
Minutes, and Hours are contained within the first
four registers.
Note: The Tenths/Hundredths of Seconds cannotbe written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (de-
pending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Control Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h con-
tains the STOP Bit (ST). Setting this bit to a '1' will
cause the oscillator to stop. If the device is expect-
ed to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce cur-
rent drain. When reset to a '0' the oscillator restarts
within one second.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. Provision has been
made to assure that a clock update does not occur
while any of the eight clock addresses are being
read. If a clock address is being read, an update of
the clock registers will be halted. This will prevent
a transition of data during the READ.
Power-down Time-StampWhen a power failure occurs, the HT Bit will auto-
matically be set to a '1.' This will prevent the clock
from updating the TIMEKEEPER® registers, and
will allow the user to read the exact time of the
power-down event. Resetting the HT Bit to a '0' will
allow the clock to update the TIMEKEEPER regis-
ters with the current time. For more information,
see Application Note AN1572.
TIMEKEEPER® RegistersThe M41T81 offers 20 internal registers which
contain Clock, Alarm, Watchdog, Flag, Square
Wave and Control data. These registers are mem-
ory locations which contain external (user accessi-
ble) and internal copies of the data (usually
referred to as BiPORT™ TIMEKEEPER cells). The
external copies are independent of internal func-
tions except that they are updated periodically by
the simultaneous transfer of the incremented inter-
nal copy. The internal divider (or clock) chain will
be reset upon the completion of a WRITE to any
clock address.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to any non-clock address (08h-13h).
TIMEKEEPER and Alarm Registers store data in
BCD. Control, Watchdog and Square Wave Reg-
isters store data in Binary Format.
13/30
M41T81
Table 2. TIMEKEEPER® Register MapKeys: S = Sign Bit
FT = Frequency Test Bit
ST = Stop Bit
0 = Must be set to '0'
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Century Bit
OUT = Output level
ABE = Alarm in Battery Back-up Mode Enable Bit
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog Flag (Read only)
AF = Alarm Flag (Read only)
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
HT = Halt Update Bit
M41T81
Calibrating the ClockThe M41T81 is driven by a quartz controlled oscil-
lator with a nominal frequency of 32,768Hz. The
devices are tested not exceed –25 to +45 ppm
(parts per million) oscillator frequency error ato C, which equates to about +1.9 to –1.1 minutes
per month (see Figure 14., page 15). When the
Calibration circuit is properly employed, accuracy
improves to better than ±2 ppm at 25°C.
The oscillation rate of crystals changes with tem-
perature. The M41T81 design employs periodic
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure
15., page 15. The number of times pulses which
are blanked (subtracted, negative calibration) or
split (added, positive calibration) depends upon
the value loaded into the five Calibration Bits found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Control Register 08h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register (see Figure
15., page 15). Assuming that the oscillator is run-
ning at exactly 32,768Hz, each of the 31 incre-
ments in the Calibration byte would represent
+10.7 or –5.35 seconds per month which corre-
sponds to a total range of +5.5 or –2.75 minutes
per month.
Two methods are available for ascertaining how
much calibration a given M41T81 may require.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate ref-
erence and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934, “TIMEKEEP-® CALIBRATION.” This allows the designer to
give the end user the ability to calibrate the clock
as the environment requires, even if the final prod-
uct is packaged in a non-user serviceable enclo-
sure. The designer could provide a simple utility
that accesses the Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT/OUT/SQW pin. The pin will toggle at
512Hz, when the Stop Bit (ST, D7 of 01h) is '0,' the
Frequency Test Bit (FT, D6 of 08h) is '1,' the Alarm
Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the
Square Wave Enable Bit (SQWE, D6 of 0Ah) is '0'
and the Watchdog Register (09h = 0) is reset.
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (XX001010) to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency.
The IRQ/FT/OUT/SQW pin is an open drain output
which requires a pull-up resistor to VCC for proper
operation. A 500-10k resistor is recommended in
order to control the rise time. The FT Bit is cleared
on power-down.
15/30
M41T81
Figure 14. Crystal Accuracy Across Temperature
Figure 15. Clock Calibration
