M41T81 ,512 BIT (64 BIT SERIAL ACCESS RTC SRAM WITH ALARMSElectrical Characteristics (Table 6.) . . . . 8OPERATION . . . . . . 92-Wire Bus Charac ..
M41T81 ,512 BIT (64 BIT SERIAL ACCESS RTC SRAM WITH ALARMSLogic Diagram Table 1. Signal Names(1)(1)Oscillator InputV VXICC BAT(1)Oscillator OutputXOIRQ/OUT/ ..
M41T81M6 ,Serial Access Real-Time Clock with AlarmsBlock Diagram . . 6OPERATION . . . . . . 72-Wire Bus Characteristics . . . . . ..
M41T81M6 ,Serial Access Real-Time Clock with AlarmsAPPLICATIONS (CAPACITOR BACK-UP ONLY)18■ BATTERY OR SUPER-CAP BACK-UP■ OPERATING TEMPERATURE OF –40 ..
M41T81M6E ,Serial Access Real-Time Clock with AlarmsElectrical Characteristics . . .22Figure 19.Power Down/Up Mode AC Waveforms . . . . . . 23 ..
M41T81M6F ,Serial Access Real-Time Clock with AlarmsM41T81Serial Access Real-Time Clock with Alarms
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208KV-10LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V208KV-12LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V216ATP-55HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V216ATP-70HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M41T81
512 BIT (64 BIT SERIAL ACCESS RTC SRAM WITH ALARMS
1/29October 2002
M41T81SERIAL ACCESS RTC WITH ALARMS
* Contact Local Sales Office
FEATURES SUMMARY 2.0 TO 5.5V CLOCK OPERATING VOLTAGE COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, and
CENTURY AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY SERIAL INTERFACE SUPPORTS I2 C BUS
(400KHz PROTOCOL) PROGRAMMABLE ALARM and INTERRUPT
FUNCTION (valid even during Battery Back-up
Mode) WATCHDOG TIMER LOW OPERATING CURRENT OF 400μA BATTERY BACK-UP NOT RECOMMENDED
FOR 3.0V APPLICATIONS (CAPACITOR
BACK-UP ONLY) BATTERY OR SUPER-CAP BACK-UP OPERATING TEMPERATURE OF –40 TO
85°C ULTRA-LOW BATTERY SUPPLY CURRENT
OF 1μA
Figure 1. 8-pin SOIC Package
Figure 2. 28-pin SOIC Package*
M41T81
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Logic Diagram (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
8-pin SOIC Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
28-pin SOIC Connections (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Block Diagram (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
AC Measurement I/O Waveform (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Crystal Electrical Characteristics (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Serial Bus Data Transfer Sequence (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Acknowledgement Sequence (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Bus Timing Requirements Sequence (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Slave Address Location (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
READ Mode Sequence (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Alternative READ Mode Sequence (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
WRITE Mode Sequence (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Power Down/Up Mode AC Waveforms (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Power Down/Up AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Power Down/Up Trip Points DC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3/29
M41T81
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15TIMEKEEPER® Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
TIMEKEEPER® Register Map (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Calibrating the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Alarm Interrupt Reset Waveform (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Back-up Mode Alarm Waveform (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Alarm Repeat Modes (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Square Wave Output Frequency (Table 12.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Preferred Initial Power-on Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Preferred Default Values (Table 13.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Crystal Accuracy Across Temperature (Figure 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Clock Calibration (Figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23SNAPHAT Battery/Crystal Table (Table 15.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
M41T81
SUMMARY DESCRIPTIONThe M41T81 Serial Access TIMEKEEPER®
SRAM is a low power Serial RTC with a built-in
32.768 KHz oscillator (external crystal controlled).
Eight bytes of the SRAM (see Table 10, page 16)
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
An additional 12 bytes of SRAM provide status/
control of Alarm, Watchdog and Square Wave
functions. Addresses and data are transferred se-
rially via a two line, bi-directional I2 C interface. The
built-in address register is incremented automati-
cally after each WRITE or READ data byte.
The M41T81 has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power fail-
ure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
small lithium button supply when a power failure
occurs. Functions available to the user include a
non-volatile, time-of-day clock/calendar, Alarm in-
terrupts, Watchdog Timer and programmable
Square Wave output. The eight clock address lo-
cations contain the century, year, month, date,
day, hour, minute, second and tenths/hundredths
of a second in 24 hour BCD format. Corrections for
28, 29 (leap year - valid until year 2100), 30 and 31
day months are made automatically.
The M41T81 is supplied in either an 8-pin SOIC or
a 28-lead SOIC SNAPHAT® package (which inte-
grates both crystal and battery in a single
SNAPHAT top). The 28-pin, 330mil SOIC provides
sockets with gold plated contacts at both ends for
direct connection to a separate SNAPHAT hous-
ing containing the battery and crystal. The unique
design allows the SNAPHAT battery/crystal pack-
age to be mounted on top of the SOIC package af-
ter the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is “M4TXX-BR12SH” (see Table 15, page 23).
Caution: Do not place the SNAPHAT battery/crys-tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
Figure 3. Logic DiagramNote:1. For SO8 package only.
Table 1. Signal NamesNote:1. For SO8 package only
5/29
M41T81
Figure 4. 8-pin SOIC Connections Figure 5. 28-pin SOIC Connections
Figure 6. Block Diagram
M41T81
MAXIMUM RATINGStressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum RatingsNote:1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-Up Mode
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT socket.
7/29
M41T81
DC AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement ConditionsNote: Output Hi-Z is defined as the point where data is no longer driven.
Figure 7. AC Measurement I/O Waveform
Table 4. CapacitanceNote:1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. At 25°C, f = 1MHz. Outputs deselected.
M41T81
Table 5. DC CharacteristicsNote:1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted). STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply. After switchover (VSO), VBAT (min) can be 2.0V for crystal with RS = 40KΩ. For rechargeable back-up, VBAT (max) may be considered VCC. For IRQ/FT/OUT/SQW pin (Open Drain)
Table 6. Crystal Electrical CharacteristicsNote:1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork
Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be con-
tacted at
[email protected] or http://www.kdsj.co.jp for further information on this crystal type. Load capacitors are integrated within the M41T81. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account. All SNAPHAT® battery/crystal tops meet these specifications.
9/29
M41T81
OPERATIONThe M41T81 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (D0h). The 20 bytes contained in the device
can then be accessed sequentially in the following
order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Control Register
10. Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20. Square Wave Register
The M41T81 clock continually monitors VCC for an
out-of-tolerance condition. Should VCC fall below
VSO, the device terminates an access in progress
and resets the device address counter. Inputs to
the device will not be recognized at this time to
prevent erroneous data from being written to the
device from a an out-of-tolerance system. The de-
vice also automatically switches over to the battery
and powers down into an ultra low current mode of
operation to conserve battery life. As system pow-
er returns and VCC rises above VSO, the battery is
disconnected, and the power supply is switched to
external VCC.
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus CharacteristicsThe bus is intended for communication between
different IC’s. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the bus
is not busy. During data transfer, the data line must remain
stable whenever the clock line is High. Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from high to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
M41T81
Figure 8. Serial Bus Data Transfer Sequence
Figure 9. Acknowledgement Sequence
11/29
M41T81
Figure 10. Bus Timing Requirements Sequence
Table 7. AC CharacteristicsNote:1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted). Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
M41T81
READ ModeIn this mode the master reads the M41T81 slave
after setting the slave address (see Figure 12,
page 12). Following the WRITE Mode Control Bit
(R/W=0) and the Acknowledge Bit, the word ad-
dress 'An' is written to the on-chip address pointer.
Next the START condition and slave address are
repeated followed by the READ Mode Control Bit
(R/W=1). At this point the master transmitter be-
comes the master receiver. The data byte which
was addressed will be transmitted and the master
receiver will send an Acknowledge Bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an Acknowledge Clock. The
M41T81 slave transmitter will now place the data
byte at address An+1 on the bus, the master re-
ceiver reads and acknowledges the new byte and
the address pointer is incremented to “An+2.”
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume due
to a Stop Condition or when the pointer increments
to any non-clock address (08h-13h).
Note: This is true both in READ Mode and WRITEMode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41T81 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 13, page 13).
Figure 11. Slave Address Location
Figure 12. READ Mode Sequence
13/29
M41T81
Figure 13. Alternative READ Mode Sequence
WRITE ModeIn this mode the master transmitter transmits to
the M41T81 slave receiver. Bus protocol is shown
in Figure 14, page 13. Following the START con-
dition and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next address location on the reception of an
acknowledge clock. The M41T81 slave receiver
will send an acknowledge clock to the master
transmitter after it has received the slave address
see Figure 11, page 12 and again after it has re-
ceived the word address and each data byte.
Figure 14. WRITE Mode Sequence
M41T81
Data Retention ModeWith valid VCC applied, the M41T81 can be ac-
cessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the pow-
er input will be switched from the VCC pin to the
battery when VCC falls below the Battery Back-up
Switchover Voltage (VSO). At this time the clock
registers will be maintained by the attached bat-
tery supply. As VCC continues to fall, the M41T81
will pass through the Register Bit Reset Voltage
(VRST) threshold, not only write protecting itself,
but also resetting certain Control Bits (see Table
13, page 21). On power-up, when VCC returns to a
nominal value, write protection continues for tREC.
For a further, more detailed review of lifetime cal-
culations, please see Application Note AN1012.
Figure 15. Power Down/Up Mode AC Waveforms
Table 8. Power Down/Up AC CharacteristicsNote:1. VCC fall time should not exceed 5mV/μs. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted).
Table 9. Power Down/Up Trip Points DC CharacteristicsNote:1. All voltages referenced to VSS. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted).
15/29
M41T81
CLOCK OPERATIONThe 20-byte Register Map (see Table 10, page 16)
is used to both set the clock and to read the date
and time from the clock, in a binary coded decimal
format. Tenths/Hundredths of Seconds, Seconds,
Minutes, and Hours are contained within the first
four registers.
Note: A WRITE to any clock register will result inthe Tenths/Hundredths of Seconds being reset to
“00,” and Tenths/Hundredths of Seconds cannot
be written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (de-
pending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Control Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h con-
tains the STOP Bit (ST). Setting this bit to a '1' will
cause the oscillator to stop. If the device is expect-
ed to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce cur-
rent drain. When reset to a '0' the oscillator restarts
within one second.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 08h) may be accessed in-
dependently. Provision has been made to assure
that a clock update does not occur while any of the
eight clock addresses are being read. If a clock ad-
dress is being read, an update of the clock regis-
ters will be halted. This will prevent a transition of
data during the READ.
Note: When a power failure occurs, the HT Bit willautomatically be set to a '1.' This will prevent the
clock from updating the TIMEKEEPER® registers,
and will allow the user to read the exact time of the
power-down event. Resetting the HT Bit to a '0' will
allow the clock to update the TIMEKEEPER regis-
ters with the current time.
TIMEKEEPER® RegistersThe M41T81 offers 20 internal registers which
contain Clock, Alarm, Watchdog, Flag, Square
Wave and Control data. These registers are mem-
ory locations which contain external (user accessi-
ble) and internal copies of the data (usually
referred to as BiPORT™ TIMEKEEPER cells). The
external copies are independent of internal func-
tions except that they are updated periodically by
the simultaneous transfer of the incremented inter-
nal copy. The internal divider (or clock) chain will
be reset upon the completion of a WRITE to any
clock address.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to any non-clock address (08h-13h).
TIMEKEEPER and Alarm Registers store data in
BCD. Control, Watchdog and Square Wave Reg-
isters store data in Binary Format.
