M41T66Q6F ,Serial real-time clock (RTC) with alarmblock diagram . . . . . 6Figure 4. Hardware hookup for SuperCap™ backup operation . . . . . ..
M41T80 ,SERIAL ACCESS RTC WITH ALARMSElectrical Characteristics (Table 6.) . . . . 6OPERATION . . . . . . 72-Wire Bus Charac ..
M41T80M6 ,Serial Access RTC with AlarmsLogic DiagramV Table 1. Signal NamesCCXI Oscillator InputXO Oscillator OutputXIIRQ/OUT/ Interrupt / ..
M41T80M6E ,Serial Access RTC with AlarmsLogic Diagram . . 1Figure 2. Package . . . . . . . 1Table 1. Signal Names . . 1 ..
M41T80M6F ,Serial Access RTC with AlarmsAbsolute Maximum Ratings . . . . . . . 14DC AND AC PARAMETERS . 152/20M41T80Table 8. Oper ..
M41T80M6F ,Serial Access RTC with AlarmsFEATURES SUMMARY■ 2.0 TO 5.5V CLOCK OPERATING VOLTAGE Figure 2. Package■ COUNTERS FOR TENTHS/HUNDRE ..
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208KV-10LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V208KV-12LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V216ATP-55HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V216ATP-70HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M41T66Q6F
Serial real-time clock (RTC) with alarm
October 2011 Doc ID 15108 Rev 2 1/41
M41T66Serial real-time clock with alarms
Features Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century 32 KHz crystal oscillator integrating load
capacitance and high crystal series resistance
operation Oscillator stop detection monitors clock
operation Serial interface supports I2 C bus (400 kHz) 525 nA timekeeping current at 3 V Low operating current of 35 µA (at 400 kHz) Timekeeping down to 1.0 V 1.3 V to 4.4 V I2 C bus operating voltage Allows use in lithium ion rechargeable
applications 32 KHz square wave on power-up to drive a
microcontroller in low-power mode Programmable (1 Hz to 32 KHz) square wave Programmable alarm with interrupt function Accurate programmable watchdog
(from 62.5 ms to 31 min) Software clock calibration to compensate
deviation of crystal due to temperature Automatic leap year compensation Operating temperature of –40 to 85 °C Lead-free 16-pin QFN package
Contents M41T662/34 Doc ID 15108 Rev 2
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.3 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.4 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.1 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8 Oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
M41T66 List of tables
Doc ID 15108 Rev 2 3/34
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. M41T66 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Initial power-on default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, mech. data . . . . . . . 29
Table 15. Carrier tape dimensions for QFN16 (3 mm x 3 mm) package . . . . . . . . . . . . . . . . . . . . . . 30
Table 16. Reel dimensions for 12 mm carrier tape - QFN16 package . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
List of figures M41T66
4/34 Doc ID 15108 Rev 2
List of figures
Figure 1. M41T66 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. M41T66 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. M41T66 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Hardware hookup for SuperCap™ backup operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 17. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline . . . . . . . . . . . 28
Figure 18. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended footprint . . . . . . 29
Figure 19. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 20. Carrier tape for QFN16 (3 mm x 3 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 21. Reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
M41T66 Description
Doc ID 15108 Rev 2 5/34
1 Description
The M41T66 is a low-power serial real-time clock (RTC) with a built-in 32.768 kHz oscillator
(external crystal controlled). Eight registers are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format. An additional 8 registers provide
status/control of alarm, square wave, calibration, and watchdog functions. Addresses and
data are transferred serially via a two line, bidirectional I2 C interface. The built-in address
register is incremented automatically after each WRITE or READ data byte.
Functions available to the user include a time-of-day clock/calendar, alarm interrupts,
programmable square wave output, and watchdog output. The eight clock address locations
contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a
second in 24-hour BCD format. Corrections for 28-, 29- (leap year), 30- and 31-day months
are made automatically.
The M41T66 is supplied in a 16-pin QFN.
Figure 1. M41T66 logic diagram Open drain Defaults to 32 KHz on power-up
Description M41T66
6/34 Doc ID 15108 Rev 2
Figure 2. M41T66 connections SQW output defaults to 32 KHz upon power-up Open drain
Figure 3. M41T66 block diagram Open drain Defaults to 32 KHz on power-up
Table 1. Signal names
M41T66 Description
Doc ID 15108 Rev 2 7/34
Figure 4. Hardware hookup for SuperCap™ backup operation Open drain For a crystal with a load capacitance (CL) of 12.5 pF, two parallel external 12.5 pF capacitors (C1 and C2)
must be added to achieve better clock accuracy. It can also be connected to another power supply. Due to the output buffer circuitry used for the SQW output, this pin must not be taken to a voltage greater
than VCC. Diode required on SQW pin for SuperCap™ (or battery) backup. Low threshold BAT42 diode
recommended.
Operation M41T66
8/34 Doc ID 15108 Rev 2
2 Operation
The M41T66 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 16 bytes
contained in the device can then be accessed sequentially in the following order: 1st byte: tenths/hundredths of a second register 2nd byte: seconds register 3rd byte: minutes register 4th byte: hours register 5th byte: square wave/day register 6th byte: date register 7th byte: century/month register 8th byte: year register 9th byte: calibration register 10th byte: watchdog register 11th - 15th bytes: alarm registers 16th byte: flags register
2.1 2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a
bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must
be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1 Bus not busy
Both data and clock lines remain high.
2.1.2 Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
2.1.3 Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
M41T66 Operation
Doc ID 15108 Rev 2 9/34
2.1.4 Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
2.1.5 Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte that has been clocked out of the slave
transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Figure 5. Serial bus data transfer sequence
Operation M41T66
10/34 Doc ID 15108 Rev 2
Figure 6. Acknowledgement sequence
2.2 READ mode
In this mode the master reads the M41T66 slave after setting the slave address (see
Figure 8 on page 11). Following the WRITE mode control bit (R/W=0) and the acknowledge
bit, the word address 'An' is written to the on-chip address pointer. Next the START condition
and slave address are repeated followed by the READ mode control bit (R/W=1). At this
point the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an acknowledge bit to the
slave transmitter. The address pointer is only incremented on reception of an acknowledge
clock. The M41T66 slave transmitter will now place the data byte at address An+1 on the
bus, the master receiver reads and acknowledges the new byte and the address pointer is
incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume due to a stop condition or when the
pointer increments to any non-clock address (08h-0Fh).
Note: This is true both in READ mode and WRITE mode.
An alternate READ mode may also be implemented whereby the master reads the M41T66
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 9 on page 11).
M41T66 Operation
Doc ID 15108 Rev 2 11/34
Figure 7. Slave address location
Figure 8. READ mode sequence
Figure 9. Alternative READ mode sequence
Operation M41T66
12/34 Doc ID 15108 Rev 2
2.3 WRITE mode
In this mode the master transmitter transmits to the M41T66 slave receiver. Bus protocol is
shown in Figure 10. Following the START condition and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed device that word address “An” will follow
and is to be written to the on-chip address pointer. The data word to be written to the
memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T66 slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
see Figure 7 on page 11 and again after it has received the word address and each data
byte.
Figure 10. WRITE mode sequence
M41T66 Clock operation
Doc ID 15108 Rev 2 13/34
3 Clock operation
The M41T66 is driven by a quartz-controlled oscillator with a nominal frequency of
32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz
crystal that is used as the time-base for the RTC.
The eight byte clock register (see Table 2: M41T66 register map) is used to both set the
clock and to read the date and time from the clock, in a binary coded decimal format.
tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first
four registers.
A WRITE to any clock register will result in the tenths/hundredths of seconds being reset to
“00,” and tenths/hundredths of seconds cannot be written to any value other than “00.”
Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and
07h contain the date (day of month), month, and years. The ninth clock register is the
calibration register (this is described in the clock calibration section). Bit D7 of register 01h
contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When
reset to a '0' the oscillator restarts within one second (typical).
Bit D7 of register 02h (minute register) contains the oscillator fail interrupt enable bit (OFIE).
When the user sets this bit to '1,' any condition which sets the oscillator fail bit (OF) (see
Oscillator stop detection on page 21) will also generate an interrupt output.
Bits D6 and D7 of clock register 06h (century/month register) contain the CENTURY bit 0
(CB0) and CENTURY bit 1 (CB1).
A WRITE to ANY location within the first eight bytes of the clock register (00h-07h),
including the OFIE bit, RS0-RS3 bit, and CB0-CB1 bits will result in an update of the system
clock and a reset of the divider chain. This could result in an inadvertent change of the
current time. These non-clock related bits should be written prior to setting the clock, and
remain unchanged until such time as a new clock time is also written.
The eight clock registers may be read one byte at a time, or in a sequential block. Provision
has been made to assure that a clock update does not occur while any of the eight clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.
Clock operation M41T66
14/34 Doc ID 15108 Rev 2
3.1 Clock registers
The M41T66 offers 16 internal registers which contain clock, calibration, alarm, watchdog,
flags, and square wave. The clock registers are memory locations which contain external
(user accessible) and internal copies of the data. The external copies are independent of
internal functions except that they are updated periodically by the simultaneous transfer of
the incremented internal copy. The internal divider (or clock) chain will be reset upon the
completion of a WRITE to any clock address (00h to 07h).
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume either due to a stop condition or when
the pointer increments to a non-clock address.
Clock and alarm registers store data in BCD format. calibration, watchdog, and square wave
bits are written in a binary format.
M41T66 Clock operation
Doc ID 15108 Rev 2 15/34
Table 2. M41T66 register map(1) Keys:
0 = must be set to '0'
AF = alarm flag (read only)
AFE = alarm flag enable flag
BMB0 - BMB4 = watchdog multiplier bits
CB0-CB1 = century bits
OF = oscillator fail bit
OFIE = oscillator fail interrupt enable bit
OUT = output level
RB0 - RB2 = watchdog resolution bits
RPT1-RPT5 = alarm repeat mode bits
RS0-RS3 = SQW frequency bits
S = sign bit
SQWE = square wave enable bit
ST = stop bit
WDF = watchdog flag bit (read only)
Clock operation M41T66
16/34 Doc ID 15108 Rev 2
3.2 Calibrating the clock
The M41T66 is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The accuracy of the real-time clock depends on the frequency of the quartz
crystal that is used as the time-base for the RTC. The accuracy of the clock is dependent
upon the accuracy of the crystal, and the match between the capacitive load of the oscillator
circuit and the capacitive load for which the crystal was trimmed. The M41T66 oscillator is
designed for use with a 6 pF crystal load capacitance. When the calibration circuit is
properly employed, accuracy improves to better than ±2 ppm at 25 °C. The M41T66’s
oscillator can drive the crystal’s load capacitance that is greater than 6 pF. External
capacitors must be added to achieve better clock accuracy (see Figure 4 on page7).
The oscillation rate of crystals changes with temperature (see Figure 11 on page 17).
Therefore, the M41T66 design employs periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as
shown in Figure 12 on page 17. The number of times pulses which are blanked (subtracted,
negative calibration) or split (added, positive calibration) depends upon the value loaded into
the five calibration bits found in the calibration register. Adding counts speeds the clock up,
subtracting counts slows the clock down.
The calibration bits occupy the five lower order bits (D4-D0) in the calibration register (08h).
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register.
Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in
the Calibration byte would represent +10.7 or –5.35 seconds per day which corresponds to
a total range of +5.5 or –2.75 minutes per month (see Figure 12 on page 17). wo methods are available for ascertaining how much calibration the M41T66 may require: The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. Calibration
values, including the number of seconds lost or gained in a given period, can be found
in application note AN934, “How to use the digital calibration feature in TIMEKEEPER®
and serial real-time clock (RTC) products.” This allows the designer to give the end user
the ability to calibrate the clock as the environment requires, even if the final product is
packaged in a non-user serviceable enclosure. The designer could provide a simple
utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the
use of the SQW pin. The SQW pin will toggle at 512 Hz when RS3 = '0,' RS2 = '1,'
RS1 = '1,' RS0 = '0,' SQWE = ‘1’ and ST = '0'.
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte
for correction. Note that setting or changing the calibration byte does not affect the square
wave output frequency.
M41T66 Clock operation
Doc ID 15108 Rev 2 17/34
Figure 11. Crystal accuracy across temperature
Figure 12. Calibration waveform
