M41T62Q6F ,Serial Access Real-Time Clock with AlarmsElectrical Characteristics . . .26Table 16. Oscillator Characteristics . 27Figure 26.Bus ..
M41T64Q6F ,Serial real-time clock (RTC) with alarmTable of contents1 Description . 62 Operation . 122.1 2-wire bus characteristics . ..
M41T65Q6F ,Serial Access Real-Time Clock with AlarmsBlock Diagram . . . 7Figure 14.Hardware Hookup for Battery Back-up Operation . . . . . . . 7 ..
M41T66Q6F ,Serial real-time clock (RTC) with alarmblock diagram . . . . . 6Figure 4. Hardware hookup for SuperCap™ backup operation . . . . . ..
M41T80 ,SERIAL ACCESS RTC WITH ALARMSElectrical Characteristics (Table 6.) . . . . 6OPERATION . . . . . . 72-Wire Bus Charac ..
M41T80M6 ,Serial Access RTC with AlarmsLogic DiagramV Table 1. Signal NamesCCXI Oscillator InputXO Oscillator OutputXIIRQ/OUT/ Interrupt / ..
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208KV-10LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V208KV-12LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V216ATP-55HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V216ATP-70HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M41T62Q6F-M41T65Q6F
Serial Access Real-Time Clock with Alarms
1/32January 2005
M41T62, M41T63
M41T64, M41T65Serial Access Real-Time Clock with Alarms
FEATURES SUMMARY 350nA TIMEKEEPING CURRENT @ 3V TIMEKEEPING DOWN TO 1.0V 1.3V TO 3.6V I2 C BUS OPERATING
VOLTAGE COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY SERIAL INTERFACE SUPPORTS I2 C BUS
(400kHz) PROGRAMMABLE ALARM WITH FLAG BIT
ONLY (M41T63/64) PROGRAMMABLE ALARM WITH FLAG BIT
AND INTERRUPT FUNCTION (M41T62/65) LOW OPERATING CURRENT OF 35µA SOFTWARE CLOCK CALIBRATION OSCILLATOR STOP DETECTION 32KHz SQUARE WAVE ON POWER-UP
(M41T62/63/64) WATCHDOG TIMER WATCHDOG OUTPUT (M41T63/65) AUTOMATIC LEAP YEAR COMPENSATION OPERATING TEMPERATURE OF –40 TO
85°C LEAD-FREE 16-PIN QFN PACKAGE
Table 1. Device Options
M41T62/63/64/65
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. M41T62 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. M41T64 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. M41T63 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 5. M41T65 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 6. M41T62 16-pin QFN Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 7. M41T63 16-pin QFN Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 8. M41T64 16-pin QFN Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 9. M41T65 16-pin QFN Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 10.M41T62 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 11.M41T63 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 12.M41T64 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 13.M41T65 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 14.Hardware Hookup for Battery Back-up Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 15.Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 16.Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 17.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 18.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 19.Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Figure 20.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Table 3. M41T62 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 4. M41T63 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 5. M41T64 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 6. M41T65 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3/32
M41T62/63/64/65Figure 21.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 22.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Figure 23.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 7. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Watchdog Output (WDO - M41T63/65 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Square Wave Output (M41T62/63/64). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 8. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Full-time 32KHz Square Wave Output (M41T64). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Century Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Output Driver Pin (M41T62/65) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Oscillator Stop Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 9. Initial Power-on Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 10. Century Bits Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Table 11. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Table 12. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 24.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 25.Crystal Isolation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 15. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 16. Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 26.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 17. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Figure 27.QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Outline . . . . . . . .28
Table 18. QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Mechanical Data.29
Figure 28.QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm, Recommended Footprint . .29
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
M41T62/63/64/65
SUMMARY DESCRIPTIONThe M41T6x Serial Access TIMEKEEPER® is a
low power Serial RTC with a built-in 32.768 kHz
oscillator (external crystal controlled). Eight regis-
ters (see Table 3., page 14) are used for the clock/
calendar function and are configured in binary
coded decimal (BCD) format. An additional 8 reg-
isters provide status/control of Alarm, 32KHz out-
put, Calibration, and Watchdog functions.
Addresses and data are transferred serially via a
two line, bi-directional I2 C interface. The built-in
address register is incremented automatically af-
ter each WRITE or READ data byte.
Functions available to the user include a time-of-
day clock/calendar, Alarm interrupts (M41T62/65),
32KHz output (M41T64), programmable Square
Wave output (M41T62/63/64), and Watchdog out-
put (M41T63/65). The eight clock address loca-
tions contain the century, year, month, date, day,
hour, minute, second and tenths/hundredths of a
second in 24 hour BCD format. Corrections for 28-
, 29- (leap year), 30- and 31-day months are made
automatically.
The M41T6x is supplied in a 16-pin QFN.
5/32
M41T62/63/64/65
M41T62/63/64/65
Figure 10. M41T62 Block DiagramNote:1. Open Drain. Defaults to 32KHz on power-up.
Figure 11. M41T63 Block DiagramNote:1. Open Drain. Defaults to 32KHz on power-up.
Figure 12. M41T64 Block DiagramNote:1. Defaults enabled on power-up. Open Drain.
7/32
M41T62/63/64/65
Figure 13. M41T65 Block DiagramNote:1. Open Drain.
Figure 14. Hardware Hookup for Battery Back-up OperationNote:1. Diode required on open drain pin (M41T65 only) for battery (or SuperCap) back-up. Low threshold BAT42 diode recommended. For M41T62 and M41T65 (Open Drain). For M41T63 and M41T65 (Open Drain). For M41T64 (Open Drain).
M41T62/63/64/65
OPERATIONThe M41T6x clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (D0h). The 16 bytes contained in the device
can then be accessed sequentially in the following
order: Tenths/Hundredths of a Second Register Seconds Register Minutes Register Hours Register Square Wave/Day Register Date Register Century/Month Register Year Register Calibration Register
10. Watchdog Register
11 - 15. Alarm Registers
16. Flags Register
2-Wire Bus CharacteristicsThe bus is intended for communication between
different ICs. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the
bus is not busy. During data transfer, the data line must remain
stable whenever the clock line is High. Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from high to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
9/32
M41T62/63/64/65
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
Figure 15. Serial Bus Data Transfer Sequence
Figure 16. Acknowledgement Sequence
M41T62/63/64/65
READ ModeIn this mode the master reads the M41T6x slave
after setting the slave address (see Figure
18., page 11). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address 'An' is written to the on-chip address
pointer. Next the START condition and slave ad-
dress are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master trans-
mitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an Acknowledge Bit to
the slave transmitter. The address pointer is only
incremented on reception of an Acknowledge
Clock. The M41T6x slave transmitter will now
place the data byte at address An+1 on the bus,
the master receiver reads and acknowledges the
new byte and the address pointer is incremented
to “An+2.”
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume due
to a Stop Condition or when the pointer increments
to any non-clock address (08h-0Fh).
Note: This is true both in READ Mode and WRITEMode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41T6x slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 19., page 11).
11/32
M41T62/63/64/65
M41T62/63/64/65
WRITE ModeIn this mode the master transmitter transmits to
the M41T6x slave receiver. Bus protocol is shown
in Figure 20., page 12. Following the START con-
dition and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next address location on the reception of an
acknowledge clock. The M41T6x slave receiver
will send an acknowledge clock to the master
transmitter after it has received the slave address
see Figure 17., page 10 and again after it has re-
ceived the word address and each data byte.
13/32
M41T62/63/64/65
CLOCK OPERATIONThe M41T6x is driven by a quartz-controlled oscil-
lator with a nominal frequency of 32.768kHz. The
accuracy of the Real-Time Clock depends on the
frequency of the quartz crystal that is used as the
time-base for the RTC.
The eight byte clock register (see Table
3., M41T62 Register Map, Table 4., M41T63 Reg-
ister Map, Table 5., M41T64 Register Map, and
Table 6., M41T65 Register Map) is used to both
set the clock and to read the date and time from
the clock, in a binary coded decimal format.
Tenths/Hundredths of Seconds, Seconds, Min-
utes, and Hours are contained within the first four
registers.
Note: A WRITE to any clock register will result inthe Tenths/Hundredths of Seconds being reset to
“00,” and Tenths/Hundredths of Seconds cannot
be written to any value other than “00.”
Bits D0 through D2 of Register 04h contain the
Day (day of week). Registers 05h, 06h, and 07h
contain the Date (day of month), Month, and
Years. The ninth clock register is the Calibration
Register (this is described in the Clock Calibration
section). Bit D7 of Register 01h contains the STOP
Bit (ST). Setting this bit to a '1' will cause the oscil-
lator to stop. When reset to a '0' the oscillator re-
starts within one second (typical).
Note: Upon initial power-up, the user should setthe ST Bit to a '1,' then immediately reset the ST
Bit to '0.' This provides an additional “kick-start” to
the oscillator circuit.
Bit D7 of Register 02h (Minute Register) contains
the Oscillator Fail Interrupt Enable Bit (OFIE).
When the user sets this bit to '1,' any condition
which sets the Oscillator Fail Bit (OF) (see Oscilla-
tor Stop Detection, page 23) will also generate an
interrupt output.
Bits D6 and D7 of Clock Register 06h (Century/
Month Register) contain the CENTURY Bit 0
(CB0) and CENTURY Bit 1 (CB1).
Note: A WRITE to ANY location within the firsteight bytes of the clock register (00h-07h), includ-
ing the OFIE Bit, RS0-RS3 Bit, and CB0-CB1 Bits
will result in an update of the system clock and a
reset of the divider chain. This could result in an in-
advertent change of the current time. These non-
clock related bits should be written prior to setting
the clock, and remain unchanged until such time
as a new clock time is also written.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. Provision has been
made to assure that a clock update does not occur
while any of the eight clock addresses are being
read. If a clock address is being read, an update of
the clock registers will be halted. This will prevent
a transition of data during the READ.
TIMEKEEPER® RegistersThe M41T6x offers 16 internal registers which
contain Clock, Calibration, Alarm, Watchdog,
Flags, and Square Wave. The Clock registers are
memory locations which contain external (user ac-
cessible) and internal copies of the data (usually
referred to as BiPORT™ TIMEKEEPER cells). The
external copies are independent of internal func-
tions except that they are updated periodically by
the simultaneous transfer of the incremented inter-
nal copy. The internal divider (or clock) chain will
be reset upon the completion of a WRITE to any
clock address (00h to 07h).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a non-clock address.
TIMEKEEPER and Alarm Registers store data in
BCD format. Calibration, Watchdog, and Square
Wave Bits are written in a Binary Format.
M41T62/63/64/65
Table 3. M41T62 Register MapKeys: 0 = Must be set to '0'
AF = Alarm Flag (Read only)
AFE = Alarm Flag Enable Flag
BMB0 - BMB4 = Watchdog Multiplier Bits
CB0-CB1 = Century Bits
OF = Oscillator Fail Bit
OFIE = Oscillator Fail Interrupt Enable Bit
OUT = Output level
RB0 - RB2 = Watchdog Resolution Bits
RPT1-RPT5 = Alarm Repeat Mode Bits
RS0-RS3 = SQW Frequency Bits
S = Sign Bit
SQWE = Square Wave Enable Bit
ST = Stop Bit
WDF = Watchdog Flag Bit (Read only)
15/32
M41T62/63/64/65
Table 4. M41T63 Register MapKeys: 0 = Must be set to '0'
AF = Alarm Flag (Read only)
BMB0 - BMB4 = Watchdog Multiplier Bits
CB0-CB1 = Century Bits
OF = Oscillator Fail Bit
RB0 - RB2 = Watchdog Resolution Bits
RPT1-RPT5 = Alarm Repeat Mode Bits
RS0-RS3 = SQW Frequency Bits
S = Sign Bit
SQWE = Square Wave Enable Bit
ST = Stop Bit
WDF = Watchdog Flag Bit (Read only)
M41T62/63/64/65
Table 5. M41T64 Register MapKeys: 0 = Must be set to '0'
32KE = 32KHz Enable Bit
AF = Alarm Flag (Read only)
BMB0 - BMB4 = Watchdog Multiplier Bits
CB0-CB1 = Century Bits
OF = Oscillator Fail Bit
RB0 - RB2 = Watchdog Resolution Bits
RPT1-RPT5 = Alarm Repeat Mode Bits
RS0-RS3 = SQW Frequency Bits
S = Sign Bit
SQWE = Square Wave Enable Bit
ST = Stop Bit
WDF = Watchdog Flag Bit (Read only)
