M41T315Y ,Serial Access Phantom RTC SupervisorElectrical Characteristics (Externally Supplied) . . 17Figure 13.Power Down/Up Mode AC Waveforms ..
M41T56 ,512 BIT (64B X 8) SERIAL ACCESS TIMEKEEPER SRAMElectrical Characteristics (Table 6.) . . . . 7OPERATION . . . . . . 82-Wire Bus Charac ..
M41T56M ,512 bit 64b x8 Serial Access TIMEKEEPER SRAMElectrical Characteristics . . . 16Figure 17.Power Down/Up Mode AC Waveforms . . . . . . 1 ..
M41T56M6 ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMElectrical Characteristics . . . 16Figure 17.Power Down/Up Mode AC Waveforms . . . . . . 1 ..
M41T56M6E ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMM41T56® 512 bit (64 bit x8) Serial Access TIMEKEEPER SRAM
M41T56M6F ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMFEATURES SUMMARY . . . . . 1Figure 1. 8-pin SOIC Package . . . . . 1Figure 2. 28-pin S ..
M5M5V108DFP-70H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V108DFP-70H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208KV-10LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V208KV-12LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M41T315Y
Serial Access Phantom RTC Supervisor
1/24June 2004
M41T315Y*
M41T315V/WSerial Access Phantom RTC Supervisor
* Contact Local Sales Office
FEATURES SUMMARY 3.0V, 3.3V, OR 5V OPERATING VOLTAGE REAL TIME CLOCK KEEPS TRACK OF
TENTHS/HUNDREDTHS OF SECONDS,
SECONDS, MINUTES, HOURS, DAYS,
DATE OF THE MONTH, MONTHS, AND
YEARS AUTOMATIC LEAP YEAR CORRECTION
VALID UP TO 2100 AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY CHOICE OF POWER-FAIL DESELECT
VOLTAGES:
(VPFD = Power-fail Deselect Voltage) M41T315Y: VCC = 4.5 to 5.5V
4.25V ≤ VPFD ≤ 4.50V M41T315V: VCC = 3.0 to 3.6V
2.80V ≤ VPFD ≤ 2.97V M41T315W: VCC = 2.7 to 3.3V
2.60V ≤ VPFD ≤ 2.70V NO ADDRESS SPACE REQUIRED TO
COMMUNICATE WITH RTC PROVIDES NONVOLATILE SUPERVISOR
FUNCTIONS FOR BATTERY BACKUP OF
SRAM FULL ±10% VCC OPERATING RANGE INDUSTRIAL OPERATING TEMPERATURE
RANGE (–40 to +85°C) ULTRA-LOW BATTERY SUPPLY CURRENT
OF 500nA (max) OPTIONAL PACKAGING INCLUDES A 28-
LEAD SOIC and SNAPHAT® TOP (to be
ordered separately) SNAPHAT PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP,
WHICH CONTAINS THE BATTERY AND
CRYSTAL
M41T315Y*, M41T315V, M41T315W
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 16-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. 16-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 7. M41T315Y/V/W to RAM/Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Non-volatile Supervisor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 8. READ Mode Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 9. WRITE Mode Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 3. AC Electrical Characteristics (M41T315Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 4. AC Electrical Characteristics (M41T315V/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 10.Comparison Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Clock Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
AM-PM/12/24 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Oscillator and Reset Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Zero Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Table 5. RTC Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 11.Reset Pulse Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 7. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 12.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 10. Crystal Electrical Characteristics (Externally Supplied). . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 13.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 11.
Power Down/Up Trip Points DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3/24
M41T315Y*, M41T315V, M41T315WFigure 14.SO16 – 16-lead Plastic Small Outline, Package Outline. . . . . . . . . . . . . . . . . . . . . . . . .18
Table 12. SO16 – 16-lead Plastic Small Outline (150 mils body width), Package Mech. Data. . . .18
Figure 15.SOH28 – 28-lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . .19
Table 13. SOH28 – 28-lead Plastic Small Outline, Package Mechanical Data . . . . . . . . . . . . . . . .19
Figure 16.SH – 4-pin SNAPHAT Housing for 48mAh Battery and Crystal, Package Outline . . . . .20
Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery and Crystal, Package Mech. Data. .20
Figure 17.SH – 4-pin SNAPHAT Housing for 120mAh Battery and Crystal, Package Outline . . . .21
Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery and Crystal, Package Mech. Data.21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
M41T315Y*, M41T315V, M41T315W
SUMMARY DESCRIPTIONThe M41T315Y/V/W RTC Supervisor is a combi-
nation of a CMOS TIMEKEEPER® and a nonvola-
tile memory supervisor. Power is constantly
monitored by the memory supervisor. In the event
of power instability or absence, an external battery
maintains the timekeeping operation and provides
power for a CMOS static RAM by switching on and
invoking write protection to prevent data corrup-
tion in the memory and RTC.
The clock keeps track of tenths/hundredths of sec-
onds, seconds, minutes, hours, day, date, month,
and year information. The last day of the month is
automatically adjusted for months with less than
31 days, including leap year correction.
The clock operates in one of two formats: a 12-hour mode with an AM/PM indicator; a 24-hour mode
The nonvolatile supervisor supplies all the neces-
sary support circuitry to convert a CMOS RAM to
a nonvolatile memory. The M41T315Y/V/W can
be interfaced with RAM without leaving gaps in
memory.
The M41T315Y/V/W is supplied in a 28-lead SOIC
SNAPHAT® package (which integrates both crys-
tal and battery in a single SNAPHAT top) or a-16
pin SOIC. The 28-pin, 330mil SOIC provides sock-
ets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT housing con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery/crystal package to
be mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
The 28-pin SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28-lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is “M4TXX-BR12SH” (see Table
17., page 22).
Caution: Do not place the SNAPHAT battery/crys-tal top in conductive foam, as this will drain the lith-
ium button-cell battery. Note:1. For 16-pin SOIC only
Table 1. Signal Names
5/24
M41T315Y*, M41T315V, M41T315W
M41T315Y*, M41T315V, M41T315W
7/24
M41T315Y*, M41T315V, M41T315W
OPERATIONFigure 6., page 5 illustrates the main elements of
the device. The following paragraphs describe the
signals and functions.
Communication with the clock is established by
pattern recognition of a serial bit stream of 64 bits
which must be matched by executing 64 consecu-
tive WRITE cycles containing the proper data on
data in (D). All accesses which occur prior to rec-
ognition of the 64-bit pattern are directed to mem-
ory via the chip enable output pin (CEO).
After recognition is established, the next 64 READ
or WRITE Cycles either extract or update data in
the clock and CEO remains high during this time,
disabling the connected memory (see Table
2., page7).
Data transfer to and from the timekeeping function
is accomplished with a serial bit stream under con-
trol of chip enable input (CEI), output enable (OE),
and WRITE enable (WE). Initially, a READ cycle
using the CEI and OE control of the clock starts the
pattern recognition sequence by moving the point-
er to the first bit of the 64-bit comparison register.
Next, 64 consecutive WRITE cycles are executed
using the CEI and WE control of the clock. These
64 WRITE cycles are used only to gain access to
the clock.
When the first WRITE cycle is executed, it is com-
pared to the first bit of the 64-bit comparison reg-
ister. If a match is found, the pointer increments to
the next location of the comparison register and
awaits the next WRITE cycle.
If a match is not found, the pointer does not ad-
vance and all subsequent WRITE cycles are ig-
nored. If a READ cycle occurs at any time during
pattern recognition, the present sequence is abort-
ed and the comparison register pointer is reset.
Pattern recognition continues for a total of 64
WRITE cycles as described above until all the bits
in the comparison register have been matched
(see Figure 10., page 11.)
With a correct match for 64 bits, access to the reg-
isters is enabled and data transfer to or from the
timekeeping registers may proceed. The next 64
cycles will cause the device to either receive data
on D, or transmit data on Q, depending on the lev-
el of OE pin or the WE pin. Cycles to other locations
outside the memory block can be interleaved with
CEI cycles without interrupting the pattern recogni-
tion sequence or data transfer sequence to the de-
vice.
For a SO16 pin package, a standard 32.768 kHz
quartz crystal can be directly connected to the
M41T315Y/V/W via pins 1 and 2 (XI, XO). The
crystal selected for use should have a specified
load capacitance (CL) of 12.5 pF (see Table
10., page 17).
Table 2. Operating ModesNote: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Note:1. See Table 11., page 17 for details.
M41T315Y*, M41T315V, M41T315W
Non-volatile Supervisor OperationA switch is provided to direct power from the bat-
tery input or VCCI to VCCO with a maximum voltage
drop of 0.3 Volts. The VCCO output pin is used to
supply uninterrupted power to CMOS SRAM. The
M41T315Y/V/W safeguards the clock and RAM
data by power-fail detection and write protection.
Power-fail detection occurs when VCCI falls below
VPFD which is set by an internal bandgap refer-
ence. The M41T315Y/V/W constantly monitors
the VCCI supply pin. When VCCI is less than VPFD,
power-fail circuitry forces the chip enable output
(CEO) to VCCI or VBAT-0.2 volts for external RAM
write protection. During nominal supply conditions,
CEO will track CEI with a propagation delay. Inter-
nally, the M41T315Y/V/W aborts any data transfer
in progress without changing any of the device
registers and prevents future access until VCCI
exceeds VPFD. Figure 7., page 6 illustrates a typi-
cal RAM/clock interface.
9/24
M41T315Y*, M41T315V, M41T315W
Table 3. AC Electrical Characteristics (M41T315Y)Note:1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V (except where noted). tWR is a function of the latter occurring edge of WE or CEI. tDH and tDS are functions of the first occurring edge of WE or CEI in RAM mode.
M41T315Y*, M41T315V, M41T315W
Table 4. AC Electrical Characteristics (M41T315V/W)Note:1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V (except where noted). tWR is a function of the latter occurring edge of WE or CEI. tDH and tDS are functions of the first occurring edge of WE or CEI in RAM mode.
11/24
M41T315Y*, M41T315V, M41T315W
M41T315Y*, M41T315V, M41T315W
Data RetentionMost low power SRAMs on the market today can
be used with the M41T315Y/V/W. There are, how-
ever some criteria which should be used in making
the final choice of an SRAM to use. The SRAM
must be designed in a way where the chip enable
input disables all other inputs to the SRAM. This
allows inputs to the M41T315Y/V/W and SRAMs
to be Don’t Care once VCCI falls below VPFD(min).
The SRAM should also guarantee data retention
down to VCC=2.0 volts. The chip enable access
time must be sufficient to meet the system needs
with the chip enable output propagation delays
included. If the SRAM includes a second chip
enable pin (E2), this pin should be tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room tem-
perature along with a worst case condition (gener-
ally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
the SRAMs can then be added to the IBAT value of
the M41T315Y/V/W to determine the total current
requirements for data retention. The available bat-
tery capacity for the SNAPHAT® of your choice
can then be divided by this current to determine
the amount of data retention available (see Table
17., page 22).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
