M41T11M6F ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 4. 8-pin SOIC Connections ..
M41T11-MH6 ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMM41T11®512 bit (64 bit x8) Serial Access TIMEKEEPER SRAM
M41T11MH6E ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMElectrical Characteristics . . . 16Figure 17.Power Down/Up Mode AC Waveforms . . . . . . 1 ..
M41T11-MH6E ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMFEATURES SUMMARY . . . . . 1Figure 1. 8-pin SOIC Package . . . . . 1Figure 2. 28-pin S ..
M41T11MH6F ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMLogic Diagram Table 1. Signal NamesOSCI Oscillator InputV VCC BATOCSO Oscillator OutputFrequency Te ..
M41T256YMT7TR ,256 Kbit 32K x8 SERIAL RTCElectrical Characteristics (Externally Supplied) . 20Figure 17.Power Down/Up Mode AC Waveforms ..
M5M5V108CFP-10H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V108CFP-70H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V108CKV-70HI , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V108CVP-10H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V108CVP-70H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V108CVP-70H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M41T11M6-M41T11M6E-M41T11M6F-M41T11-MH6-M41T11MH6E-M41T11-MH6E-M41T11MH6F
512 Bit (64B X8) Serial Access TIMEKEEPER SRAM
1/24December 2004
M41T11512 bit (64 bit x8) Serial Access TIMEKEEPER® SRAM
FEATURES SUMMARY 2.0 TO 5.5V CLOCK OPERATING VOLTAGE COUNTERS FOR SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEARS AND
CENTURY YEAR 2000 COMPLIANT SOFTWARE CLOCK CALIBRATION AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY I2 C BUS COMPATIBLE 56 BYTES of GENERAL PURPOSE RAM ULTRA-LOW BATTERY SUPPLY CURRENT
OF 1µA LOW OPERATING CURRENT OF 300µA BATTERY OR SUPER-CAP BACK-UP BATTERY BACK-UP NOT RECOMMENDED
FOR 3.0V APPLICATIONS (CAPACITOR
BACK-UP ONLY) OPERATING TEMPERATURE OF –40 TO
85°C AUTOMATIC LEAP YEAR COMPENSATION SPECIAL SOFTWARE PROGRAMMABLE
OUTPUT PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT® TOP (to be ordered
separately; 3.3V to 5.0V supply voltage only)
M41T11
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 8-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. 8-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Stop data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 7. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 8. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 9. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 2. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 10.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 11.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 12.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 13.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Table 3. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Clock Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Preferred Initial Power-on Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Figure 14.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 15.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 5. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3/24
M41T11Figure 16.AC Testing Input/Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 6. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 7. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 8. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 17.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 18.SO8 – 8-lead Plastic Small Outline Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 11. SO8 – 8-lead Plastic Small Outline Package Mechanical Data. . . . . . . . . . . . . . . . . . . .18
Figure 19.SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT Package Outline . . . . . . . .19
Table 12. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT Package Mech. Data . . . . .19
Figure 20.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal Package Outline . . . . . . .20
Table 13. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . .20
Figure 21.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . .21
Table 14. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . .21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 16. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 17. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
M41T11
SUMMARY DESCRIPTIONThe M41T11 TIMEKEEPER® RAM is a low power
512-bit, static CMOS RAM organized as 64 words
by 8 bits. A built-in 32.768kHz oscillator (external
crystal controlled) and the first 8 bytes of the RAM
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
Addresses and data are transferred serially via a
two-line bi-directional bus. The built-in address
register is incremented automatically after each
write or read data byte.
The M41T11 clock has a built-in power sense cir-
cuit which detects power failures and automatical-
ly switches to the battery supply during power
failures. The energy needed to sustain the RAM
and clock operations can be supplied from a small
lithium coin cell.
Typical data retention time is in excess of 5 years
with a 50mA/h 3V lithium cell. The M41T11 is sup-
plied in 8 lead Plastic Small Outline package or 28
lead SNAPHAT® package.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion. The SOIC and battery/crys-
tal packages are shipped separately in plastic anti-
static tubes or in Tape & Reel form.
For the 28-lead SOIC, the battery/crystal package
(i.e. SNAPHAT) part number is “M4Txx-BR12SH”
(see Table 16., page 22).
Caution: Do not place the SNAPHAT battery/crys-tal package “M4Txx-BR12SH” in conductive foam
since this will drain the lithium button-cell battery.
Table 1. Signal Names
5/24
M41T11
M41T11
OPERATION
The M41T11 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (D0h). The 64 bytes contained in the device
can then be accessed sequentially in the following
order: Seconds Register Minutes Register Century/Hours Register Day Register Date Register Month Register Years Register Control Register
9 to 64.RAM
The M41T11 clock continually monitors VCC for an
out of tolerance condition. Should VCC fall below
VSO, the device terminates an access in progress
and resets the device address counter. Inputs to
the device will not be recognized at this time to
prevent erroneous data from being written to the
device from an out of tolerance system. When VCC
falls below VSO, the device automatically switches
over to the battery and powers down into an ultra
low current mode of operation to conserve battery
life. Upon power-up, the device switches from bat-
tery to VCC at VSO and recognizes inputs.
2-Wire Bus Characteristics
This bus is intended for communication between
different ICs. It consists of two lines: one bi-direc-
tional for data signals (SDA) and one for clock sig-
nals (SCL). Both the SDA and the SCL lines must
be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the bus
is not busy. During data transfer, the data line must remain
stable whenever the clock line is High. Changes in the data line while the clock line is
High will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the High period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition, a device that gives out a message is
called “transmitter”, the receiving device that gets
the message is called “receiver”. The device that
controls the message is called “master”. The de-
vices that are controlled by the master are called
“slaves”.
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver, whereas
the master generates an extra acknowledge relat-
ed clock pulse.
A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of
each byte. Also, a master receiver must generate
an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case, the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
7/24
M41T11
M41T11
Figure 9. Bus Timing Requirements Sequence
Note: P = STOP and S = START
Table 2. AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted). Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
9/24
M41T11
READ Mode
In this mode, the master reads the M41T11 slave
after setting the slave address (see Figure 10).
Following the write Mode Control Bit (R/W = 0) and
the Acknowledge Bit, the word address An is writ-
ten to the on-chip address pointer. Next the
START condition and slave address are repeated,
followed by the READ Mode Control Bit (R/W =1).
At this point, the master transmitter becomes the
master receiver. The data byte which was ad-
dressed will be transmitted and the master receiv-
er will send an Acknowledge Bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an Acknowledge Bit. The
M41T11 slave transmitter will now place the data
byte at address An + 1 on the bus. The master re-
ceiver reads and acknowledges the new byte and
the address pointer is incremented to An + 2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
An alternate READ mode may also be implement-
ed, whereby the master reads the M41T11 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 12., page 10).
Figure 10. Slave Address Location
Figure 11. READ Mode Sequence
M41T11
Figure 12. Alternate READ Mode Sequence
WRITE Mode
In this mode the master transmitter transmits to
the M41T11 slave receiver. Bus protocol is shown
in Figure 10. Following the START condition and
slave address, a logic '0' (R/W = 0) is placed on the
bus and indicates to the addressed device that
word address An will follow and is to be written to
the on-chip address pointer. The data word to be
written to the memory is strobed in next and the in-
ternal address pointer is incremented to the next
memory location within the RAM on the reception
of an acknowledge clock. The M41T11 slave re-
ceiver will send an acknowledge clock to the mas-
ter transmitter after it has received the slave
address and again after it has received the word
address and each data byte (see Figure
9., page8).
Data Retention Mode
With valid VCC applied, the M41T11 can be ac-
cessed as described above with read or write cy-
cles. Should the supply voltage decay, the
M41T11 will automatically deselect, write protect-
ing itself when VCC falls (see Figure 17).
Figure 13. WRITE Mode Sequence
11/24
M41T11
CLOCK OPERATION
The eight byte clock register (see Table 3) is used
to both set the clock and to read the date and time
from the clock, in a binary coded decimal format.
Seconds, Minutes, and Hours are contained within
the first three registers. Bits D6 and D7 of clock
register 2 (Hours Register) contain the CENTURY
ENABLE Bit (CEB) and the CENTURY Bit (CB).
Setting CEB to a '1' will cause CB to toggle, either
from '0' to '1' or from '1' to '0' at the turn of the cen-
tury (depending upon its initial state). If CEB is set
to a '0', CB will not toggle. Bits D0 through D2 of
register 3 contain the Day (day of week). Registers
4, 5 and 6 contain the Date (day of month), Month
and Years. The final register is the Control Regis-
ter (this is described in the Clock Calibration sec-
tion). Bit D7 of register 0 contains the STOP Bit
(ST). Setting this bit to a '1' will cause the oscillator
to stop. If the device is expected to spend a signif-
icant amount of time on the shelf, the oscillator
may be stopped to reduce current drain. When re-
set to a '0' the oscillator restarts within one second.
Note: In order to guarantee oscillator start-up after
the initial power-up, set the ST Bit to a '1,' then re-
set this bit to a '0.' This sequence enables a “kick
start” circuit which aids the oscillator start-up dur-
ing worst case conditions of voltage and tempera-
ture.
The seven Clock Registers may be read one byte
at a time, or in a sequential block. The Control
Register (Address location 7) may be accessed in-
dependently. Provision has been made to assure
that a clock update does not occur while any of the
seven clock addresses are being read. If a clock
address is being read, an update of the clock reg-
isters will be delayed by 250ms to allow the read
to be completed before the update occurs. This
will prevent a transition of data during the read.
Note: This 250ms delay affects only the clock reg-
ister update and does not alter the actual clock
time.
Table 3. Register Map
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit
ST = STOP Bit
OUT = Output level
X = Don’t care
CEB = Century Enable Bit
CB = Century Bit
Note:1. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' every 100 years (dependent upon the initial value set).
When CEB is set to '0', CB will not toggle.
M41T11
Clock Calibration
The M41T11 is driven by a quartz controlled oscil-
lator with a nominal frequency of 32,768Hz. The
devices are tested not to exceed 35 ppm (parts per
million) oscillator frequency error at 25°C, which
equates to about ±1.53 minutes per month. With
the calibration bits properly set, the accuracy of
each M41T11 improves to better than ±2 ppm at
25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 14., page 13). Most clock
chips compensate for crystal frequency and tem-
perature shift error with cumbersome trim capaci-
tors. The M41T11 design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 15., page 13. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five-bit Calibration byte found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control register (Addr 7). This
byte can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M41T11 may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference (like WWV broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his en-
vironment may require, even after the final product
is packaged in a non-user serviceable enclosure.
All the designer has to do is provide a simple utility
that accessed the Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) Bit, the seventh-most significant bit in the
Control Register, is set to a '1', and the oscillator is
running at 32,768Hz, the FT/OUT pin of the device
will toggle at 512Hz. Any deviation from 512Hz in-
dicates the degree and direction of oscillator fre-
quency shift at the test temperature.
For example, a reading of 512.01024Hz would in-
dicate a +20 ppm oscillator frequency error, requir-
ing a –10(XX001010) to be loaded into the
Calibration Byte for correction. Note that setting or
changing the Calibration Byte does not affect the
Frequency test output frequency.
Output Driver Pin
When the FT Bit is not set, the FT/OUT pin be-
comes an output driver that reflects the contents of
D7 of the control register. In other words, when D6
of location 7 is a zero and D7 of location 7 is a zero
and then the FT/OUT pin will be driven low.
Note: The FT/OUT pin is open drain which re-
quires an external pull-up resistor.
Preferred Initial Power-on Defaults
Upon initial application of power to the device, the
FT Bit will be set to a '0' and the OUT Bit will be set
to a '1'. All other Register bits will initially power-on
in a random state.
