M41T11 Fast Delivery |IC PHOENIX CO.,LIMITED

M41T11 ,512 BIT (64B X 8) SERIAL ACCESS TIMEKEEPER SRAMElectrical Characteristics (Table 6.) . . . . 8OPERATION . . . . . . 92-Wire Bus Charac ..
M41T11M6 ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMFEATURES SUMMARY■ 2.0 TO 5.5V CLOCK OPERATING VOLTAGE Figure 1. 8-pin SOIC Package■ COUNTERS FOR SE ..
M41T11M6E ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMAPPLICATIONS (CAPACITOR BACK-UP ONLY)■ OPERATING TEMPERATURE OF –40 TO 85°C■ AUTOMATIC LEAP YEAR CO ..
M41T11M6F ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 4. 8-pin SOIC Connections ..
M41T11-MH6 ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMM41T11®512 bit (64 bit x8) Serial Access TIMEKEEPER SRAM
M41T11MH6E ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMElectrical Characteristics . . . 16Figure 17.Power Down/Up Mode AC Waveforms . . . . . . 1 ..
M5M5V108CFP-10H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V108CFP-70H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V108CKV-70HI , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V108CVP-10H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V108CVP-70H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V108CVP-70H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

M41T11
512 BIT (64B X 8) SERIAL ACCESS TIMEKEEPER SRAM
1/24November 2002
M41T11
512 bit (64 bit x 8) SERIAL ACCESS TIMEKEEPER® SRAM
FEATURES SUMMARY 2.0 TO 5.5V CLOCK OPERATING VOLTAGE COUNTERS FOR SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEARS and
CENTURY YEAR 2000 COMPLIANT SOFTWARE CLOCK CALIBRATION AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRYI2 C BUS COMPATIBLE 56 BYTES of GENERAL PURPOSE RAM ULTRA-LOW BATTERY SUPPLY CURRENT
OF 1μA LOW OPERATING CURRENT OF 300μA BATTERY OR SUPER-CAP BACK-UP BATTERY BACK-UP NOT RECOMMENDED
FOR 3.0V APPLICATIONS (CAPACITOR
BACK-UP ONLY) OPERATING TEMPERATURE OF –40 TO
85°C AUTOMATIC LEAP YEAR COMPENSATION SPECIAL SOFTWARE PROGRAMMABLE
OUTPUT PACKAGING INCLUDES a 28-LEAD SOIC and
SNAPHAT® TOP (to be ordered separately;
3.3V to 5.0V supply voltage only)
Figure 1. 8-pin SOIC Package
Figure 2. 28-pin SOIC Package
M41T11
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Logic Diagram (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
8-pin SOIC Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
28-pin SOIC Connections (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Block Diagram (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
AC Testing Input/Output Waveform (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Crystal Electrical Characteristics (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Serial Bus Data Transfer Sequence (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Acknowledgement Sequence (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Bus Timing Requirements Sequence (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Slave Address Location (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
READ Mode Sequence (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Alternate READ Mode Sequence (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
WRITE Mode Sequence (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Power Down/Up Mode AC Waveforms (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Power Down/Up AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Power Down/Up Trip Points DC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3/24
M41T11
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Register Map (Table 10.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Preferred Initial Power-on Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Crystal Accuracy Across Temperature (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Clock Calibration (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
SNAPHAT Battery Table (Table 12.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
M41T11
SUMMARY DESCRIPTION
The M41T11 TIMEKEEPER® RAM is a low power
512-bit, static CMOS RAM organized as 64 words
by 8 bits. A built-in 32.768 kHz oscillator (external
crystal controlled) and the first 8 bytes of the RAM
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
Addresses and data are transferred serially via a
two-line bi-directional bus. The built-in address
register is incremented automatically after each
write or read data byte.
The M41T11 clock has a built-in power sense cir-
cuit which detects power failures and automatical-
ly switches to the battery supply during power
failures. The energy needed to sustain the RAM
and clock operations can be supplied from a small
lithium coin cell.
Typical data retention time is in excess of 5 years
with a 50mA/h 3V lithium cell. The M41T11 is sup-
plied in 8 lead Plastic Small Outline package or 28
lead SNAPHAT® package.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion. The SOIC and battery/crys-
tal packages are shipped separately in plastic anti-
static tubes or in Tape & Reel form.
For the 28-lead SOIC, the battery/crystal package
(i.e. SNAPHAT) part number is “M4Txx-BR12SH”
(see Table 12, page 18).
Caution: Do not place the SNAPHAT battery/crys-
tal package “M4Txx-BR12SH” in conductive foam
since this will drain the lithium button-cell battery.
Figure 3. Logic Diagram Table 1. Signal Names
5/24
M41T11
Figure 4. 8-pin SOIC Connections Figure 5. 28-pin SOIC Connections
Figure 6. Block Diagram
M41T11
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Note:1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 and 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
7/24
M41T11
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Note: Output Hi-Z is defined as the point where data is no longer driven. Supply Voltage for SOH28 is 3.3V to 5.5V.
Figure 7. AC Testing Input/Output Waveform
Table 4. Capacitance
Note:1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. At 25°C, f = 1MHz. Outputs deselected.
M41T11
Table 5. DC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted). STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply. After switchover (VSO), VBAT(min) can be 2.0V for crystal with RS = 40KΩ. For rechargeable back-up, VBAT(max) may be considered VCC.
Table 6. Crystal Electrical Characteristics
Note:1. These values are externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/
1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature
operations. KDS can be contacted at [email protected] or http://www.kdsj.co.jp for further information on this crystal type. Load capacitors are integrated within the M41T00. Circuit board layout considerations for the 32.768kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account. All SNAPHAT® battery/crystal tops meet these specifications.
9/24
M41T11
OPERATION
The M41T11 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (D0h). The 64 bytes contained in the device
can then be accessed sequentially in the following
order: Seconds Register Minutes Register Century/Hours Register Day Register Date Register Month Register Years Register Control Register
9 to 64. RAM
The M41T11 clock continually monitors VCC for an
out of tolerance condition. Should VCC fall below
VSO, the device terminates an access in progress
and resets the device address counter. Inputs to
the device will not be recognized at this time to
prevent erroneous data from being written to the
device from an out of tolerance system. When VCC
falls below VSO, the device automatically switches
over to the battery and powers down into an ultra
low current mode of operation to conserve battery
life. Upon power-up, the device switches from bat-
tery to VCC at VSO and recognizes inputs.
2-Wire Bus Characteristics
This bus is intended for communication between
different ICs. It consists of two lines: one bi-direc-
tional for data signals (SDA) and one for clock sig-
nals (SCL). Both the SDA and the SCL lines must
be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the bus
is not busy. During data transfer, the data line must remain
stable whenever the clock line is High. Changes in the data line while the clock line is
High will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the High period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition, a device that gives out a message is
called “transmitter”, the receiving device that gets
the message is called “receiver”. The device that
controls the message is called “master”. The de-
vices that are controlled by the master are called
“slaves”.
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver, whereas
the master generates an extra acknowledge relat-
ed clock pulse.
A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of
each byte. Also, a master receiver must generate
an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case, the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
M41T11
Figure 8. Serial Bus Data Transfer Sequence
Figure 9. Acknowledgement Sequence
Figure 10. Bus Timing Requirements Sequence
Note: P = STOP and S = START
11/24
M41T11
Table 7. AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted). Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
M41T11
READ Mode
In this mode, the master reads the M41T11 slave
after setting the slave address (see Figure 11).
Following the write Mode Control Bit (R/W = 0) and
the Acknowledge Bit, the word address An is writ-
ten to the on-chip address pointer. Next the
START condition and slave address are repeated,
followed by the READ Mode Control Bit (R/W =1).
At this point, the master transmitter becomes the
master receiver. The data byte which was ad-
dressed will be transmitted and the master receiv-
er will send an Acknowledge Bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an Acknowledge Bit. The
M41T11 slave transmitter will now place the data
byte at address An + 1 on the bus. The master re-
ceiver reads and acknowledges the new byte and
the address pointer is incremented to An + 2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
An alternate READ mode may also be implement-
ed, whereby the master reads the M41T11 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 13, page 13).
WRITE Mode
In this mode the master transmitter transmits to
the M41T11 slave receiver. Bus protocol is shown
in Figure 11. Following the START condition and
slave address, a logic '0' (R/W = 0) is placed on the
bus and indicates to the addressed device that
word address An will follow and is to be written to
the on-chip address pointer. The data word to be
written to the memory is strobed in next and the in-
ternal address pointer is incremented to the next
memory location within the RAM on the reception
of an acknowledge clock. The M41T11 slave re-
ceiver will send an acknowledge clock to the mas-
ter transmitter after it has received the slave
address and again after it has received the word
address and each data byte (see Figure 10, page
10).
Figure 11. Slave Address Location

Partno	Mfg	Dc	Qty	Available	Descript
M41T11	ST	N/a	200	avai	512 BIT (64B X 8) SERIAL ACCESS TIMEKEEPER SRAM