M41T00AUD ,Serial real-time clock (RTC) with audioelectrical characteristics, valid for V = 3.3 V and CCT = 25 °C (except where otherwise noted) ..
M41T00AUDD1F ,Serial real-time clock (RTC) with audioFeaturesCombination real-time clock with audio■ Serial real-time clock (RTC) based on M41T00■ Audio ..
M41T00M6 ,Serial Access TIMEKEEPERBlock Diagram . . 5OPERATION . . . . . . 62-Wire Bus Characteristics . . . . . ..
M41T00M6E ,Serial Access TIMEKEEPERElectrical Characteristics . . . 16Figure 15.Power Down/Up Mode AC Waveforms . . . . . . 1 ..
M41T00M6F ,Serial Access TIMEKEEPERLogic Diagram Table 1. Signal NamesOSCI Oscillator InputV VCC BATOCSO Oscillator OutputFrequency Te ..
M41T00M6TR ,Serial Access TIMEKEEPERFEATURES SUMMARY■ 2.0 TO 5.5V CLOCK OPERATING VOLTAGE Figure 1. Package■ COUNTERS FOR SECONDS, MINU ..
M5M54R08AJ-10 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08AJ-10 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08J-12 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08J-15 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R16AJ-10 , 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
M5M54R16AJ-12 , 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
M41T00AUD-M41T00AUDD1F
Serial real-time clock (RTC) with audio
February 2012 Doc ID 13480 Rev 5 1/42
M41T00AUDSerial real-time clock (RTC) with audio
Features
Combination real-time clock with audio Serial real-time clock (RTC) based on M41T00 Audio section provides: 300 mW differential audio amplifier 256 and 512 Hz tone generation –33 to +12 dB gain, 3 dB steps (16 steps
plus MUTE) 0 °C to 70 °C operation Small DFN16 package (5 mm x 4 mm)
Real-time clock details Superset of M41T00 3.0 to 3.6 V operation Timekeeping down to 1.7 V Automatic backup switchover circuit Ultra-low 400 nA backup current at 3.0 V
(typ) Suitable for battery or capacitor backup On-chip trickle charge circuit for backup
capacitor 400 kHz I2 C bus M41T00 compatible register set with counters
for seconds, minutes, hours, day, date, month,
years, and century Automatic leap year compensation HT bit set when clock goes into backup
mode RTC operates using 32,768 Hz quartz crystal Calibration register provides for
adjustments of –63 to +126 ppm Oscillator supports crystals with up to 40
kΩ series resistance, 12.5 pF load
capacitance Oscillator fail detect circuit OF bit indicates
when oscillator has stopped for four or more
cycles
Audio section Power amplifier Differential output amplifier Provides 300 mW into 8 Ω
(THD+N = 2% (max), fin = 1 kHz) Summing node at audio input Inverting configuration with summing
resistors into the minus (-) terminal 0 dB gain with 10 kΩ feedback resistor and
20 kΩ input summing resistors Signal input centered at VDD/2 1.6 VP-P analog input range (max) 256 or 512 Hz signal multiplexing with analog
input to provide audio with beep tones Volume control, 4-bit register Allows gain adjustment from –33 dB to
+12 dB 3 dB steps
–MUTE bit Audio automatically shuts off in backup mode
Contents M41T00AUD2/42 Doc ID 13480 Rev 5
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
M41T00AUD clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.1 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 Halt bit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.2 Oscillator fail detect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.3 Trickle charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Reading and writing the clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Priority for IRQ/FT/OUT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4 Switchover thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.5 T rickle charge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246.1 Digital calibration (periodic counter correction) . . . . . . . . . . . . . . . . . . . . 24
Audio section operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287.1 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1.1 Gain tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2 Wake-up time: T WU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
M41T00AUD ContentsDoc ID 13480 Rev 5 3/42
Initial conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
List of tables M41T00AUD
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List of tables
Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. List of registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. M41T00AUD register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Priority for IRQ/FT/OUT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7. MUTE and GAIN values (VCC = 3.3 V and ambient temperature = 25 °C). . . . . . . . . . . . . 29
Table 8. Initial values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11. Input/output characteristics (25 °C, f = 1 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 12. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14. RTC power down/up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. RTC power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 16. Audio section electrical characteristics, valid for VCC = 3.3 V and
TAMB = 25 °C (except where otherwise noted). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17. DFN16 (5 mm x 4 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 18. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
M41T00AUD List of figures
Doc ID 13480 Rev 5 5/42
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Typical hookup example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Alternate READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Counter update diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Switchover thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. Trickle charge circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 15. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. Audio section diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. AC testing input/output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 18. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. DFN16 (5 mm x 4 mm) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. DFN16 (5 mm x 4 mm) footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Description M41T00AUD
6/42 Doc ID 13480 Rev 5
1 Description
The M41T00AUD is a low-power serial real-time clock (RTC) with an integral audio section
with tone generator and 300 mW output amplifier. The RTC is a superset of the M41T00
with enhancements such as a precision reference for switchover, an oscillator fail detect
circuit, and storing of the time at power-down. The audio section includes a summing
amplifier (inverting) at the input. An 8 kHz low-pass filter follows that with a 16-step
programmable gain stage next. A 256 or 512 Hz audio tone can be switched into the filter in
place of the input signal. From the gain stage, the 300 mW amplifier drives the output pins.
The M41T00AUD has a built-in power sense circuit which detects power failures and
automatically switches to the backup input when VCC is removed. Backup power can be
supplied by a capacitor or by a battery such as a lithium coin cell. The device includes a
trickle charge circuit for charging the capacitor.
The RTC includes a built-in 32.768 kHz oscillator controlled by an external crystal. Eight
register bytes are used for the clock/calendar functions and are superset compatible with the
M41T00. Two additional registers control the audio section and the trickle charger. The 10
registers (see Table 2) are accessed over a 400 kHz I2 C bus. The address register
increments automatically after each byte READ or WRITE operation thus streamlining
transfers by eliminating the need to send a new address for each byte to be transferred. ypical data retention times will be in excess of 5 years with a 50 mAh 3 V lithium cell (see
RTC DC characteristics, Table 12 for more information).
Figure 1. Logic diagram
M41T00AUD Pin settings
Doc ID 13480 Rev 5 7/42
2 Pin settings
2.1 Pin connection
Figure 2. Pin connection
2.2 Pin description
Table 1. Pin description
Application M41T00AUD
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3 Application
Figure 3. Application diagram
M41T00AUD Application
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Figure 4. Typical hookup example
Operation M41T00AUD
10/42 Doc ID 13480 Rev 5
4 Operation
The M41T00AUD clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 10 bytes
contained in the device can then be accessed sequentially in the following order:
The M41T00AUD continually monitors VCC for an out of tolerance condition. Should VCC fall
below VPFD, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from an out of tolerance system. When VCC falls below VSO,
the device automatically switches over to the backup battery or capacitor and powers down
into an ultra low current mode of operation to conserve battery life. Upon power-up, the
device switches from battery to VCC at VSO and recognizes inputs.
Table 2. List of registers
M41T00AUD Operation
Doc ID 13480 Rev 5 11/42
4.1 2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line while the clock line is high will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined: Bus not busy. Both data and clock lines remain high. Start data transfer. A change in the state of the data line, from high to low, while the
clock is high, defines the START condition. Stop data transfer. A change in the state of the data line, from low to high, while the
clock is high, defines the STOP condition. Data valid. The state of the data line represents valid data when after a start condition,
the data line is stable for the duration of the high period of the clock signal. The data on
the line may be changed during the low period of the clock signal. There is one clock
pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is called "transmitter", the receiving device
that gets the message is called "receiver". The device that controls the message is called
"master". The devices that are controlled by the master are called "slaves". Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This
acknowledge bit is a low level put on the bus by the receiver, whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case, the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Operation M41T00AUD
12/42 Doc ID 13480 Rev 5
Figure 5. Serial bus data transfer sequence
Figure 6. Acknowledgement sequence
Figure 7. Bus timing requirements sequence
Note: P = STOP and S = START
M41T00AUD Operation
Doc ID 13480 Rev 5 13/42
4.2 Characteristics
4.3 READ mode
In this mode, the master reads the M41T00AUD slave after setting the slave address (see
Figure 8). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the
word (register) address An is written to the on-chip address pointer. Next the START
condition and slave address are repeated, followed by the READ mode control bit (R/W = 1).
At this point, the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an acknowledge bit to the
slave transmitter. The address pointer is only incremented on reception of an acknowledge
bit. The device slave transmitter will now place the data byte at address An+1 on the bus.
The master receiver reads and acknowledges the new byte and the address pointer is
incremented to An+2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
An alternate READ mode may also be implemented, whereby the master reads the
M41T00AUD slave without first writing to the (volatile) address pointer. The first address
that is read is the last one stored in the pointer (see Figure 10).
Table 3. AC characteristics Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted). Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL.
Operation M41T00AUD
14/42 Doc ID 13480 Rev 5
Figure 8. Slave address location
Figure 9. READ mode sequence
Figure 10. Alternate READ mode sequence
M41T00AUD Operation
Doc ID 13480 Rev 5 15/42
4.4 WRITE mode
In this mode the master transmitter transmits to the M41T00AUD slave receiver. Bus
protocol is shown in Figure 11. Following the ST ART condition and slave address, a logic '0'
(R/W = 0) is placed on the bus and indicates to the addressed device that word address An
will follow and is to be written to the on-chip address pointer. The data word to be written to
the device is strobed in next and the internal address pointer is incremented to the next
location within the device on the reception of an acknowledge clock. The M41T00AUD slave
receiver will send an acknowledge clock to the master transmitter after it has received the
slave address and again after it has received the word address and each data byte (see
Figure8).
Figure 11. WRITE mode sequence
4.5 Data retention mode
With valid VCC applied, the M41T00AUD can be accessed as described above with READ
or WRITE cycles. Should the supply voltage decay, the M41T00AUD will automatically
deselect, write protecting itself when VCC falls (see Figure 13).
M41T00AUD clock operation M41T00AUD
16/42 Doc ID 13480 Rev 5 M41T00AUD clock operation
5.1 Clock registers
The 10-byte register map (see Table 2) is used to both set the clock and to read the date
and time from the clock, in a binary coded decimal format.
Seconds, minutes, and hours are contained within the first three registers. Bits D6 to D0 or
register 00h (seconds register) contain the seconds count in BCD format with values in the
range 0 to 59. Bit D7 is the ST or stop bit, described below, and is not affected by the
timekeeping operation, but users must avoid inadvertently altering it when writing the
seconds register.
Setting the ST bit to a 1 will cause the oscillator to stop. If the device is expected to spend a
significant amount of time on the shelf, the oscillator may be stopped to reduce current drain
on the backup battery. When reset to a 0 the oscillator restarts within one second.
In order to ensure oscillator start-up after the initial power-up, set the ST bit to a 1 then write
it to 0. This sequence enables the "kick start" circuit which aids the oscillator start-up by
temporarily increasing the oscillator current. This will guarantee oscillator start-up under
worst case conditions of voltage and temperature. This feature can be employed anytime
the oscillator is being started but should not occur on subsequent power-ups when the
oscillator is already running.
Bits D6 to D0 of register 01h (minutes register) contain the minutes count in BCD format
with values in the range 0 to 59. Bit D7 always reads 0. Writing it has no effect.
Bits D5 to D0 of register 02h (century/ hours register) contain the hours in BCD format with
values in the range 0 to 23. Bits D7 and D6 contain the century enable bit (CEB) and the
century bit (CB). CB provides a one-bit indicator for the century. The user can apply his
preferred convention for defining the meaning of this bit. For example, 0 can mean the
current century, and 1 the next, or the opposite meanings may be used.
When enabled, CB will toggle every 100 years. Setting CEB to a 1 enables CB to toggle at
the turn of the century, either from 0 to 1 or from 1 to 0, depending on its initial state, as
programmed by the user. When CEB is a 0, CB will not toggle.
Bits D2 through D0 of register 03h (day register) contain the day of the week in BCD format
with values in the range 0 to 7. Bits D3 and D7 will always read 0. Writes to them have no
effect. Bits D6, D5 and D4 will power up in an indeterminate state.
Register 04h contains the date (day of month) in BCD format with values in the range 01 to
31. Bits D7 and D6 always read 0. Writes to them have no effect.
Register 05 h is the Month in BCD format with values in the range 1 to 12. Bits D7, D6 and
D5 always read 0. Writes to them have no effect.
Register 06h is the years in BCD format with values in the range 0 to 99. Writing to any of
the registers 00h to 06h, including the control bits therein, will result in updates to the
counters and resetting of the internal clock divider chain including the 256/512 Hz tone
generator. The updates do not occur immediately after the write(s), but occur upon
completion of the current write access. This is described in greater detail in the next section.
Registers 07h and 09h also contain clock control and status information. These registers
can be written at any time without affecting the timekeeping function.
M41T00AUD M41T00AUD clock operation
Doc ID 13480 Rev 5 17/42
Register 08 is the calibration register. Calibration is described in detail in the clock
calibration section. Bit D7 is the OUT bit and controls the discrete output pin IRQ/FT/OUT as
described in Table5.
5.1.1 Halt bit operation
Bit D7 of register 09 h is the HT or halt bit. Whenever the device switches to backup power,
it sets the HT bit to 1 and stores the time of power-down in the transfer buffer registers. This
is known as power-down time stamp. During normal timekeeping, once per second, the
transfer buffer registers are updated with the current time. When HT is 1, that updating is
halted. The clock continues to keep time but the periodic updates do not occur.
Upon power-up, reads of the clock registers will return the time of power-down (assuming
adequate backup power was maintained while VCC was off). After the user clears the HT bit
by writing it to 0, subsequent reads of the clock registers will return the current time.
At power-up, the user can read the time of power-down, and then clear the HT bit to allow
updates. The next read will return the current time. Knowing both the power-up time and the
power-down time allows the user to calculate the duration of power-off.
In addition to the HT bit getting set to 1 automatically at power-down, the user can also write
it to 1 to halt updating of the registers.
5.1.2 Oscillator fail detect operation
Bits D5 and D4 of register 09 h contain the oscillator fail flag (OF) and the oscillator fail
interrupt enable bit (OFIE). If the 32 KHz oscillator drops four or more pulses in a row, as
might occur during an extended outage while backed up on a capacitor, the OF bit will be set
to 1. This provides an indication to the user of the integrity of the timekeeping operation.
Whenever the OF bit is a 1, the system should consider the time to be possibly corrupted
due to operating at too low a voltage. The OF bit will always be 1 at the initial power-up of
the device. The OF bit is cleared by writing it to 0. At the initial power-up, users should wait
three seconds for the oscillator to stabilize before clearing the OF bit.
OFIE can be used to enable the device to assert its interrupt output whenever an oscillator
failure is detected. The oscillator fail interrupt will drive the IRQ/FT/OUT pin as described in able 5. The interrupt is cleared by writing the OF bit to 0. Setting OFIE enables the
oscillator fail interrupt. Clearing it to 0 disables it, but the OF will continue to function
regardless of OFIE.
5.1.3 Trickle charger
Bits D6 and D3 to D0, of register 09h, control the trickle charge function. It is described in
detail in the trickle charge circuit section.
M41T00AUD clock operation M41T00AUD
18/42 Doc ID 13480 Rev 5
5.2 Reading and writing the clock registers
The counters used to implement the timing chain in the real-time clock are not directly
accessed by the serial interface. Instead, as depicted in Figure 12, reads and writes are
buffered through a set of transfer registers. This ensures coherency of the timekeeping
function.
During writes of the timekeeping registers (00h to 06h), the write data is stored in the buffer
transfer registers until all the data is written, then the register contents are simultaneously
transferred to the counters thus updating them. The update is triggered either by a STOP
condition or by a write to one of the non RTC registers, 07h to 09h. If any of the buffer
transfer registers are not written, then the corresponding counters are not updated. Instead,
those counters will retain their previous contents when the update occurs.
Similar to the writes, reads access the buffer transfer registers. The device periodically
updates the registers with the counter contents. But during reads, the updates are
suspended. Timekeeping continues, but the registers are frozen until after a STOP
condition or a non RTC register (07h to 09h) is read. Suspending the updates ensures that
a clock roll-over does not occur during a user read cycle.
The seven clock registers may be read one byte at a time, or in a sequential block. The
calibration, audio and Control2 registers, location 07 h to 09 h, may be accessed
independently.
Provision has been made to ensure that a clock update does not occur while any of the
seven clock addresses are being read. During a clock register read (addresses 00h to 06h),
updates of the clock transfer buffer registers are halted. The clock counters continue to keep
time, but the contents of the transfer buffer registers is frozen at the time that the read
access began.
This prevents a transition of data during the READ. For example, without the halt function, if
the time incremented past midnight in the middle of an access sequence, the user might
begin reading at 11:59:59pm and finish at 12:00:00am. The data read might appear as
12:59:59 because the seconds and minutes were read before midnight while the hours were
read after. The device prevents this by halting the updates of the registers until after the read
access has occurred.
M41T00AUD M41T00AUD clock operation
Doc ID 13480 Rev 5 19/42
Table 4. M41T00AUD register map(1) Key:
S = SIGN bit
FT = Frequency test bit
ST = STOP bit
OF = Oscillator fail detect flag
OFIE = Oscillator fail interrupt enable
OUT = Logic output
TCHE3:TCHEO = Trickle charge enable bits
TCFE = Trickle charge FET bypass enable
HT = Halt bit
TCH2 = Trickle charge enable #2
TONE = Tone on/off select
CB = Century bit
CEB = Century enable bit
256/512 = Tone frequency select bit 0 bits always read as 0. Writing them has no effect. Y bits are indeterminate at power-up. These are the factory test mode bits, and must be written to 0.
M41T00AUD clock operation M41T00AUD
20/42 Doc ID 13480 Rev 5
Figure 12. Counter update diagram
M41T00AUD M41T00AUD clock operation
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5.3 Priority for IRQ/FT/OUT pin
Three functions share pin 5 of the M41T00AUD. The oscillator fail interrupt (IRQ), the
calibration frequency test output (FT) and the discrete logic output (OUT) all use this pin.
In normal operation, when operating from VCC, the interrupt function has priority over the
frequency test function which in turn has priority over the discrete output function.
In the backup mode, when operating from VBACK, the priorities are different. The interrupt
and frequency test functions are disabled, and only the discrete output function can be
used.
When operating from VCC, if the oscillator fail interrupt enable bit is set (OFIE, D4 of register
09h), the pin is an interrupt output which will be asserted anytime the OF bit (D5 of register
09h) goes true. (See Section 5 for more details.)
During calibration, the pin can be used as a frequency test output. When FT is a 1 (and
OFIE a 0), the device will output a 512 Hz test signal on this pin. Users can measure this
with a frequency counter and use that result to determine the appropriate calibration register
value.
Otherwise, when OFIE is a 0 and FT is a 0, it becomes the discrete logic OUT pin and
reflects the value of the OUT bit (D7 of register 07h).
When operating from VBACK, the discrete output function can still be used. The
IRQ/FT/OUT pin will reflect the contents of the out bit.
Note: The IRQ/FT/OUT pin is open drain and requires an external pull-up resistor.
Table 5. Priority for IRQ/FT/OUT pin
