M41ST87YMX6 ,5.0, 3.3, OR 3.0V, 1280 Bit (160 X8) Secure Serial RTC and NVRAM Supervisor with Tamper DetectionAbsolute Maximum Ratings . . . . . . . 33DC and AC PARAMETERS . 34Table 14. DC and AC Me ..
M41ST95WMX6 ,5.0 or 3.0V, 512 Bit (64 Bit x8) Serial RTC (SPI) SRAM and NVRAM SupervisorAbsolute Maximum Ratings . . . . . . . 25DC AND AC PARAMETERS . 26Table 11. DC and AC Mea ..
M41T0 ,SERIAL REAL-TIME CLOCKElectrical Characteristics (Table 6.) . . . . 7OPERATION . . . . . . 82-Wire Bus Charac ..
M41T00 ,SERIAL ACCESS TIMEKEEPERFEATURES SUMMARY
M41ST87WMX6-M41ST87WMX6TR-M41ST87YMX6
5.0, 3.3, OR 3.0V, 1280 Bit (160 X8) Secure Serial RTC and NVRAM Supervisor with Tamper Detection
1/40September 2004
M41ST87Y
M41ST87W5.0, 3.3, or 3.0V, 1280 bit (160 x8) Secure Serial RTC
and NVRAM Supervisor with Tamper Detection
FEATURES SUMMARY 5.0, 3.3, OR 3.0V OPERATING VOLTAGE SERIAL INTERFACE SUPPORTS I2 C BUS
(400kHz) NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM 2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY CHOICE OF POWER-FAIL DESELECT
VOLTAGES M41ST87Y:
VCC = 4.75 to 5.5V;
THS Bit = '1': 4.50V ≤ VPFD ≤ 4.75V
VCC = 4.5 to 5.5V;
THS Bit = '0': 4.20V ≤ VPFD ≤ 4.50V M41ST87W:
VCC = 3.0 to 3.6V;
THS Bit = '1': 2.8V ≤ VPFD ≤ 3.0V
VCC = 2.7 to 3.6V;
THS Bit = '0': 2.55V ≤ VPFD ≤ 2.70V TWO INDEPENDENT POWER-FAIL
COMPARATORS (1.25V REFERENCE) COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY 128 BYTES OF GENERAL PURPOSE RAM PROGRAMMABLE ALARM AND
INTERRUPT FUNCTION (VALID EVEN
DURING BATTERY BACK-UP MODE) PROGRAMMABLE WATCHDOG TIMER UNIQUE ELECTRONIC SERIAL NUMBER
(8-BYTE) 32kHz FREQUENCY OUTPUT AVAILABLE
UPON POWER-ON MICROPROCESSOR POWER-ON RESET BATTERY LOW FLAG ULTRA-LOW BATTERY SUPPLY CURRENT
OF 500nA (TYP)
M41ST87Y, M41ST87W
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SECURITY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 3. 28-pin, 300mil SOIC (MX) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 5. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Stop data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Data Valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 6. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 7. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 8. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 2. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Figure 9. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 10.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 11.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Figure 12.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 13.WRITE Cycle Timing: RTC & External SRAM Control Signals . . . . . . . . . . . . . . . . . . . .13
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Tamper Detection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Tamper Register Bits (Tamper 1 and Tamper 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Tamper Enable Bits (TEB1 and TEB2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Tamper Bits (TB1 and TB2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Tamper Interrupt Enable Bits (TIE1 and TIE2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Tamper Connect Mode Bit (TCM1 and TCM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Tamper Polarity Mode Bits (TPM1 and TPM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 14.Tamper Detect Connection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 3. Tamper Detection Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 15.Tamper Detect Output Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 16.Basic Tamper Detect Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Tamper Detect Sampling (TDS1 and TDS2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3/40
M41ST87Y, M41ST87WTamper Current Hi/Tamper Current Lo (TCHI/TCLO1 and TCHI/TCLO2) . . . . . . . . . . . . . . . . . . .17
RAM Clear (CLR1 and CLR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
RAM Clear External (CLR1EXT and CLR2EXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 4. Tamper Detection Current (Normally Closed - TCMX = '0') . . . . . . . . . . . . . . . . . . . . . . .17
Figure 17.Tamper Detect Sampling Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 18.Tamper Current Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 19.Tamper Output Timing (with CLR1EXT or CLR2EXT = '1') . . . . . . . . . . . . . . . . . . . . . . . .19
Table 5. Tamper Detect Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 20.RAM Clear Hardware Hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Tamper Detection Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Internal Tamper Pull-up/down Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Tamper Event Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Power-Down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 6. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Figure 21.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 22.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Figure 23.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 7. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 24.Back-Up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Table 8. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Full-time 32kHz Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Figure 25.RSTIN1 & RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 9. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Power-fail Comparators (1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Power-fail Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Century Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
trec Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Electronic Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Oscillator Stop Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Table 10. Century Bits Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 11. trec Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 12. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
M41ST87Y, M41ST87W
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Table 13. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Table 14. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 26.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 15. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 16. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 27.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 17. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37Figure 28.SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal Outline. . . . . . . . .37
Table 18. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Mechanical Data 37
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
5/40
M41ST87Y, M41ST87W
SUMMARY DESCRIPTIONThe M41ST87Y/W Serial TIMEKEEPER® /Con-
troller SRAM is a low power 1280-bit, static CMOS
SRAM organized as 160 bytes by 8 bits. A built-in
32.768 kHz oscillator (internal crystal-controlled)
and 8 bytes of the SRAM (see Table 6., page 23)
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
An additional 11 bytes of RAM provide calibration,
status/control of Alarm, Watchdog, Tamper, and
Square Wave functions. 8 bytes of ROM and final-
ly 128 bytes of User RAM are also provided. Ad-
dresses and data are transferred serially via a two
line, bi-directional I2 C interface. The built-in ad-
dress register is incremented automatically after
each WRITE or READ data byte. The M41ST87Y/
W has a built-in power sense circuit which detects
power failures and automatically switches to the
battery supply when a power failure occurs. The
energy needed to sustain the SRAM and clock op-
erations can be supplied by a small lithium button-
cell supply when a power failure occurs.
Functions available to the user include a non-vol-
atile, time-of-day clock/calendar, Alarm interrupts,
Tamper Detection, Watchdog Timer, and pro-
grammable Square Wave output. Other features
include a Power-On Reset as well as two addition-
al debounced inputs (RSTIN1 and RSTIN2) which
can also generate an output Reset (RST). The
eight clock address locations contain the century,
year, month, date, day, hour, minute, second and
tenths/hundredths of a second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year), 30 and 31
day months are made automatically.
Security FeaturesTwo fully independent Tamper Detection Inputs al-
low monitoring of multiple locations within the sys-
tem. Programmable bits provide both, “Normally
Open” and “Normally Closed” switch monitoring.
Time Stamping of the tamper event is automatical-
ly provided. There is also an option allowing data
stored in either internal memory (128 bytes), and/
or external memory to be cleared, protecting sen-
sitive information in the event tampering occurs.
By embedding the 32kHz crystal in the package,
the clock is completely isolated from external tam-
pering. An Oscillator Fail Bit (OF) is also provided
to ensure correct operation of the oscillator.
The M41ST87Y/W is supplied in a 28-pin, 300mil
SOIC package (MX) which includes an embedded
32kHz crystal.
The SOIC package is shipped in plastic anti-static
tubes or in Tape & Reel form.
The 300mil, embedded crystal SOIC requires only
a user-supplied battery to provide non-volatile op-
eration.
M41ST87Y, M41ST87W
Table 1. Signal NamesNote:1. Open drain output Programmable output (Open drain or Full-CMOS) Should be connected to VSS.
7/40
M41ST87Y, M41ST87W
M41ST87Y, M41ST87W
9/40
M41ST87Y, M41ST87W
OPERATING MODESThe M41ST87Y/W clock operates as a slave de-
vice on the serial bus. Access is obtained by im-
plementing a start condition followed by the
correct slave address (D0h). The 160 bytes con-
tained in the device can then be accessed sequen-
tially in the following order:
00h. Tenths/Hundredths of a Second Regis-
ter
01h. Seconds Register
02h. Minutes Register
03h. Century/Hours Register
04h. Day Register
05h. Date Register
06h. Month Register
07h. Year Register
08h. Control Register
09h. Watchdog Register
0Ah-0Eh. Alarm Registers
0Fh. Flag Register
10h-12h. Reserved
13h. Square Wave
14h. Tamper Register 1
15h. Tamper Register 2
16h-1Dh. Serial Number (8 bytes)
1Eh-1Fh. Reserved (2 bytes)
20h-9Fh. User RAM (128 bytes)
The M41ST87Y/W clock continually monitors VCC
for an out-of-tolerance condition. Should VCC fall
below VPFD, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When VCC falls below VSO, the device automati-
cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
VCC rises above VSO, the battery is disconnected,
and the power supply is switched to external VCC.
Write protection continues until VCC reaches VPFD
(min) plus trec (min).
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus CharacteristicsThe bus is intended for communication between
different ICs. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the bus
is not busy. During data transfer, the data line must remain
stable whenever the clock line is High. Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
M41ST87Y, M41ST87W
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
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M41ST87Y, M41ST87W
M41ST87Y, M41ST87W
READ ModeIn this mode the master reads the M41ST87Y/W
slave after setting the slave address (see Figure
9., page 12). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address 'An' is written to the on-chip address
pointer. Next the START condition and slave ad-
dress are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master trans-
mitter becomes the master receiver.
The data byte which was addressed will be trans-
mitted and the master receiver will send an Ac-
knowledge Bit to the slave transmitter. The
address pointer is only incremented on reception
of an Acknowledge Clock. The M41ST87Y/W
slave transmitter will now place the data byte at
address An+1 on the bus, the master receiver
reads and acknowledges the new byte and the ad-
dress pointer is incremented to An+2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure
10., page 12).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
Note: This is true both in READ Mode and WRITEMode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41ST87Y/W
slave without first writing to the (volatile) address
pointer. The first address that is read is the last
one stored in the pointer (see Figure
11., page 13).
13/40
M41ST87Y, M41ST87WIn this mode the master transmitter transmits to
the M41ST87Y/W slave receiver. Bus protocol is
shown in Figure 12., page 13. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST87Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see Figure
9., page 12) and again after it has received the
word address and each data byte.
M41ST87Y, M41ST87W
Data Retention ModeWith valid VCC applied, the M41ST87Y/W can be
accessed as described above with READ or
WRITE Cycles. Should the supply voltage decay,
the M41ST87Y/W will automatically deselect,
write protecting itself (and any external SRAM)
when VCC falls between VPFD (max) and
VPFD (min) (see Figure 27., page 36, Table
17., page 36). This is accomplished by internally
inhibiting access to the clock registers. At this
time, the Reset pin (RST) is driven active and will
remain active until VCC returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing ECON to a high level. This level is
within 0.2 volts of the VBAT. ECON will remain at
this level as long as VCC remains at an out-of-tol-
erance condition. When VCC falls below the Bat-
tery Back-up Switchover Voltage (VSO), power
input is switched from the VCC pin to the battery,
and the clock registers and external SRAM are
maintained from the attached battery supply.
All outputs become high impedance. The VOUT pin
is capable of supplying 100µA (for M41ST87W) or
150µA (for M41ST87Y) of current to the attached
memory with less than 0.3 volts drop under this
condition. On power up, when VCC returns to a
nominal value, write protection continues for trec
by inhibiting ECON. The RST signal also remains
active during this time (see Figure 27., page 36).
Note: Most low power SRAMs on the market to-day can be used with the M41ST87Y/W RTC SU-
PERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all oth-
er inputs to the SRAM. This allows inputs to the
M41ST87Y/W and SRAMs to be “Don’t Care”
once VCC falls below VPFD(min). The SRAM
should also guarantee data retention down to
VCC=2.0 volts. The chip enable access time must
be sufficient to meet the system needs with the
chip enable output propagation delays included. If
the SRAM includes a second chip enable pin (E2),
this pin should be tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room tem-
perature along with a worst case condition (gener-
ally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
the SRAMs can then be added to the IBAT value of
the M41ST87Y/W to determine the total current re-
quirements for data retention. The available bat-
tery capacity for the battery of your choice can
then be divided by this current to determine the
amount of data retention available.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
Tamper Detection CircuitThe M41ST87Y/W provides two independent in-
put pins, the Tamper Pin 1 Input (TP1IN) and
Tamper Pin 2 Input (TP2IN), which can be used to
monitor two separate signals which can result in
the associated setting of the Tamper Bits (TB1
and/or TB2, in Flag Register 0Fh) if the Tamper
Enable Bits (TEB1 and/or TEB2) are enabled, for
the respective Tamper 1 or Tamper 2. The TP1IN
Pin or TP2IN Pin may be set to indicate a tamper
event has occurred by either 1) closing a switch to
ground or VOUT (Normally Open), or by 2) opening
a switch that was previously closed to ground or
VOUT (Normally Closed), depending on the state
of the TCMX Bits and the TPMX Bits in the Tamper
Register (14h and/or 15h).
Tamper Register Bits (Tamper 1 and Tamper 2)
Tamper Enable Bits (TEB1 and TEB2). When
set to a logic '1,' this bit will enable the Tamper De-
tection Circuit. This bit must be set to '0' in order to
clear the associated Tamper Bits (TBX, in 0Fh).
Note: TEBX should be reset whenever the TamperDetect condition is modified.
Tamper Bits (TB1 and TB2). If the TEBX Bit is
set, and a tamper condition occurs, the TBX Bit will
be set to '1.' This bit is “Read-only” and is reset
only by setting the TEBX Bit to '0.' These bits are
located in the Flags Register 0Fh.
Tamper Interrupt Enable Bits (TIE1 and TIE2).If this bit is set to a logic '1,' the IRQ/OUT pin will
be activated when a tamper event occurs. This
function is also valid in battery back-up if the ABE
Bit (Alarm in Battery Back-up) is also set to '1' (see
Figure 15., page 16).
Note: In order to avoid an inadvertent activation ofthe IRQ/OUT pin due to a prior tamper event, the
Flag Register (0Fh) should be read prior to reset-
ting the TEBX Bit.
Tamper Connect Mode Bit (TCM1 and TCM2).This bit indicates whether the position of the exter-
nal switch selected by the user is in the Normally
Open (TCMX= '1') or Normally Closed
(TCMX= '0') position (see Figure 14., page 15 and
Figure 16., page 16).
Tamper Polarity Mode Bits (TPM1 and TPM2).The state of this bit indicates whether the Tamper
Pin Input will be taken high (to VOUT if TPMX = '1')
or low (to VSS if TPMX = '0') during a tamper event
(see Figure 14., page 15 and Figure
16., page 16).
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M41ST87Y, M41ST87W
M41ST87Y, M41ST87W
Tamper Detect Sampling (TDS1 and TDS2).This bit selects between a 1Hz sampling rate or
constant monitoring of the Tamper Input Pin(s) to
detect a tamper event when the Normally Closed
switch mode is selected. This allows the user to re-
duce the current drain when the TEBX Bit is en-
abled while the device is in battery backup (see
Table 4., page 17 and Figure 17., page 18). Sam-
pling is disabled if the TCMX Bit is set to logic '1'
(Normally Open). In this case the state of the
TDSX Bit is a “Don’t care.”
Note: The crystal oscillator must be “On” for sam-pling to be enabled.
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M41ST87Y, M41ST87W
Tamper Current Hi/Tamper Current Lo (TCHI/
TCLO1 and TCHI/TCLO2). This bit selects the
strength of the internal pull-up or pull-down used
during the sampling of the Normally Closed condi-
tion. The state of the TCHI/TCLOX Bit is a “Don’t
care” for Normally Open (TCMX = '1') mode (see
Figure 18., page 18).
RAM Clear (CLR1 and CLR2). When either of
these bits and the TEBX Bit are set to a logic '1,'
the internal 128 bytes of user RAM (see Figure
15., page 16) will be cleared to all zeros in the
event of a tamper condition. The 128 bytes of user
RAM will be deselected (invalid data will be read)
until the corresponding TEBX Bit is reset to '0.'
RAM Clear External (CLR1EXT and CLR2EXT).When either of these bits are set to a logic '1' and
the TEBX Bit is also set to logic '1,' the external
SRAM will be cleared and the RST output enabled
(see Figure 15., page 16 and Figure
20., page 20).
Note: The reset output resulting from a tamper
event will be the same as a reset resulting from a
power-down condition, a watchdog time-out, or a
manual reset (RSTIN1 or RSTIN2).
This is accomplished by forcing TPCLR high, which
if used to control the inhibit pin of the DC regulator
(see Figure 20., page 20) will also switch off VOUT,
depriving the external SRAM of power to the VCC
pin. VOUT will automatically be disconnected from
the battery if the tamper occurs during battery
back-up (see Figure 19., page 19). By inhibiting
the DC regulator, the user will also prevent other
inputs from sourcing current to the external SRAM,
allowing it to retain data.
The user may optionally connect an inverting
charge pump to the VCC pin of the external SRAM
(see Figure 20., page 20). Depending on the pro-
cess technology used for the manufacturing of the
external SRAM, clearing the memory may require
varying durations of negative potential on the VCC
pin. This device configuration will allow the user to
program the time needed for their particular appli-
cation. Control Bits CLRPW0 and CLRPW1 deter-
mine the duration TPCLR will be enabled (see
Figure 19., page 19 and Table 5., page 19).
Note: When using the inverting charge pump, theuser must also provide isolation in the form of two
additional small-signal power MOSFETs. These
will isolate the VOUT pin from both the negative
voltage generated by the charge pump during a
tamper condition, and from being pulled to ground
by the output of the charge pump when it is in shut-
down mode (SHDN = logic low). The gates of both
MOSFETs should be connected to TPCLR as
shown in Figure 20., page 20. One n-channel en-
hancement MOSFET should be placed between
the output of the inverting charge pump and the
VOUT of the M41ST87. The other MOSFET should
be an enhancement mode p-channel, and placed
between VOUT of the M41ST87 and VCC of the ex-
ternal SRAM. When TPCLR goes high after a
tamper condition occurs, the n-channel MOSFET
will turn on and the p-channel will turn off. During
normal operating conditions, TPCLR will be low
and the p-channel will be on, while the n-channel
will be off.
Table 4. Tamper Detection Current (Normally Closed - TCMX = '0')Note:1. When calculating battery lifetime, this current should be added to IBAT current listed in Table 16., page35. Per Tamper Detect Input
M41ST87Y, M41ST87W
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M41ST87Y, M41ST87W
M41ST87Y, M41ST87W
