M41ST85WMH6F ,512 Kbit (64 Bit x8) Serial Access RTC and NVRAM SupervisorM41ST85YM41ST85W5.0 or 3.0V, 512 bit (64 x 8)Serial RTC and NVRAM Supervisor
M41ST85WMH6TR ,512 Kbit (64 Bit x8) Serial Access RTC and NVRAM SupervisorBlock Diagram . . 6Figure 7. Hardware Hookup . . . . . . . 7OPERATING MODES . . ..
M41ST85WMX6 ,512 Kbit (64 Bit x8) Serial Access RTC and NVRAM SupervisorFEATURES SUMMARY . . . . . 1Figure 1. 28-pin SOIC Package . . . . 1Figure 2. 28-pin (3 ..
M41ST85WMX6TR ,512 Kbit (64 Bit x8) Serial Access RTC and NVRAM SupervisorFEATURES SUMMARY■ 5.0 OR 3.0V OPERATING VOLTAGE Figure 1. 28-pin SOIC Package2■ SERIAL INTERFACE SU ..
M41ST85YMH6 ,512 Kbit (64 Bit x8) Serial Access RTC and NVRAM Supervisorfeatures include a Power-OnCaution: Do not place the SNAPHAT battery/crys-Reset as well as two addi ..
M41ST87WMX6 ,5.0, 3.3, OR 3.0V, 1280 Bit (160 X8) Secure Serial RTC and NVRAM Supervisor with Tamper DetectionBlock Diagram . . 7Figure 5. Hardware Hookup . . . . . . . 8OPERATING MODES . . ..
M5M54R08AJ-10 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08AJ-10 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08J-12 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08J-15 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R16AJ-10 , 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
M5M54R16AJ-12 , 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
M41ST85WMH6-M41ST85WMH6E-M41ST85WMH6F-M41ST85WMH6TR-M41ST85WMX6-M41ST85WMX6TR-M41ST85YMH6
512 Kbit (64 Bit x8) Serial Access RTC and NVRAM Supervisor
1/34September 2004
M41ST85Y
M41ST85W5.0 or 3.0V, 512 bit (64 x 8)
Serial RTC and NVRAM Supervisor
FEATURES SUMMARY 5.0 OR 3.0V OPERATING VOLTAGE SERIAL INTERFACE SUPPORTS I2 C BUS
(400 KHz) NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM OPTIMIZED FOR MINIMAL
INTERCONNECT TO MCU 2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY CHOICE OF POWER-FAIL DESELECT
VOLTAGES M41ST85Y: VCC = 4.5 to 5.5V;
4.20V ≤ VPFD ≤ 4.50V M41ST85W: VCC = 2.7 to 3.6V;
2.55V ≤ VPFD ≤ 2.70V 1.25V REFERENCE (for PFI/PFO) COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY 44 BYTES OF GENERAL PURPOSE RAM PROGRAMMABLE ALARM AND
INTERRUPT FUNCTION (VALID EVEN
DURING BATTERY BACK-UP MODE) WATCHDOG TIMER MICROPROCESSOR POWER-ON RESET BATTERY LOW FLAG POWER-DOWN TIMESTAMP (HT BIT) ULTRA-LOW BATTERY SUPPLY CURRENT
OF 500nA (MAX) PACKAGING INCLUDES A 28-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately) SOIC SNAPHAT PACKAGE PROVIDES
DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY
AND CRYSTAL SOIC EMBEDDED CRYSTAL PACKAGE
(MX) OPTION
M41ST85Y, M41ST85W
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. 28-pin (300mil) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. 28-pin, 300mil SOIC (MX) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 8. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 9. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 10.WRITE Cycle Timing: RTC & External SRAM Control Signals . . . . . . . . . . . . . . . . . . . . .9
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 11.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 12.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 13.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 14.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Power-down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Table 2. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 15.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 16.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Figure 17.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 3. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 18.Back-Up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 4. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Figure 19.RSTIN1 & RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 5. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3/34
M41ST85Y, M41ST85W
Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
trec Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 6. trec Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Table 9. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 20.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 21.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 12. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 22.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 13. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Figure 23.SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline. . . . . . . .28
Table 14. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 28
Figure 24.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . .29
Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Mechanical Data . . . . . . .29
Figure 25.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . .30
Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Mechanical Data . . . . . .30
Figure 26.SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline.31
Table 17. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Mech. Data. . . . .31
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 19. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
M41ST85Y, M41ST85W
SUMMARY DESCRIPTIONThe M41ST85Y/W Serial TIMEKEEPER® /Con-
troller SRAM is a low power 512-bit, static CMOS
SRAM organized as 64 words by 8 bits. A built-in
32.768 kHz oscillator (external crystal controlled)
and 8 bytes of the SRAM (see Table 2., page 14)
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
An additional 12 bytes of RAM provide status/con-
trol of Alarm, Watchdog and Square Wave func-
tions. Addresses and data are transferred serially
via a two line, bi-directional I2 C interface. The
built-in address register is incremented automati-
cally after each WRITE or READ data byte. The
M41ST85Y/W has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power fail-
ure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
small lithium button-cell supply when a power fail-
ure occurs.
Functions available to the user include a non-vol-
atile, time-of-day clock/calendar, Alarm interrupts,
Watchdog Timer and programmable Square
Wave output. Other features include a Power-On
Reset as well as two additional debounced inputs
(RSTIN1 and RSTIN2) which can also generate an
output Reset (RST). The eight clock address loca-
tions contain the century, year, month, date, day,
hour, minute, second and tenths/hundredths of a
second in 24 hour BCD format. Corrections for 28,
29 (leap year - valid until year 2100), 30 and 31
day months are made automatically.
The M41ST85Y/W is supplied in a 28-lead SOIC
SNAPHAT® package (which integrates both crys-
tal and battery in a single SNAPHAT top) or a 28-
pin, 300mil SOIC package (MX) which includes an
embedded 32kHz crystal.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery/crystal package to
be mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28-lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is “M4TXX-BR12SH” (see Table
19., page 32).
Caution: Do not place the SNAPHAT battery/crys-tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
The 300mil, embedded crystal SOIC requires only
a user-supplied battery to provide non-volatile op-
eration.
5/34
M41ST85Y, M41ST85W
Table 1. Signal NamesNote:1. For 28-pin, 300mil embedded crystal SOIC only.
Figure 4. 28-pin SOIC Connections Figure 5. 28-pin, 300mil SOIC (MX)
ConnectionsNote: No Function (NF) pins should be tied to VSS. Pins 1, 2, 3, and
4 are internally shorted together.
M41ST85Y, M41ST85W
7/34
M41ST85Y, M41ST85W
M41ST85Y, M41ST85W
OPERATING MODESThe M41ST85Y/W clock operates as a slave de-
vice on the serial bus. Access is obtained by im-
plementing a start condition followed by the
correct slave address (D0h). The 64 bytes con-
tained in the device can then be accessed sequen-
tially in the following order: Tenths/Hundredths of a Second Register Seconds Register Minutes Register Century/Hours Register Day Register Date Register Month Register Year Register Control Register
10. Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20. Square Wave Register
21 - 64. User RAM
The M41ST85Y/W clock continually monitors VCC
for an out-of-tolerance condition. Should VCC fall
below VPFD, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When VCC falls below VSO, the device automati-
cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
VCC rises above VSO, the battery is disconnected,
and the power supply is switched to external VCC.
Write protection continues until VCC reaches
VPFD(min) plus trec (min).
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus CharacteristicsThe bus is intended for communication between
different ICs. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the bus
is not busy. During data transfer, the data line must remain
stable whenever the clock line is High. Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
9/34
M41ST85Y, M41ST85W
M41ST85Y, M41ST85W
READ ModeIn this mode the master reads the M41ST85Y/W
slave after setting the slave address (see Figure
11., page 10). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address 'An' is written to the on-chip address
pointer. Next the START condition and slave ad-
dress are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master trans-
mitter becomes the master receiver.
The data byte which was addressed will be trans-
mitted and the master receiver will send an Ac-
knowledge Bit to the slave transmitter. The
address pointer is only incremented on reception
of an Acknowledge Clock. The M41ST85Y/W
slave transmitter will now place the data byte at
address An+1 on the bus, the master receiver
reads and acknowledges the new byte and the ad-
dress pointer is incremented to An+2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure
12., page 10).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
Note: This is true both in READ Mode and WRITEMode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41ST85Y/W
slave without first writing to the (volatile) address
pointer. The first address that is read is the last
one stored in the pointer (see Figure
13., page 11).
11/34
M41ST85Y, M41ST85WIn this mode the master transmitter transmits to
the M41ST85Y/W slave receiver. Bus protocol is
shown in Figure 14., page 11. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST85Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see Figure
11., page 10) and again after it has received the
word address and each data byte.
M41ST85Y, M41ST85W
Data Retention ModeWith valid VCC applied, the M41ST85Y/W can be
accessed as described above with READ or
WRITE Cycles. Should the supply voltage decay,
the M41ST85Y/W will automatically deselect,
write protecting itself (and any external SRAM)
when VCC falls between VPFD(max) and
VPFD(min). This is accomplished by internally in-
hibiting access to the clock registers. At this time,
the Reset pin (RST) is driven active and will re-
main active until VCC returns to nominal levels. Ex-
ternal RAM access is inhibited in a similar manner
by forcing ECON to a high level. This level is within
0.2 volts of the VBAT. ECON will remain at this level
as long as VCC remains at an out-of-tolerance con-
dition. When VCC falls below the Battery Back-up
Switchover Voltage (VSO), power input is switched
from the VCC pin to the SNAPHAT® battery, and
the clock registers and external SRAM are main-
tained from the attached battery supply.
All outputs become high impedance. The VOUT pin
is capable of supplying 100 µA of current to the at-
tached memory with less than 0.3 volts drop under
this condition. On power up, when VCC returns to
a nominal value, write protection continues for trec
by inhibiting ECON. The RST signal also remains
active during this time (see Figure 22., page 27).
Note: Most low power SRAMs on the market to-day can be used with the M41ST85Y/W RTC SU-
PERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all oth-
er inputs to the SRAM. This allows inputs to the
M41ST85Y/W and SRAMs to be “Don’t Care”
once VCC falls below VPFD(min). The SRAM
should also guarantee data retention down to
VCC=2.0 volts. The chip enable access time must
be sufficient to meet the system needs with the
chip enable output propagation delays included. If
the SRAM includes a second chip enable pin (E2),
this pin should be tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room tem-
perature along with a worst case condition (gener-
ally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
the SRAMs can then be added to the IBAT value of
the M41ST85Y/W to determine the total current re-
quirements for data retention. The available bat-
tery capacity for the SNAPHAT® of your choice
can then be divided by this current to determine
the amount of data retention available (see Table
19., page 32).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
13/34
M41ST85Y, M41ST85W
CLOCK OPERATIONThe eight byte clock register (see Table
2., page 14) is used to both set the clock and to
read the date and time from the clock, in a binary
coded decimal format. Tenths/Hundredths of Sec-
onds, Seconds, Minutes, and Hours are contained
within the first four registers.
Note: A WRITE to any clock register will result inthe Tenths/Hundredths of Seconds being reset to
“00,” and Tenths/Hundredths of Seconds cannot
be written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (de-
pending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Control Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h con-
tains the STOP Bit (ST). Setting this bit to a '1' will
cause the oscillator to stop. If the device is expect-
ed to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce cur-
rent drain. When reset to a '0' the oscillator restarts
within one second.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 08h) may be accessed in-
dependently. Provision has been made to assure
that a clock update does not occur while any of the
eight clock addresses are being read. If a clock ad-
dress is being read, an update of the clock regis-
ters will be halted. This will prevent a transition of
data during the READ.
Power-down Time-StampWhen a power failure occurs, the Halt Update Bit
(HT) will automatically be set to a '1.' This will pre-
vent the clock from updating the TIMEKEEPER®
registers, and will allow the user to read the exact
time of the power-down event. Resetting the HT
Bit to a '0' will allow the clock to update the TIME-
KEEPER registers with the current time. For more
information, see Application Note AN1572.
TIMEKEEPER® RegistersThe M41ST85Y/W offers 20 internal registers
which contain Clock, Alarm, Watchdog, Flag,
Square Wave and Control data. These registers
are memory locations which contain external (user
accessible) and internal copies of the data (usually
referred to as BiPORT™ TIMEKEEPER cells). The
external copies are independent of internal func-
tions except that they are updated periodically by
the simultaneous transfer of the incremented inter-
nal copy. The internal divider (or clock) chain will
be reset upon the completion of a WRITE to any
clock address.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
TIMEKEEPER and Alarm Registers store data in
BCD. Control, Watchdog and Square Wave Reg-
isters store data in Binary Format.
M41ST85Y, M41ST85W
Table 2. TIMEKEEPER® Register MapKeys: S = Sign Bit
FT = Frequency Test Bit
ST = Stop Bit
0 = Must be set to zero
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Century Bit
OUT = Output level
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag (Read only)
AF = Alarm flag (Read only)
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
HT = Halt Update Bit
TR = trec Bit
15/34
M41ST85Y, M41ST85W
Calibrating the ClockThe M41ST85Y/W is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not exceed +/–35 ppm
(parts per million) oscillator frequency error ato C, which equates to about +/–1.53 minutes per
month. When the Calibration circuit is properly em-
ployed, accuracy improves to better than ±2 ppm
at 25°C.
The oscillation rate of crystals changes with tem-
perature (see Figure 15., page 16). Therefore, the
M41ST85Y/W design employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the di-
vide by 256 stage, as shown in Figure
16., page 16. The number of times pulses which
are blanked (subtracted, negative calibration) or
split (added, positive calibration) depends upon
the value loaded into the five Calibration Bits found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Control Register (08h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M41ST85Y/W may re-
quire.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate ref-
erence and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934, “TIMEKEEP-® CALIBRATION.” This allows the designer to
give the end user the ability to calibrate the clock
as the environment requires, even if the final prod-
uct is packaged in a non-user serviceable enclo-
sure. The designer could provide a simple utility
that accesses the Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT/OUT pin. The pin will toggle at 512Hz,
when the Stop Bit (ST, D7 of 01h) is '0,' the Fre-
quency Test Bit (FT, D6 of 08h) is '1,' the Alarm
Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the
Watchdog Steering Bit (WDS, D7 of 09h) is '1' or
the Watchdog Register (09h = 0) is reset.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124 Hz would indicate a +20 ppm oscilla-
tor frequency error, requiring a –10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency test output frequen-
cy.
The IRQ/FT/OUT pin is an open drain output
which requires a pull-up resistor to VCC for proper
operation. A 500 to10k resistor is recommended in
order to control the rise time. The FT Bit is cleared
on power-down.
M41ST85Y, M41ST85W
17/34
M41ST85Y, M41ST85W
Setting Alarm Clock RegistersAddress locations 0Ah-0Eh contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second, or repeat every year, month,
day, hour, minute, or second. It can also be pro-
grammed to go off while the M41ST85Y/W is in the
battery back-up to serve as a system wake-up call.
Bits RPT5–RPT1 put the alarm in the repeat mode
of operation. Table 3., page 17 shows the possible
configurations. Codes not listed in the table default
to the once per second mode to quickly alert the
user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5–RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT/OUT pin as shown in
Figure 17., page 17. To disable alarm, write '0' to
the Alarm Date Register and to RPT5–RPT1.
Note: If the address pointer is allowed to incre-ment to the Flag Register address, an alarm con-
dition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different ad-
dress. It should also be noted that if the last ad-
dress written is the “Alarm Seconds,” the address
pointer will increment to the Flag address, causing
this situation to occur.
The IRQ/FT/OUT output is cleared by a READ to
the Flags Register. A subsequent READ of the
Flags Register is necessary to see that the value
of the Alarm Flag has been reset to '0.'
The IRQ/FT/OUT pin can also be activated in the
battery back-up mode. The IRQ/FT/OUT will go
low if an alarm occurs and both ABE (Alarm in Bat-
tery Back-up Mode Enable) and AFE are set. The
ABE and AFE Bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M41ST85Y/W was in the de-
select mode during power-up. Figure 18., page18
illustrates the back-up mode alarm timing.
