M41ST84W ,512 BIT (64 X 8) SERIAL RTC WITH SUPERVISORY FUNCTIONSFEATURES SUMMARY■ 5.0 OR 3.0V OPERATING VOLTAGE Figure 1. 16-pin SOIC Package2■ SERIAL INTERFACE SU ..
M41ST84W. ,512 BIT (64 X 8) SERIAL RTC WITH SUPERVISORY FUNCTIONSLogic Diagram Table 1. Signal Names(1) (1)Oscillator InputXIV VCC BAT(1)XO Oscillator OutputInterru ..
M41ST84WMQ6 ,512 Bit (64 X8) Serial RTC with Supervisory FunctionsFEATURES SUMMARY . . . . . 1Figure 1. 16-pin SOIC Package . . . . 1Figure 2. 28-pin SO ..
M41ST84WMQ6E ,512 Bit (64 X8) Serial RTC with Supervisory FunctionsLogic Diagram Table 1. Signal Names (1) (1)XI Oscillator InputV VCC BAT (1)Oscillator OutputXOInter ..
M41ST84WMQ6F ,512 Bit (64 X8) Serial RTC with Supervisory FunctionsFEATURES SUMMARY■ 5.0 OR 3.0V OPERATING VOLTAGE Figure 1. 16-pin SOIC Package2■ SERIAL INTERFACE SU ..
M41ST84WMQ6TR ,512 Bit (64 X8) Serial RTC with Supervisory FunctionsBlock Diagram . . 5Figure 7. Hardware Hookup . . . . . . . 6OPERATING MODES . . ..
M5M5408BTP , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08AJ-10 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08AJ-10 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08J-12 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08J-15 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R16AJ-10 , 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
M41ST84W-M41ST84W.
512 BIT (64 X 8) SERIAL RTC WITH SUPERVISORY FUNCTIONS
1/31July 2002
M41ST84Y
M41ST84W5.0 OR 3.0V, 512bit (64x 8) SERIALRTC
WITH SUPERVISORY FUNCTIONS
FEATURES SUMMARY 5.0 OR 3.0V OPERATING VOLTAGE SERIAL INTERFACE SUPPORTSI2 CBUS
(400 KHz) OPTIMIZED FOR MINIMAL INTERCONNECT MCU 2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY CHOICE OF POWER-FAIL DESELECT
VOLTAGES: M41ST84Y: VCC= 4.5to 5.5V;
4.20V≤ VPFD≤ 4.50V M41ST84W: VCC =2.7to 3.6V;
2.55V≤ VPFD≤ 2.70V 1.25V REFERENCE (for PFI/PFO) COUNTERS FOR TENTHS/HUNDREDTHS SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, and
CENTURY 44 BYTES OF GENERAL PURPOSE RAM PROGRAMMABLE ALARM and INTERRUPT
FUNCTION (VALID EVEN DURING BATTERY
BACK-UP MODE) WATCHDOG TIMER MICROPROCESSOR POWER-ON RESET BATTERY LOW FLAG ULTRA-LOW BATTERY SUPPLY CURRENT 500 nA (max) OPTIONAL PACKAGING INCLUDESA 28-
LEAD SOIC and SNAPHAT® TOP (tobe
ordered separately) SNAPHAT PACKAGE PROVIDES DIRECT
CONNECTION FORA SNAPHAT TOP,
WHICH CONTAINS THE BATTERY and
CRYSTAL
M41ST84Y, M41ST84W2/31
TABLE OF CONTENTS
SUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... .....4Logic Diagram (Figure 3.). ...... ....... ...... ....... ...... ....... ...... ...... .....4
Signal Names (Table1.).. ...... ....... ...... ....... ...... ....... ...... ...... .....4
16-pin SOIC Connections (Figure4.) ..... ...... ....... ...... ....... ...... ...... .....5
28-pin SOIC Connections (Figure5.) ..... ...... ....... ...... ....... ...... ...... .....5
Block Diagram (Figure6.). ...... ....... ...... ....... ...... ....... ...... ...... .....5
Hardware Hookup (Figure 7.) .... ....... ...... ....... ...... ....... ...... ...... .....6
MAXIMUM RATING... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....6Absolute Maximum Ratings (Table2.) .... ...... ....... ...... ....... ...... ...... .....6
AND AC PARAMETERS.. ...... ....... ...... ....... ...... ....... ...... ...... .....7 and AC Measurement Conditions (Table3.)... ....... ...... ....... ...... ...... .....7 Testing Input/Output Waveforms (Figure8.)... ....... ...... ....... ...... ...... .....7
Capacitance (Table4.)... ...... ....... ...... ....... ...... ....... ...... ...... .....7 Characteristics (Table5.) .... ....... ...... ....... ...... ....... ...... ...... .....8
Crystal Electrical Characteristics(Externally Supplied) (Table 6.)... ....... ...... ...... .....8
OPERATING MODES. ...... ...... ....... ...... ....... ...... ....... ...... ...... .....92-Wire BusCharacteristics ...... ....... ...... ....... ...... ....... ...... ...... .....9
Serial Bus Data Transfer Sequence (Figure9.)... ....... ...... ....... ...... ...... ....10
Acknowledgement Sequence (Figure 10.). ...... ....... ...... ....... ...... ...... ....10
Bus Timing Requirements Sequence (Figure 11.). ....... ...... ....... ...... ...... ....10 Characteristics(Table 7.) .... ....... ...... ....... ...... ....... ...... ...... ....11
READ Mode...... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....12
Slave Address Location (Figure 12.) ...... ...... ....... ...... ....... ...... ...... ....12
READ Mode Sequence (Figure 13.) ...... ...... ....... ...... ....... ...... ...... ....12
Alternate READ Mode Sequence (Figure 14.) .... ....... ...... ....... ...... ...... ....13
WRITEMode ..... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....13
WRITE Mode Sequence (Figure 15.) ..... ...... ....... ...... ....... ...... ...... ....13
Data Retention Mode..... ...... ....... ...... ....... ...... ....... ...... ...... ....14
Power Down/Up Mode AC Waveforms (Figure 16.) ....... ...... ....... ...... ...... ....14
Power Down/Up AC Characteristics (Table 8.) .... ....... ...... ....... ...... ...... ....14
3/31
M41ST84Y, M41ST84W
CLOCKOPERATION. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....15TIMEKEEPER® Registers. ...... ....... ...... ....... ...... ....... ...... ...... ....15
TIMEKEEPER® Register Map (Table 9.).. ...... ....... ...... ....... ...... ...... ....16
Calibrating the Clock ..... ...... ....... ...... ....... ...... ....... ...... ...... ....17
Setting Alarm Clock Registers.... ....... ...... ....... ...... ....... ...... ...... ....18
Alarm Interrupt ResetWaveform (Figure 17.) ..... ....... ...... ....... ...... ...... ....18
Alarm Repeat Modes (Table 10.). ....... ...... ....... ...... ....... ...... ...... ....18
Back-Up Mode Alarm Waveform (Figure 18.) ..... ....... ...... ....... ...... ...... ....19
Watchdog Timer.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....19
Square Wave Output..... ...... ....... ...... ....... ...... ....... ...... ...... ....20
Square Wave Output Frequency (Table 11.)...... ....... ...... ....... ...... ...... ....20
Power-on Reset... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....21
ResetInput (RSTIN) ..... ...... ....... ...... ....... ...... ....... ...... ...... ....21
RSTIN Timing Waveform (Figure 19.)..... ...... ....... ...... ....... ...... ...... ....21
ResetACCharacteristics. ...... ....... ...... ....... ...... ....... ...... ...... ....21
Power-fail INPUT/OUTPUT ...... ....... ...... ....... ...... ....... ...... ...... ....22
Century Bit....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....22
Output Driver Pin.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....22
Battery Low Warning ..... ...... ....... ...... ....... ...... ....... ...... ...... ....22
tREC Bit.. ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....22
Initial Power-on Defaults.. ...... ....... ...... ....... ...... ....... ...... ...... ....22
tREC Definitions (Table 13.) ..... ....... ...... ....... ...... ....... ...... ...... ....23
DefaultValues (Table 14.). ...... ....... ...... ....... ...... ....... ...... ...... ....23
Crystal Accuracy Across Temperature (Figure 20.) ....... ...... ....... ...... ...... ....24
ClockCalibration (Figure 21.) .... ....... ...... ....... ...... ....... ...... ...... ....24
PART NUMBERING.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....25SNAPHAT BatteryTable (Table 16.)...... ...... ....... ...... ....... ...... ...... ....25
PACKAGE MECHANICAL INFORMATION... ...... ....... ...... ....... ...... ...... ....26
REVISION HISTORY.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....30
M41ST84Y, M41ST84W4/31
SUMMARY DESCRIPTIONThe M41ST84Y/W Serial supervisory TIMEKEEP-® SRAMisa low power 512-bit static CMOS
SRAM organizedas64 wordsby8 bits.A built-in
32.768 kHz oscillator (external crystal controlled)
and8 bytesof the SRAM (see Table9, page 16)
are used for the clock/calendar function and are
configuredin binary coded decimal (BCD) format. additional12 bytesof RAM provide status/con-
trolof Alarm, Watchdog and Square Wave func-
tions. Addresses and data are transferred serially
viaa two line, bi-directional I2C interface. The
built-in address registeris incremented automati-
cally after each WRITEor READ data byte.
The M41ST84Y/W hasa built-in power sense cir-
cuit which detects power failures and automatical- switchesto the battery supply whena power
failure occurs. The energy neededto sustain the
SRAM and clock operations canbe suppliedbya
small lithium button-cell supply whena power fail-
ure occurs. Functions availableto the user include non-volatile, time-of-day clock/calendar, Alarm
interrupts, Watchdog Timer and programmable
Square Wave output. Other features includea
Power-On Reset as well as an additional input
(RSTIN) which can also generatean output Reset
(RST). The eight clock address locations contain
the century, year, month, date, day, hour, minute,
second and tenths/hundredthsofa secondin 24
hour BCD format. Correctionsfor 28,29 (leap year valid until year 2100),30 and31 day months are
made automatically.
The M41ST84Y/Wis suppliedina 28-lead SOIC
SNAPHAT® package (which integrates both crys-
tal and batteryina single SNAPHAT top)ora 16-
pin SOIC. The 28-pin, 330mil SOIC provides sock-
ets with gold plated contactsat both endsfor direct
connectiontoa separate SNAPHAT housing con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery/crystal packageto mounted on topof the SOIC package after the
completion of the surface mount process.
Insertionof the SNAPHAT housing after reflow
prevents potential battery and crystal damage due the high temperatures required for device sur-
face-mounting. The SNAPHAT housingis also
keyedto prevent reverse insertion.
The 28-pin SOIC and battery/crystal packages are
shipped separatelyin plastic anti-static tubesorin
Tape& Reel form. For the 28-lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
beris “M4TXX-BR12SH” (see Table 16, page 25).
Caution: Do not place the SNAPHAT battery/crys-
tal topin conductive foam,as this will drain the lith-
ium button-cell battery.
Table1. Signal NamesNote:1. For SO16 package only.
5/31
M41ST84Y, M41ST84W
M41ST84Y, M41ST84W6/31
Stressing the deviceabove therating listedinthe
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operationof the deviceat
theseor any other conditions above those indicat-in the Operating sectionsof this specificationis
not implied. Exposureto Absolute Maximum Rat-
ing conditionsfor extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table2. Absolute Maximum RatingsNote:1. Reflowat peak temperatureof 215°Cto 225°Cfor<60 seconds (total thermal budgetnotto exceed 180°Cfor between90to120
seconds).
CAUTION: Negative undershoots below –0.3Varenot allowedonanypin whileinthe Battery Back-up mode.
CAUTION:Do NOT wave solder SOICto avoid damaging SNAPHAT sockets.
7/31
M41ST84Y, M41ST84W AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristicsof the device. The parametersin
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listedin the relevant tables. De-
signers should check that the operating conditions their projects match the measurement condi-
tions when using the quoted parameters.
Table3. DC and AC Measurement ConditionsNote: Output Hi-Zis definedasthe point where dataisno longer driven.
Table4. CapacitanceNote:1. Effective capacitance measured with power supplyat5V. Sampled only,not 100% tested.At 25°C,f= 1MHz. Outputs deselected.
M41ST84Y, M41ST84W8/31
Table5. DC CharacteristicsNote:1. Validfor Ambient Operating Temperature:TA=–40to 85°C; VCC=2.7to 3.6Vor4.5to 5.5V (except where noted). RSTIN internally pulled-upto VCC through 100KΩ resistor. WDI internally pulled-downto VSS through 100KΩ resistor. Outputs deselected. For PFO and SQW pins (CMOS). For IRQ/FT/OUT, RSTpins (OpenDrain):if pulled-up tosupply other than VCC, thissupply mustbe equalto,or less than3.0Vwhen
VCC=0V (during battery back-up mode). For rechargeable back-up, VBAT (max) maybe considered VCC.
Table6. Crystal Electrical Characteristics (Externally Supplied)Note:1. Load capacitorsare integrated withinthe M41ST84Y/W. Circuit board layout considerationsforthe 32.768 kHz crystalof minimum
trace lengths and isolation fromRF generating signals shouldbe takeninto account. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole)or the DMX-26S:
1TJS125FH2A212, (SMD) quartz crystalfor industrial temperature operations. KDScanbe contactedat
[email protected]tp://www.kdsj.co.jpfor further informationonthis crystal type.
9/31
M41ST84Y, M41ST84W
OPERATING MODESThe M41ST84Y/W clock operatesasa slave de-
vice on the serial bus. Accessis obtainedby im-
plementinga start condition followed by the
correct slave address (D0h). The 64 bytes con-
tainedin the device can thenbe accessed sequen-
tiallyin the following order: Tenths/Hundredthsofa Second Register Seconds Register Minutes Register Century/Hours Register Day Register Date Register Month Register Year Register Control Register
10. Watchdog Register- 16. Alarm Registers- 19. Reserved
20. Square Wave Register- 64. User RAM
The M41ST84Y/W clock continually monitors VCC
for an out-of tolerance condition. Should VCC fall
below VPFD, the device terminates an accessin
progress and resets the device address counter.
Inputsto the device will notbe recognizedat this
timeto prevent erroneous data from being written the device froma an out-of-tolerance system.
When VCC falls below VSO, the device automati-
cally switches overto the battery and powers
down intoan ultra low current modeof operationto
conserve battery life.As system power returns and
VCC rises above VSO, the batteryis disconnected,
and the power supplyis switchedto external VCC.
Write protection continues until VCC reaches
VPFD(min) plus tREC (min).
For more informationon Battery Storage Life refer Application Note AN1012.
2-Wire Bus CharacteristicsThe busis intended for communication between
different IC’s.It consistsof two lines:a bi-direction- data signal (SDA) anda clock signal (SCL).
Both the SDA and SCL lines mustbe connectedto positive supply voltage viaa pull-up resistor.
The following protocol has been defined: Data transfer maybe initiated only when the bus not busy. During data transfer, the data line must remain
stable whenever the clock lineis High. Changesin the data line, while the clock lineis
High, willbe interpretedas control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer.A changein the stateof the
data line, from Highto Low, while the clockis High,
defines the START condition.
Stop data transfer.A changein the stateof the
data line, from Lowto High, while the clockis High,
defines the STOP condition.
Data Valid. Thestateof thedatalinerepresents
valid data when aftera start condition, the data line stable for the durationof the high periodof the
clock signal. The dataon the line maybe changed
during the Low periodof the clock signal. Thereis
one clock pulse perbitof data.
Each data transferis initiated witha start condition
and terminated witha stop condition. The number data bytes transferred between the start and
stop conditionsis not limited. The informationis
transmitted byte-wide and each receiver acknowl-
edges witha ninth bit. definitiona device that gives outa messageis
called “transmitter”, the receiving device that gets
the messageis called “receiver”. The device that
controls the messageis called “master”. The de-
vices that are controlledby the master are called
“slaves”.
Acknowledge. Each byteof eight bitsis followed one Acknowledge Bit. This Acknowledge Bitis low level puton the busby the receiver whereas
the master generatesan extra acknowledge relat- clock pulse.A slave receiver whichis ad-
dressedis obligedto generate an acknowledge
after the receptionof each byte that has been
clocked outof the slave transmitter.
The device that acknowledges hasto pull down
the SDA line during the acknowledge clock pulse sucha way that the SDA lineisa stable Low dur-
ing the High periodof the acknowledge related
clock pulse.Of course, setup and hold times must taken into account.A master receiver must sig-
nalan endof datato the slave transmitterby not
generating an acknowledge on the last byte that
has been clocked outof the slave.In this case the
transmitter must leave the data line Highto enable
the masterto generate the STOP condition.
M41ST84Y, M41ST84W10/31
11/31
M41ST84Y, M41ST84W
Table7. AC CharacteristicsNote:1. Validfor Ambient Operating Temperature:TA=–40to 85°C; VCC=2.7to 3.6Vor4.5to 5.5V (except where noted). Transmitter must internally providea hold timeto bridgethe undefined region (300ns max)ofthe falling edgeof SCL.
M41ST84Y, M41ST84W12/31
READ Mode this mode the master reads the M41ST84Y/W
slave after setting the slave address (see Figure
12, page 12). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address ‘An’is writtento the on-chip address
pointer. Next the START condition and slave ad-
dress are repeated followed by the READ Mode
ControlBit (R/W=1).At this point the master trans-
mitter becomes the master receiver. The data byte
which was addressed willbe transmitted and the
master receiver will send an Acknowledge Bitto
the slave transmitter. The address pointeris only
incremented on reception of an Acknowledge
Clock. The M41ST84Y/W slave transmitter will
now place the data byteat address An+1 on the
bus, the master receiver reads and acknowledges
the new byte and the address pointer is
incrementedto “An+2.”
This cycleof reading consecutive addresses will
continue until the master receiver sendsa STOP
conditionto the slave transmitter (see Figure 13,
page 12).
The system-to-user transferof clock data will be
halted whenever the address being readisa clock
address (00hto 07h). The update will resumeei-
ther duetoa Stop Conditionor when the pointer
incrementstoa non-clockor RAM address.
Note: Thisis true bothin READ Mode and WRITE
Mode. alternateREAD Mode may alsobeimplement- whereby the master reads the M41ST84Y/W
slave without first writingto the (volatile) address
pointer. The first address thatis readis the last
one storedin the pointer (see Figure 14, page 13).
13/31
M41ST84Y, M41ST84W this mode the master transmitter transmitsto
the M41ST84Y/W slave receiver. Bus protocolis
shown in Figure 15, page 13. Following the
START condition and slave address,a logic'0' (R/
W=0)is placedon the bus and indicatesto the ad-
dressed device that word address An will follow
andistobe writtento the on-chip address pointer.
Thedatawordtobe writtento thememoryis
strobedin next and the internal address pointeris
incrementedto the next memory location within
the RAM on the receptionof an acknowledge
clock. The M41ST84Y/W slave receiver will send acknowledge clockto the master transmitteraf-
terit has received the slave address (see Figure
12, page 12) and again afterit has received the
word address and each data byte.
M41ST84Y, M41ST84W14/31
Data Retention ModeWith valid VCC applied, the M41ST84Y/W canbe
accessed as described above with READ or
WRITE cycles. Should the supply voltage decay,
the M41ST84Y/W will automatically deselect,
write protecting itself when VCC falls between
VPFD(max) and VPFD(min). Thisis accomplished internally inhibiting accessto the clock regis-
ters.At this time, the Reset pin (RST)is driven ac-
tive and will remain active until VCC returnsto
nominal levels. When VCC falls below the Battery
Back-up Switchover Voltage (VSO), power inputis
switched from the VCC pinto the SNAPHAT® (or
external) battery, and the clock registers and
SRAM are maintained from the attached battery
supply.
All outputs become high impedance. On power up,
when VCC returnstoa nominal value, write protec-
tion continues for tREC.The RST signal also re-
mains activeduringthis time(seeFigure16, page
14).
Fora further more detailed reviewof lifetime calcu-
lations, please see Application Note AN1012.
15/31
M41ST84Y, M41ST84W
CLOCK OPERATIONThe eight byte clock register (see Table9, page
16)is usedto both set the clock andto read the
date and time from the clock,ina binary coded
decimal format. Tenths/Hundredthsof Seconds,
Seconds, Minutes, and Hours are contained within
the first four registers.
Note:A WRITEto any clock register will resultin
the Tenths/Hundredthsof Seconds being resetto
“00,” and Tenths/Hundredthsof Seconds cannot writtento any value other than “00.”
Bits D6 and D7of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEBtoa'1' will cause CBto toggle, either from'0''1'or from'1'to'0'at the turnof the century (de-
pending uponits initial state).If CEBis settoa '0,' will not toggle. Bits D0 through D2of Register
04h contain the Day (dayof week). Registers 05h,
06h, and 07h contain the Date (dayof month),
Month and Years. The ninth clock registeris the
Control Register (thisis describedin the Clock
Calibration section). Bit D7of Register 01h con-
tains the STOPBit (ST). Setting thisbittoa'1' will
cause the oscillatorto stop.If the deviceis expect-to spenda significant amountof time on the
shelf, the oscillator maybe stoppedto reduce cur-
rent drain. When resettoa'0' the oscillator restarts
within one second.
The eight clock registers maybe read one byteat time,orina sequential block. The Control Reg-
ister (Address location 08h) maybe accessedin-
dependently. Provision has been madeto assure
thata clock update does not occur while anyof the
eight clock addresses are being read.Ifa clock ad-
dressis being read,an updateof the clock regis-
ters willbe halted. This will preventa transitionof
data during the READ.
Note: Whena power failure occurs, the Halt Up-
dateBit (HT) will automatically beset toa'1.'This
will prevent the clock from updating the TIME-
KEEPER® registers, and will allow the userto read
the exact timeof the power-down event. Resetting
the HT Bittoa'0' will allow the clockto update the
TIMEKEEPER registers with the current time.
TIMEKEEPER® RegistersThe M41ST84Y/W offers 12 additional internal
registers which contain the Alarm, Watchdog,
Flag, Square Wave and Control data. These reg-
isters are memory locations which contain external
(user accessible) and internal copiesof the data
(usually referredto as BiPORT™ TIMEKEEPER
cells). The external copies are independentofin-
ternal functions except that they are updated peri-
odically by the simultaneous transfer of the
incremented internal copy. The internal divider (or
clock) chain willbe reset upon the completionofa
WRITEto any clock address.
The system-to-user transferof clock data will be
halted whenever the address being readisa clock
address (00hto 07h). The update will resumeei-
ther duetoa Stop Conditionor when the pointer
incrementstoa non-clockor RAM address.
TIMEKEEPER and Alarm Registers store datain
BCD. Control, Watchdog and Square Wave Reg-
isters store datain Binary Format.
M41ST84Y, M41ST84W16/31
Table9. TIMEKEEPER® Register MapKeys:S= SignBit= Frequency TestBit= StopBit
0=Mustbeset tozero= Battery Low Flag (Read only)
BMB0-BMB4= Watchdog MultiplierBits
CEB= Century EnableBit= CenturyBit
OUT= Output level
AFE= Alarm Flag Enable Flag
RB0-RB1= Watchdog Resolution Bits
WDS= Watchdog SteeringBit
ABE= Alarmin Battery Back-Up Mode EnableBit
RPT1-RPT5= Alarm Repeat Mode Bits
WDF= Watchdogflag (Read only)= Alarm flag (Read only)
SQWE= Square Wave Enable
RS0-RS3= SQW Frequency= Halt UpdateBit= tRECBit
