M40Z300WMH6TR ,NVRAM CONTROLLER FOR UP TO EIGHT LPSRAMAbsolute Maximum Ratings . . . . . . . 10DC AND AC PARAMETERS . 11Table 4. DC and AC Meas ..
M40Z300WMQ6 ,NVRAM CONTROLLER FOR UP TO EIGHT LPSRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 4. 28-pin SOIC Connections ..
M41000000G , 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
M41000000H , 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
M41000001W , 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM
M41000001X , 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM
M5M5408BFP , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M5408BTP , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08AJ-10 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08AJ-10 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08J-12 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08J-15 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M40Z300WMH6-M40Z300WMH6TR-M40Z300WMQ6
NVRAM CONTROLLER FOR UP TO EIGHT LPSRAM
1/21February 2005
M40Z300
M40Z300W5V or 3V NVRAM Supervisor for Up to 8 LPSRAMs
FEATURES SUMMARY CONVERTS LOW POWER SRAM INTO
NVRAMs PRECISION POWER MONITORING AND
POWER SWITCHING CIRCUITRY AUTOMATIC WRITE-PROTECTION WHEN
VCC IS OUT-OF-TOLERANCE TWO-INPUT DECODER ALLOWS
CONTROL FOR UP TO 8 SRAMs (with 2
devices active in parallel) CHOICE OF SUPPLY VOLTAGES AND
POWER-FAIL DESELECT VOLTAGES: M40Z300:
VCC = 4.5V to 5.5V
THS = VSS: 4.5V ≤ VPFD ≤ 4.75V
THS = VOUT: 4.2V ≤ VPFD ≤ 4.5V M40Z300W:
VCC = 3.0V to 3.6V
THS = VSS: 2.8V ≤ VPFD ≤ 3.0V
VCC = 2.7V to 3.3V
THS = VOUT: 2.5 ≤ VPFD ≤ 2.7V RESET OUTPUT (RST) FOR POWER ON
RESET BATTERY LOW PIN (BL) LESS THAN 12ns CHIP ENABLE ACCESS
PROPAGATION DELAY (for 5.0V device) PACKAGING INCLUDES A 28-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately), OR A 16-LEAD SOIC SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY
M40Z300, M40Z300W
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 16-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. M40Z300 16-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. M40Z300W 16-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Two to Four Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 2. Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 8. Address-Decode Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Data Retention Lifetime Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Power-on Reset Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Battery Low Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 9. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Table 4. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 10.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 6. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 11.Power Down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 12.Power Up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 7. Power Down/Up Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 13.SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline.15
Table 8. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 15
Figure 14.SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline. . . . . . . . . . . . . . .16
Table 9. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data . . . . . . .16
Figure 15.SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline . . . . . . . . . . . . . .17
Table 10. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data . . . . . .17
Figure 16.SO16 – 16-lead Plastic Small Outline, 150 mils body width, Package Outline . . . . . . . .18
Table 11. SO16 – 16-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data 18
3/21
M40Z300, M40Z300W
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 12. Ordering Information Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 13. SNAPHAT® Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
M40Z300, M40Z300W
DESCRIPTIONThe M40Z300/W NVRAM SUPERVISOR is a self-
contained device which converts a standard low-
power SRAM into a non-volatile memory. A preci-
sion voltage reference and comparator monitors
the VCC input for an out-of-tolerance condition.
When an invalid VCC condition occurs, the condi-
tioned chip enable outputs (E1CON to E4CON) are
forced inactive to write-protect the stored data in
the SRAM. During a power failure, the SRAM is
switched from the VCC pin to the lithium cell within
the SNAPHAT® to provide the energy required for
data retention. On a subsequent power-up, the
SRAM remains write protected until a valid power
condition returns.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts for direct connection to a sep-
arate SNAPHAT housing containing the battery.
The SNAPHAT housing has gold plated pins
which mate with the sockets, ensuring reliable
connection. The housing is keyed to prevent im-
proper insertion. This unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process which greatly reduces the
board manufacturing process complexity of either
directly soldering or inserting a battery into a sol-
dered holder. Providing non-volatility becomes a
“SNAP.” The 16-pin SOIC provides battery pins for
an external user-supplied battery.
Insertion of the SNAPHAT housing after reflow
prevents potential battery damage due to the high
temperatures required for device surface-mount-
ing. The SNAPHAT housing is also keyed to pre-
vent reverse insertion.
The 28-pin SOIC and battery packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28-lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is “M4ZXX-BR00SH” (see Table
13., page 19).
Caution: Do not place the SNAPHAT battery topin conductive foam, as this will drain the lithium
button-cell battery.
Table 1. Signal NamesNote: For M40Z300W, B– must be connected to the negative bat-
tery terminal only (not to Pin 8, VSS).
5/21
M40Z300, M40Z300W
Figure 6. M40Z300W 16-pin SOIC ConnectionsNote: For M40Z300W, B– must be connected to the negative bat-
tery terminal only (not to Pin 8, VSS).
M40Z300, M40Z300W
Figure 7. Hardware HookupNote:1. If the second chip enable pin (E2) is unused, it should be tied to VOUT.
7/21
M40Z300, M40Z300W
OPERATIONThe M40Z300/W, as shown in Figure 7., page6,
can control up to four (eight, if placed in parallel)
standard low-power SRAMs. These SRAMs must
be configured to have the chip enable input dis-
able all other input signals. Most slow, low-power
SRAMs are configured like this, however many
fast SRAMs are not. During normal operating con-
ditions, the conditioned chip enable (E1CON to
E4CON) output pins follow the chip enable (E) input
pin with timing shown in Figure 8., page 8 and Ta-
ble 7., page 14. An internal switch connects VCC
to VOUT. This switch has a voltage drop of less
than 0.3V (IOUT1).
When VCC degrades during a power failure,
E1CON to E4CON are forced inactive independent
of E. In this situation, the SRAM is unconditionally
write protected as VCC falls below an out-of-toler-
ance threshold (VPFD). For the M40Z300 the pow-
er fail detection value associated with VPFD is
selected by the Threshold Select (THS) pin and is
shown in Table 6., page 12. For the M40Z300W,
the THS pin selects both the supply voltage and
VPFD (also shown in Table 6., page 12).
Note: In either case, THS pin must be connectedto either VSS or VOUT.
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time tWPT,
E1CON to E4CON are unconditionally driven high,
write protecting the SRAM. A power failure during
a WRITE cycle may corrupt data at the currently
addressed location, but does not jeopardize the
rest of the SRAM's contents. At voltages below
VPFD (min), the user can be assured the memory
will be write protected within the Write Protect
Time (tWPT) provided the VCC fall time exceeds tF
(see Figure 8., page8).
As VCC continues to degrade, the internal switch
disconnects VCC and connects the internal battery
to VOUT. This occurs at the switchover voltage
(VSO). Below the VSO, the battery provides a volt-
age VOHB to the SRAM and can supply current
IOUT2 (see Table 6., page 12).
When VCC rises above VSO, VOUT is switched
back to the supply voltage. Outputs E1CON to
E4CON are held inactive for tCER (120ms maxi-
mum) after the power supply has reached VPFD,
independent of the E input, to allow for processor
stabilization (see Figure 12., page 13).
Two to Four DecodeThe M40Z300/W includes a 2 input (A, B) decoder
which allows the control of up to 4 independent
SRAMs. The Truth Table for these inputs is shown
in Table 2.
Table 2. Truth Table
M40Z300, M40Z300W
Figure 8. Address-Decode TimeNote: During system design, compliance with the SRAM timing parameters must comprehend the propagation delay between E1CON -
E4CON.
Data Retention Lifetime CalculationMost low power SRAMs on the market today can
be used with the M40Z300/W NVRAM SUPERVI-
SOR. There are, however some criteria which
should be used in making the final choice of which
SRAM to use. The SRAM must be designed in a
way where the chip enable input disables all other
inputs to the SRAM. This allows inputs to the
M40Z300/W and SRAMs to be “Don't Care” once
VCC falls below VPFD(min). The SRAM should also
guarantee data retention down to VCC = 2.0V. The
chip enable access time must be sufficient to meet
the system needs with the chip enable propaga-
tion delays included. If the SRAM includes a sec-
ond chip enable pin (E2), this pin should be tied to
VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use.
The data retention current value of the SRAMs can
then be added to the IBAT value of the M40Z300/
W to determine the total current requirements for
data retention. The available battery capacity for
the SNAPHAT® of your choice can then be divided
by this current to determine the amount of data re-
tention available (see Table 13., page 19).
CAUTION: Take care to avoid inadvertent dis-charge through VOUT and E1CON - E4CON after
battery has been attached.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
Power-on Reset OutputAll microprocessors have a reset input which forc-
es them to a known state when starting. The
M40Z300/W has a reset output (RST) pin which is
guaranteed to be low within tWPT of VPFD (see 7).
This signal is an open drain configuration. An ap-
propriate pull-up resistor should be chosen to con-
trol the rise time. This signal will be valid for all
voltage conditions, even when VCC equals VSS.
Once VCC exceeds the power failure detect volt-
age VPFD, an internal timer keeps RST low for
tREC to allow the power supply to stabilize.
Battery Low PinThe M40Z300/W automatically performs battery
voltage monitoring upon power-up, and at factory-
programmed time intervals of at least 24 hours.
The Battery Low (BL) pin will be asserted if the
battery voltage is found to be less than approxi-
mately 2.5V. The BL pin will remain asserted until
completion of battery replacement and subse-
quent battery low monitoring tests, either during
the next power-up sequence or the next scheduled
24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below
2.5V and may not be able to maintain data integrity
in the SRAM. Data should be considered suspect,
and verified as correct. A fresh battery should be
installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT® top
should be replaced with valid VCC applied to the
device.
9/21
M40Z300, M40Z300WThe M40Z300/W only monitors the battery when a
nominal VCC is applied to the device. Thus appli-
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique. The BL pin is an open drain output and
an appropriate pull-up resistor to VCC should be
chosen to control the rise time.
VCC Noise And Negative Going TransientsICC transients, including those produced by output
switching, can produce voltage fluctuations, re-
sulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store en-
ergy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
9.) is recommended in order to provide the needed
filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on VCC that drive it to values
below VSS by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, STMicroelectronics recom-
mends connecting a schottky diode from VCC to
VSS (cathode connected to VCC, anode to VSS).
Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount.
Figure 9. Supply Voltage Protection
M40Z300, M40Z300W
MAXIMUM RATINGStressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 3. Absolute Maximum RatingsNote:1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds). For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
11/21
M40Z300, M40Z300W
DC AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 4. DC and AC Measurement ConditionsNote: Output High Z is defined as the point where data is no longer driven.
Table 5. CapacitanceNote:1. Sampled only, not 100% tested. At 25°C, f = 1MHz. Outputs deselected.
