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M40Z111MH6-M40Z111WMH6-M40Z111WMH6TR
NVRAM CONTROLLER FOR UP TO TWO LPSRAM
1/15May 2002
M40Z111
M40Z111W OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs
FEATURES SUMMARY CONVERT LOW POWER SRAMs INTO
NVRAMs PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY AUTOMATIC WRITE-PROTECTION WHEN
VCCIS OUT-OF-TOLERANCE CHOICE OF SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES: M40Z111: VCC =4.5to 5.5V
THS= VSS;4.5≤ VPFD≤ 4.75V
THS= VOUT;4.2≤ VPFD≤ 4.5V M40Z111W: VCC= 3.0to 3.6V
THS= VSS;2.8≤ VPFD≤ 3.0V
VCC= 2.7to 3.3V
THS= VOUT;2.5≤ VPFD≤ 2.7V LESS THAN 15ns CHIP ENABLE ACCESS
PROPAGATION DELAY (for 5.0V device) PACKAGINGINCLUDESA 28-LEAD SOIC and
SNAPHAT® TOP(tobe ordered separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION FORA SNAPHAT TOP WHICH
CONTAINS THE BATTERY
M40Z111, M40Z111W2/15
TABLE OF CONTENTS
SUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... .....3Logic Diagram (Figure 2.). ...... ....... ...... ....... ...... ....... ...... ...... .....3
Signal Names (Table1.).. ...... ....... ...... ....... ...... ....... ...... ...... .....3
SOIC28 Connections (Figure3.).. ....... ...... ....... ...... ....... ...... ...... .....3
Hardware Hookup (Figure 4.) .... ....... ...... ....... ...... ....... ...... ...... .....4
MAXIMUM RATING... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....4Absolute Maximum Ratings (Table2.) .... ...... ....... ...... ....... ...... ...... .....4
AND AC PARAMETERS.. ...... ....... ...... ....... ...... ....... ...... ...... .....5 and AC Measurement Conditions (Table3.)... ....... ...... ....... ...... ...... .....5 Testing Load Circuit (Figure 5.)....... ...... ....... ...... ....... ...... ...... .....5
Capacitance (Table4.)... ...... ....... ...... ....... ...... ....... ...... ...... .....5 Characteristics (Table5.) .... ....... ...... ....... ...... ....... ...... ...... .....6
OPERATION. ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....7Data Retention Lifetime Calculation ...... ...... ....... ...... ....... ...... ...... .....7
Power Down Timing (Figure 6.)... ....... ...... ....... ...... ....... ...... ...... .....8
Power Up Timing (Figure 7.) ..... ....... ...... ....... ...... ....... ...... ...... .....8
Power Down/Up AC Characteristics (Table 6.) .... ....... ...... ....... ...... ...... .....9
VCC Noise And Negative Going Transients. ...... ....... ...... ....... ...... ...... .....9
Supply Voltage Protection (Figure8.) ..... ...... ....... ...... ....... ...... ...... .....9
PART NUMBERING.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10Battery Table (Table 8.)... ...... ....... ...... ....... ...... ....... ...... ...... ....10
PACKAGE MECHANICAL INFORMATION... ...... ....... ...... ....... ...... ...... ....11
REVISION HISTORY.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....14
3/15
M40Z111, M40Z111W
SUMMARY DESCRIPTIONThe M40Z111/W NVRAM SUPERVISORisa self-
contained device which convertsa standard low-
power SRAM intoa non-volatile memory. precision voltage reference and comparator
monitors the VCC inputforan out-of-tolerance con-
dition.
Whenan invalid VCC condition occurs, the condi-
tioned chip enable (ECON) outputis forced inactive write-protect the stored datain the SRAM.
Duringa power failure, the SRAMis switched from
the VCC pin to the lithium cell within the
SNAPHAT®to provide the energy required for
data retention. Ona subsequent power-up, the
SRAM remains write protected untila valid power
condition returns.
The 28-pin, 330mil SOIC provides sockets with
gold plated contactsat both ends for direct con-
nectiontoa separate SNAPHAT housing contain-
ing the battery. The unique design allows the
SNAPHAT battery packageto be mountedon top the SOIC package after the completionof the
surface mount process.
Insertionof the SNAPHAT housing after reflow
prevents potential battery damage dueto the high
temperatures required for device surface-mount-
ing. The SNAPHAT housingis keyedto prevent
reverse insertion.
The SOIC and battery packages are shipped sep-
aratelyin plastic anti-static tubesorin Tape& Reel
form. For the 28-lead SOIC, the battery package
(e.g., SNAPHAT) part number is “M4Z28-
BR00SH” or “M4Z32-BR00SH” (See Table 8,
page 10).
M40Z111, M40Z111W4/15
Stressing the deviceabove therating listedinthe
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operationof the deviceat
theseor any other conditions above those indicat-in the Operating sectionsof this specificationis
not implied. Exposureto Absolute Maximum Rat-
ing conditionsfor extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table2. Absolute Maximum RatingsNote:1. Reflowat peak temperatureof 215°Cto 225°Cfor<60 seconds (total thermal budgetnotto exceed 180°Cfor between90to120
seconds).
CAUTION: Negative undershoots below –0.3Varenot allowedonanypin whileinthe Battery Back-up mode.
CAUTION:Do NOT wave solder SOICto avoid damaging SNAPHAT sockets.
5/15
M40Z111, M40Z111W AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristicsof the device. The parametersin
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listedin the relevant tables. De-
signers should check that the operating conditions their projects match the measurement condi-
tions when using the quoted parameters.
Table3. DC and AC Measurement ConditionsNote: Notethat Output Hi-Zis definedasthe point where dataisno longer driven.
Table4. CapacitanceNote:1. Effective capacitance measured with power supplyat5V (M40Z111)or 3.3V (M40Z111W); sampled only,not 100% tested.At 25°C,f= 1MHz. Outputs deselected
M40Z111, M40Z111W6/15
Table5. DC CharacteristicsNote:1. Validfor Ambient Operating Temperature:TA=–40to 85°C; VCC=4.5to 5.5Vor2.7to 3.6V (except where noted). Outputs deselected.
7/15
M40Z111, M40Z111W
OPERATIONThe M40Z111/W,as shownin Figure4, page4,
can controlupto two standard low-power SRAMs.
These SRAMs must be configuredto have the
chip enable input disableall other input signals.
Most slow, low-power SRAMs are configured like
this, however many fast SRAMs are not. During
normal operating conditions, the conditioned chip
enable (ECON) output pin follows the chip enable
(E) input pin with timing shownin Table6, page9. internal switch connects VCCto VOUT.This
switch hasa voltage drop of less than 0.3V
(IOUT1).
When VCC degrades duringa power failure, ECON forced inactive independentofE.In this situa-
tion, the SRAMis unconditionally write protected VCC falls below an out-of-tolerance threshold
(VPFD). The power fail detection value associated
with VPFDis selectedby the THS pin andis shown Table5, page6.
Note: The THS pin must be connectedto either
VSSor VOUT. chip enable accessisin progress duringa power
fail detection, that memory cycle continuesto com-
pletion before the memoryis write protected.If the
memory cycleis not terminated within time tWP,
ECONis unconditionally driven high, write protect-
ing the SRAM. power failure duringa write cycle may corrupt
dataat the currently addressed location, but does
not jeopardize the restof the SRAM's contents.At
voltages below VPFD (min), the user can be as-
sured the memory willbe write protected provided
the VCC fall time exceedstF. VCC continuesto degrade, the internal switch
disconnects VCC and connects the internal battery VOUT. This occursat the switchover voltage
(VSO). Below the VSO, the battery providesa volt-
age VOHBto the SRAM and can supply current
IOUT2 (see Table5, page 6). When VCC rises
above VSO,VOUTis switched backto the supply
voltage. Output ECONis held inactive for tER
(200ms maximum) after the power supply has
reached VPFD, independentof theE input,to allow
for processor stabilization (see Figure7, page 8).
Data Retention Lifetime CalculationMost low power SRAMson the market today can used with the M40Z111/W NVRAM SUPERVI-
SOR. There are, however some criteria which
shouldbe usedin making the final choiceof which
SRAMto use. The SRAM mustbe designedina
way where the chip enable input disablesall other
inputsto the SRAM. This allows inputsto the
M40Z111/W and SRAMsto be “Don't Care” once
VCC falls below VPFD (min). The SRAM should
also guarantee data retention downto VCC =2.0V.
The chip enable access time mustbe sufficientto
meet the system needs with the chip enable prop-
agation delays included.If the SRAM includesa
second chip enable pin (E2), this pin should be
tiedto VOUT.If data retention lifetimeisa critical
parameter for the system,itis importantto review
the data retention current specifications for the
particular SRAMs being evaluated. Most SRAMs
specifya data retention currentat 3.0V.
Manufacturers generally specifya typical condi-
tionfor room temperature along witha worst case
condition (generallyat elevated temperatures).
The system level requirements will determine the
choiceof which valueto use. The data retention
current valueof the SRAMs can thenbe addedto
the ICCDR valueof the M40Z111/Wto determine
the total current requirementsfor data retention.
The available battery capacity for the SNAPHAT® your choice can thenbe dividedby this current determine the amountof data retention avail-
able (see Table8, page 10). For more information Battery Storage Life referto the Application
Note AN1012.
M40Z111, M40Z111W8/15
