M40SZ100WMQ6F ,3 V NVRAM supervisor for LPSRAMBlock diagram . . . . 6Figure 4. Hardware hookup . 7Figure 5. Power-down timing ..
M40SZ100WMQ6F ,3 V NVRAM supervisor for LPSRAMFeaturesSRAM. During a power failure, the SRAM is switched from the V pin to the external battery C ..
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M40Z111WMH6 ,NVRAM CONTROLLER FOR UP TO TWO LPSRAMLogic Diagram(Figure 2.) . ...... ....... ...... ....... ...... ....... ...... ...... .....3Signal ..
M40Z111WMH6TR ,NVRAM CONTROLLER FOR UP TO TWO LPSRAMFEATURES SUMMARY■ CONVERT LOW POWER SRAMs INTO Figure 1. 28-pin SOIC PackageNVRAMs■ PRECISION POWER ..
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M40SZ100WMQ6F
3 V NVRAM supervisor for LPSRAM
December 2013 DocID007528 Rev 4 1/20
M40SZ100W3 V NVRAM supervisor for LPSRAM
Datasheet - production data
Features Convert low power SRAMs into NVRAMs 3 V operating voltage Precision power monitoring and power
switching circuitry Automatic write-protection when VCC is out-of-
tolerance Choice of supply voltage and power-fail
deselect voltage:
–VCC = 2.7 to 3.6 V; 2.55 V VPFD 2.70 V Reset output (RST) for power on reset 1.25 V reference (for PFI/PFO) Less than 15 ns chip enable access
propagation delay Battery low pin (BL) RoHS compliant Lead-free second level interconnect
DescriptionThe M40SZ100W NVRAM controller is a self-
contained device which converts a standard low-
power SRAM into a non-volatile memory. A
precision voltage reference and comparator
monitors the VCC input for an out-of-tolerance
condition.
When an invalid VCC condition occurs, the
conditioned chip enable output (ECON) is forced
inactive to write protect the stored data in the
SRAM. During a power failure, the SRAM is
switched from the VCC pin to the external battery
to provide the energy required for data retention.
On a subsequent power-up, the SRAM remains
write-protected until a valid power condition
returns.
Contents M40SZ100W2/20 DocID007528 Rev 4
Contents Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1 Data retention lifetime calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Power-on reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Reset input (RSTIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Battery low pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DocID007528 Rev 4 3/20
M40SZ100W List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 2. Power-down/up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 3. Reset AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 5. DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 6. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 7. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 8. SO16 – 16-lead plastic small outline package mechanical data. . . . . . . . . . . . . . . . . . . . .17
Table 9. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 10. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
List of figures M40SZ100W
4/20 DocID007528 Rev 4
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 4. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 5. Power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 6. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 7. RSTIN timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 8. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 9. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 10. AC testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 11. SO16 – 16-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DocID007528 Rev 4 5/20
M40SZ100W Device overview
1 Device overview
Device overview M40SZ100W
6/20 DocID007528 Rev 4
DocID007528 Rev 4 7/20
M40SZ100W Device overview
Operation M40SZ100W
8/20 DocID007528 Rev 4
2 Operation
The M40SZ100W, as shown in Figure 4 on page 7, can control one (two, if placed in
parallel) standard low-power SRAM. This SRAM must be configured to have the chip enable
input disable all other input signals. Most slow, low-power SRAMs are configured like this,
however many fast SRAMs are not. During normal operating conditions, the conditioned
chip enable (ECON) output pin follows the chip enable (E) input pin with timing shown in
Table 2 on page 10. An internal switch connects VCC to VOUT. This switch has a voltage
drop of less than 0.3 V (IOUT1).
When VCC degrades during a power failure, ECON is forced inactive independent of E. In
this situation, the SRAM is unconditionally write protected as VCC falls below an out-of-
tolerance threshold (VPFD). For the M40SZ100W the power fail detection value associated
with VPFD is shown in Table 7 on page 16.
If chip enable access is in progress during a power fail detection, that memory cycle
continues to completion before the memory is write protected. If the memory cycle is not
terminated within time tWPT, ECON is unconditionally driven high, write protecting the SRAM.
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the SRAM's contents. At voltages below VPFD (min), the
user can be assured the memory will be write protected within the Write Protect Time (tWPT)
provided the VCC fall time does not exceed tF (see Table 2 on page 10).
As VCC continues to degrade, the internal switch disconnects VCC and connects the internal
battery to VOUT . This occurs at the switchover voltage (VSO). Below the VSO, the battery
provides a voltage VOHB to the SRAM and can supply current IOUT2 (see Table 7 on
page 16).
When VCC rises above VSO, VOUT is switched back to the supply voltage. Output ECON is
held inactive for tCER (120 ms maximum) after the power supply has reached VPFD,
independent of the E input, to allow for processor stabilization (see Figure 6 on page 10).
2.1 Data retention lifetime calculation
Most low power SRAMs on the market today can be used with the M40SZ100W NVRAM
controller. There are, however some criteria which should be used in making the final choice
of which SRAM to use. The SRAM must be designed in a way where the chip enable input
disables all other inputs to the SRAM. This allows inputs to the M40SZ100W and SRAMs to
be “Don't care” once VCC falls below VPFD(min) (see Figure 5 on page 9). The SRAM should
also guarantee data retention down to VCC = 2.0 V. The chip enable access time must be
sufficient to meet the system needs with the chip enable propagation delays included.
If data retention lifetime is a critical parameter for the system, it is important to review the
data retention current specifications for the particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0 V. Manufacturers generally specify a typical condition
for room temperature along with a worst case condition (generally at elevated
temperatures). The system level requirements will determine the choice of which value to
use. The data retention current value of the SRAMs can then be added to the ICCDR value of
the M40SZ100W to determine the total current requirements for data retention.
Caution: Take care to avoid inadvertent discharge through VOUT and ECON after battery has been
attached.
DocID007528 Rev 4 9/20
M40SZ100W Operation
For a further more detailed review of lifetime calculations, please see application note
AN1012.
Operation M40SZ100W
