M36W0T7050T0ZAQT ,128Mbit (Multiple Bank, 8Mb x 16, Burst) Flash Memory 32Mbit (2M x16) PSRAM, Dual Supply, Multi-Chip PackageAbsolute Maximum Ratings . . . . . . . 112/18M36W0T7050T0, M36W0T7050B0DC AND AC PARAMETERS ..
M36W432BG70ZA6T ,32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory ProductFEATURES USING TWO CHIP ENABLE INPUTS–V = V = 2.7V to 3.3VDDS DDQF–V = 12V for Fast Program (option ..
M36W432TG70ZA6T ,32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory ProductAbsolute Maximum Ratings 12DC AND AC PARAMETERS . 13Table 4. Operating and AC Measurement ..
M37161EFFP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37161EFFP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M3720-4 , 1 KEY 1 SOUND
M54678FP , 2-PHASE STEPPER MOTOR DRIVER
M54678FP , 2-PHASE STEPPER MOTOR DRIVER
M5480B7 ,LED DISPLAY DRIVERSblock diagram is shown in Figure 3. The output2 digit alphanumeric displays with minimal inter- cur ..
M5481B7 ,LED DISPLAY DRIVERSFEATURES SUMMARY■ 2 DIGIT LED DRIVER (14 segments) through a variable resistor connected either to ..
M5482B7 ,LED Display Driverblock diagram is shown in Figure 3. The outputSerial data transfer from the data source to the dis- ..
M54914FP , F2F MAGNETIC STRIPE ENCORDING CARD READER
M36W0T7050T0ZAQT
128Mbit (Multiple Bank, 8Mb x 16, Burst) Flash Memory 32Mbit (2M x16) PSRAM, Dual Supply, Multi-Chip Package
1/18December 2004
M36W0T7050T0
M36W0T7050B0128Mbit (Multiple Bank, 8Mb x 16, Burst) Flash Memory
32Mbit (2M x16) PSRAM, Dual Supply, Multi-Chip Package
FEATURES SUMMARYMULTI-CHIP PACKAGE1 die of 128 Mbit (8Mb x16, Multiple Bank,
Burst) Flash Memory1 die of 32 Mbit (2Mb x16) Pseudo SRAMSUPPLY VOLTAGE
–VDDF = 1.7 to 2V
–VDDP = VDDQ = 2.7 to 3.3V
–VPP = 12V for fast Program (optional)ELECTRONIC SIGNATUREManufacturer Code: 20hDevice Code (Top Flash Configuration)
M36W0T7050T0: 881EhDevice Code (Bottom Flash
Configuration) M36W0T7050B0: 881FhPACKAGECompliant with Lead-Free Soldering
ProcessesLead-Free Versions
FLASH MEMORYSYNCHRONOUS / ASYNCHRONOUS READSynchronous Burst Read mode: 40MHzAsynchronous/ Synchronous Page Read
modeRandom Access: 70nsSYNCHRONOUS BURST READ SUSPENDPROGRAMMING TIME8µs by Word typical for Fast Factory
ProgramDouble/Quadruple Word Program optionEnhanced Factory Program optionsMEMORY BLOCKSMultiple Bank Memory Array: 4 Mbit
BanksParameter Blocks (Top or Bottom
location) DUAL OPERATIONSprogram/erase in one Bank while read in
othersNo delay between read and write
operations
M36W0T7050T0, M36W0T7050B0
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1.Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2.Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1.Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3.TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SIGNAL DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Address Inputs (A0-A22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Flash Chip Enable (EF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Flash Output Enable (GF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Flash Latch Enable (LF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Flash Clock (KF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Flash Wait (WAITF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PSRAM Chip Enable (E1P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PSRAM Chip Enable (E2P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PSRAM Output Enable (GP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PSRAM Write Enable (WP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
PSRAM Upper Byte Enable (UBP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
PSRAM Lower Byte Enable (LBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VDDF Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VDDP Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 4.Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 2.Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
FLASH MEMORY COMPONENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PSRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Table 3.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3/18
M36W0T7050T0, M36W0T7050B0
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 4.Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 5.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 6.AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 5.Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 6.Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 7.Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 8.PSRAM DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 7. Stacked TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Bottom View Outline . . . .15
Table 9.Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data. . . . .15
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 10.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 11.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
M36W0T7050T0, M36W0T7050B0
SUMMARY DESCRIPTION
Table 1. Signal NamesNote:1.A22-A21 are not connected to the PSRAM component.
5/18
M36W0T7050T0, M36W0T7050B0
M36W0T7050T0, M36W0T7050B0
SIGNAL DESCRIPTIONSSee Figure 2.,Logic Diagram and Table 1.,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A22).Addresses A0-A20
are common inputs for the Flash Memory and the
PSRAM components. The other lines (A21-A22)
are inputs for the Flash Memory component only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the Flash
memory Program/Erase Controller or they select
the cells to access in the PSRAM.
The Flash memory component is accessed
through the Chip Enable signal (EF) and through
the Write Enable (WF) signal, while the PSRAM is
accessed through two Chip Enable signals (E1P
and E2P) and the Write Enable signal (WP).
Data Input/Output (DQ0-DQ15). In the Flash
memory component the Data I/O output the data
stored at the selected address during a Bus Read
operation or input a command or the data to be
programmed during a Write Bus operation.
In the PSRAM component, the Upper Byte Data
Inputs/Outputs, DQ8-DQ15, carry the data to or
from the upper part of the selected address during
a Write or Read operation, when Upper Byte En-
able (UBP) is driven Low.
The Lower Byte Data Inputs/Outputs, DQ0-DQ7,
carry the data to or from the lower part of the se-
lected address during a Write or Read operation,
when Lower Byte Enable (LBP) is driven Low
Flash Chip Enable (EF). The Chip Enable input
activates the memory control logic, input buffers,
decoders and sense amplifiers. When Chip En-
able is Low, VIL, and Reset is High, VIH, the device
is in active mode. When Chip Enable is at VIH the
Flash memory is deselected, the outputs are high
impedance and the power consumption is reduced
to the standby level.
Flash Output Enable (GF). The Output Enable
input controls data output during Flash memory
Bus Read operations.
Flash Write Enable (WF). The Write Enable
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is Low, VIL,
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, VIH, Lock-Down is
disabled and the Locked-Down blocks can be
locked or unlocked. (See the Lock Status Table in
the M30W0T7000x0 datasheet).
Flash Reset (RPF). The Reset input provides a
hardware reset of the memory. When Reset is at
VIL, the memory is in Reset mode: the outputs are
high impedance and the current consumption is
reduced to the Reset Supply Current IDD2. Refer to
Table 6.,Flash Memory DC Characteristics - Cur-
rents, for the value of IDD2. After Reset all blocks
are in the Locked state and the Configuration Reg-
ister is reset. When Reset is at VIH, the device is in
normal operation. Exiting Reset mode the device
enters Asynchronous Read mode, but a negative
transition of Chip Enable or Latch Enable is re-
quired to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to VRPH
(refer to Table 7.,Flash Memory DC Characteris-
tics - Voltages).
Flash Latch Enable (LF).Latch Enable latches
the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, VIL,
and it is inhibited when Latch Enable is High, VIH.
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
supported.
Flash Clock (KF).The Clock input synchronizes
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, accord-
ing to the configuration settings) when Latch En-
able is at VIL. Clock is don't care during
Asynchronous Read and in write operations.
Flash Wait (WAITF).WAIT is a Flash output sig-
nal used during Synchronous Read to indicate
whether the data on the output bus are valid. This
output is high impedance when Flash Chip Enable
is at VIH or Flash Reset is at VIL. It can be config-
ured to be active during the wait cycle or one clock
cycle in advance. The WAITF signal is not gated
by Output Enable.
PSRAM Chip Enable (E1P).When asserted
(Low), the Chip Enable, E1P, activates the memo-
ry state machine, address buffers and decoders,
allowing Read and Write operations to be per-
formed. When de-asserted (High), all other pins
are ignored, and the device is put, automatically, in
low-power Standby mode.
PSRAM Chip Enable (E2P).The Chip Enable,
E2P, puts the device in Power-down mode (Deep
Power-Down, PAR and Standby) when it isdriven
Low. One of these, Deep Power-Down mode, is
the lowest power mode.
PSRAM Output Enable (GP).The Output En-
able, GP, provides a high speed tri-state control,
7/18
M36W0T7050T0, M36W0T7050B0allowing fast read/write cycles to be achieved with
the common I/O data bus.
PSRAM Write Enable (WP).The Write Enable,
WP, controls the Bus Write operation of the mem-
ory.
PSRAM Upper Byte Enable (UBP).The Upper
Byte Enable, UBP, gates the data on the Upper
Byte Data Inputs/Outputs (DQ8-DQ15) to or from
the upper part of the selected address during a
Write or Read operation.
PSRAM Lower Byte Enable (LBP).The Lower
Byte Enable, LBP, gates the data on the Lower
Byte Data Inputs/Outputs (DQ0-DQ7) to or from
the lower part of the selected address during a
Write or Read operation.
VDDF Supply Voltage.VDDF provides the power
supply to the internal cores of the Flash memory
component. It is the main power supply for all
Flash operations (Read, Program and Erase).
VDDP Supply Voltage. The VDDP Supply Volt-
age supplies the power for all PSRAM operations
(Read, Write, etc.) and for driving the refresh logic,
even when the device is not being accessed.
VDDQ Supply Voltage. VDDQ provides the power
supply for the Flash Memory I/O pins. This allows
all Outputs to be powered independently of the
Flash Memory core power supply, VDDF.
VPPF Program Supply Voltage. VPPF is both a
Flash control input and a Flash power supply pin.
The two functions are selected by the voltage
range applied to the pin.
If VPPF is kept in a low voltage range (0V to VDDQ)
VPPF is seen as a control input. In this case a volt-
age lower than VPPLKF gives an absolute protec-
tion against Program or Erase, while VPPF > VPP1F
enables these functions (see Tables 6 and 7, DC
Characteristics for the relevant values). VPPF is
only sampled at the beginning of a Program or
Erase; a change in its value after the operation has
started does not have any effect and Program or
Erase operations continue.
If VPPF is in the range of VPPHF it acts as a power
supply pin. In this condition VPPF must be stable
until the Program/Erase algorithm is completed.
VSS Ground. VSS is the common ground refer-
ence for all voltage measurements in the Flash
(core and I/O Buffers) and PSRAM chips.
Note: Each Flash memory device in a system
should have their supply voltage (VDDF) and
the program supply voltage VPPF decoupled
with a 0.1µF ceramic capacitor close to the pin
(high frequency, inherently low inductance ca-
pacitors should be as close as possible to the
package). See Figure 6.,AC Measurement
Load Circuit. The PCB track widths should be
sufficient to carry the required VPPF program
and erase currents.
M36W0T7050T0, M36W0T7050B0
FUNCTIONAL DESCRIPTIONThe PSRAM and Flash memory components have
separate power supplies but share the same
grounds. They are distinguished by three Chip En-
able inputs: EF for the Flash memory and E1P and
E2P for the PSRAM.
Recommended operating conditions do not allow
more than one device to be active at a time. The
most common example is simultaneous read oper-
ations in the Flash memory and the PSRAM which
would result in a data bus contention. Therefore it
is recommended to put the other device in the high
impedance state when reading the selected de-
vice.
9/18
M36W0T7050T0, M36W0T7050B0
Table 2. Main Operating Modes Note:1.X = Don't care.LF can be tied to VIH if the valid address has been previously latched. Depends on GF.WAIT signal polarity is configured using the Set Configuration Register command. See the M30W0T7000x0 datasheet for details.
