M36DR432A120ZA6C ,32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory ProductFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Packages–V =V =1.65V to 2.2VDDF DDS–V = 12V for Fast Pro ..
M36DR432AD10ZA6T ,32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory ProductBlock Diagram 10Table 2. Main Operation Modes . . . 11FLASH MEMORY COMPONENT . . ..
M36L0R7050B0ZAQ ,128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip PackageAbsolute Maximum Ratings . . . . . . . 11DC AND AC PARAMETERS . 12Table 5. Operating and ..
M36L0R7060T1ZAQF , 128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package
M36L0R8060T1ZAQE , 256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
M36L0T7050B2ZAQF , 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package
M54585KP , 8-UNIT 500mA DARLINGTON TRANSISTOR-ARRAY WITH CLAMP DIODE
M54587FP , 8-UNIT 500mA DARLINGTON TRANSISTOR ARRAY WITH CLAMP DIODE
M54587FP , 8-UNIT 500mA DARLINGTON TRANSISTOR ARRAY WITH CLAMP DIODE
M54641L , Bi-DIRECTIONAL MOTOR DRIVER WITH BRAKE FUNCTION
M54641L , Bi-DIRECTIONAL MOTOR DRIVER WITH BRAKE FUNCTION
M54678FP , 2-PHASE STEPPER MOTOR DRIVER
M36DR432A100ZA6C-M36DR432A120ZA6C
32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product
1/46November 2001
M36DR432A
M36DR432B Mbit (2Mb x16, Dual Bank, Page) Flash Memory
and4 Mbit (256K x16) SRAM, Multiple Memory Product
FEATURES SUMMARY SUPPLY VOLTAGE
–VDDF =VDDS =1.65Vto 2.2V
–VPPF= 12V for Fast Program (optional) ACCESS TIME: 100,120ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M36DR432A: 00A0h Bottom Device Code, M36DR432B: 00A1h
FLASH MEMORY 32 Mbit (2Mb x16) BOOT BLOCK Parameter Blocks (Topor Bottom Location) PROGRAMMING TIME 10μs typical Double Word Programming Option ASYNCRONOUS PAGE MODE READ Page width:4 Word Page Mode Access Time: 35ns DUAL BANK OPERATION Read within one Bank while Programor
Erase within the other No Delay between Read and Write
Operations BLOCK PROTECTION ON ALL BLOCKS
–WPFfor Block Locking COMMON FLASH INTERFACE 64bit Security Code
SRAM4 Mbit (256Kx16 bit) LOW VDDS DATA RETENTION: 1V POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
M36DR432A, M36DR432B2/46
DESCRIPTION
Table1. Signal Names
3/46
M36DR432A, M36DR432B
M36DR432A, M36DR432B4/46
Table2. Absolute Maximum Ratings(1)Note:1. Exceptforthe rating "Operating Temperature Range", stresses above those listedinthe Table "Absolute Maximum Ratings" may
cause permanent damagetothe device. Theseare stress ratings only and operationofthe deviceat theseorany otherconditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposureto Absolute Maximum Rating condi-
tions forextended periods may affect device reliability.Referalsotothe STMicroelectronics SUREProgramand otherrelevant qual-
ity documents. Minimum voltage may undershootto –2V during transition andfor less than 20ns. Dependson range. VDD =VDDS =VDDF.
5/46
M36DR432A, M36DR432B
SIGNAL DESCRIPTIONSSee Figure2 and Table1.
Address Inputs (A0-A17). Addresses A0to A17
are common inputs for the Flash chip and the
SRAM chip. The address inputs for the Flash
memory are latched duringa write operation on
the falling edgeof the Flash Chip Enable (EF)or
Write Enable (WF), while address inputs for the
SRAM array are latched duringa write operation the falling edgeof the SRAM Chip Enable lines
(E1Sor E2S)or Write Enable (WS).
Address Inputs (A18-A20). Address A18to A20
are address inputs for the Flash chip. They are
latched duringa write operationon the falling edge Flash Chip Enable (EF)or Write Enable (WF).
Data Input/Outputs (DQ0-DQ15). The input is
datato be programmedin the Flashor SRAM
memory arrayora commandto be writtento the
C.I.of the Flash chip. Both are latchedon the ris-
ing edgeof Flash Chip Enable (EF)orWrite En-
able (WF) and, SRAM Chip Enable lines (E1Sor
E2S)or Write Enable (WS). The outputis data
from the Flash memoryor SRAM array, the Elec-
tronic Signature Manufactureror Device codesor
the Status register Data Pollingbit DQ7, the Tog-
gle Bits DQ6 and DQ2, the Errorbit DQ5or the
Erase Timer bit DQ3. Outputs are valid when
Flash Chip Enable (EF) and Output Enable (GF)or
SRAM Chip Enable lines (E1Sor E2S) and Output
Enable (GS) are active. The outputis high imped-
ance when the both the Flash chip and the SRAM
chip are deselectedor the outputs are disabled
and when Reset (RPF)isata VIL.
Flash Chip Enable (EF). The Chip Enable input
for Flash activates the memory control logic, input
buffers, decoders and sense amplifiers. EFat VIH
deselects the memory and reduces the power con-
sumptionto the standby level and outputdo Hi-Z. canalsobeusedto control writingto the com-
mand register andto the Flash memory array,
while WF remainsat VIL.Itisnot allowedto set EF VIL,E1Sat VIL and E2Sat VIHat the same time.
Flash Write Enable (WF). The Write Enable in-
put controls writingto the Command Registerof
the Flash chip and Address/Data latches. Data are
latchedon the rising edgeof WF.
Flash Output Enable (GF). The Output Enable
gates the outputs through the data buffers during read operationof the Flash chip. When GF and are High the outputs are High impedance.
Flash Reset/Power Down Input (RPF). The RPF
input provides hardware resetof the memory
(without affecting the Configuration Register sta-
tus), and/or Power Down functions, dependingon
the Configuration Register status. Reset/Power
Downof the memoryis achievedby pulling RPFto
VILforat least tPLPH. When the reset pulseis giv-
en,if the memoryisin Read, Erase Suspend Read Standby,it will output new valid datain tPHQ7V1
after the rising edgeof RPF.Ifthe memoryisin
Eraseor Program modes, the operation will be
aborted and the reset recovery will takea maxi-
mumof tPLQ7V. The memory will recover from
Power Down (when enabled)in tPHQ7V2 after the
rising edgeof RPF. See Tables1,26 and Figure
Flash Write Protect (WPF). Write Protectis an
inputto protector unprotect the two lockable pa-
rameter blocksof the Flash memory. When WPFat VIL, the lockable blocks are protected. Pro-
gram or erase operations are not achievable.
When WPFisat VIH, the lockable blocks are un-
protected and they canbe programmedor erased
(referto Table 17).
SRAM Chip Enable (E1S,E2S). The Chip En-
able inputsfor SRAM activate the memory control
logic, input buffers and decoders. E1Sat VIHor
E2Sat VIL deselects the memory and reduces the
power consumptionto the standby level. E1S and
E2S can also be usedto control writingto the
SRAM memory array, while WS remainsat VIL.It not allowedto set EFat VIL,E1Sat VIL and E2S VIHat the same time.
SRAM WriteEnable(WS). The Write Enablein-
put controls writingto the SRAM memory array.is active low.
SRAM Output Enable (GS). The Output Enable
gates the outputs through the data buffers during read operationof the SRAM chip. GSis active
low.
SRAM Upper Byte Enable (UBS). Enable the
upper bytesfor SRAM (DQ8-DQ15). UBSis active
low.
SRAM Lower Byte Enable (LBS). Enable the
lower bytes for SRAM (DQ0-DQ7). LBSis active
low.
VDDFSupply Voltage (1.65Vto 2.2V). Flash memo- power supplyforall operations (Read, Program and
Erase).
VPPF Programming Voltage (11.4V to 12.6V).Usedto provide high voltage for fast factory pro-
gramming. High voltageon VPPF pinis requiredto
use the Double Word Program instruction.Itis
also possibleto perform word programor erasein-
structions with VPPF pin grounded.
VDDS Supply Voltage (1.65Vto 2.2V). SRAM
power supply forall operations (Read, Program).
VSSF and VSSS Ground. VSSF and VSSS are the
reference for all voltage measurements respec-
tivelyin the Flash and SRAM chips.
M36DR432A, M36DR432B6/46
Table3. Main Operation ModesNote:X= VILor VIH,VPPFH=12V± 5%. IfUBSand LBSare tied togetherthebusisat16bit.Foran8bitbus configurationuse UBS and LBS separately.
7/46
M36DR432A, M36DR432B
FLASH MEMORY COMPONENT
OrganizationThe Flash Chipis organizedas 2Mb x16 bits. A0-
A20 are the address lines, DQ0-DQ15 are the
Data Input/Output. Memory controlis providedby
Chip Enable EF, Output Enable GF and Write En-
able WF inputs.
Reset RPFis usedto resetall the memory circuitry
andto set the chipin power down modeif this
functionis enabledbya proper settingof the Con-
figuration Register. Erase and Program operations
are controlledbyan internal Program/Erase Con-
troller (P/E.C.). Status Register data output on
DQ7 providesa Data Polling signal, DQ6 and DQ2
provide Toggle signals and DQ5 provides errorbit indicate the stateof the P/E.C operations.
Memory BlocksThe device features asymmetrically blocked archi-
tecture. The Flash Chip hasan arrayof71 blocks
andis divided into two banksA andB, providing
Dual Bank operations. While programming or
erasingin BankA, read operations are possible
into BankBor vice versa. The memory also fea-
tures an erase suspend allowingto reador pro-
gramin another block within the same bank. Once
suspended the erase can be resumed. The Bank
Size and Sectorization are summarizedin Table4.
Parameter Blocks are locatedat the topof the
memory address spacefor the Top version, andat
the bottom for the Bottom version. The memory
maps are shownin Tables5,6,7 and8.
The Program and Erase operations are managed
automatically by the P/E.C. Block protection
against Programor Erase provides additional data
security.All blocks are protectedat Power Up.In-
structions are providedto protector unprotect any
blockin the application.A second register locks
the protection status while WPFis low (see Block
Locking description). The Reset command does
not affect the configurationof unprotected blocks
and the Configuration Register status.
Device OperationsThe following operations canbe performed using
the appropriate bus cycles: Read Array (Random,
and Page Modes), Write command, Output Dis-
able, Standby, Reset/Power Down and Block
Locking. See Table9.
Read. Read operations are usedto output the
contentsof the Memory Array, the Electronic Sig-
nature, the Status Register, the CFI, the Block
Protection Status or the Configuration Register
status. Read operationof the memory arrayis per-
formedin asynchronous page mode, that provides
fast access time. Datais internally read and storeda page buffer. The page hasa sizeof4 words
andis addressedby A0-A1 address inputs. Read
operationsof the Electronic Signature, the Status
Register, the CFI, the Block Protection Status, the
Configuration Register status and the Security
Code are performedas single asynchronous read
cycles (Random Read). Both Chip Enable EF and
Output Enable GF must beat VILin orderto read
the outputof the memory.
Write. Write operations are usedto give Instruc-
tion Commandsto the memoryorto latch Input
Datatobe programmed.A write operationis initi-
ated when Chip Enable EF and Write Enable WF
areat VIL with Output Enable GFat VIH.Address- are latched on the falling edgeof WFor EF
whichever occurs last. Commands and Input Data
are latchedon the rising edgeof WFor EF which-
ever occurs first. Noise pulsesof less than 5ns typ-
icalon EF,WF and GF signalsdo not starta write
cycle.
Dual Bank Operations. The Dual Bank allowsto
read data from one bankof memory whilea pro-
gramor erase operationisin progressin the other
bankof the memory. Read and Write cycles can initiatedfor simultaneous operationsin different
banks without any delay. Status Register during
Programor Erase mustbe monitored usingan ad-
dress within the bank being modified.
Output Disable. The data outputs are high im-
pedance when the Output Enable GFisat VIH with
Write Enable WFat VIH.
Standby. The memoryisin standby when Chip
Enable EFisat VIH and the P/E.C.is idle. The
power consumptionis reducedto the standby level
and the outputs are high impedance, independent the Output Enable GFor Write Enable WF in-
puts.
Automatic Standby. Whenin Read mode, after
150nsof bus inactivity and when CMOS levels are
driving the addresses, the chip automatically en-
tersa pseudo-standby mode where consumption reducedto the CMOS standby value, while out-
puts still drive the bus.
Power Down. The memoryisin Power Down
when the Configuration Registeris set for Power
Down and RPFisat VIL. The power consumption reducedto the Power Down level, and Outputs
arein high impedance, independentof the Chip
Enable EF, Output Enable GFor Write Enable WF
inputs.
Block Locking. Any combinationof blocks can temporarily protected against Program or
Eraseby setting the lock register and pulling WPF VIL (see Block Lock instruction).
M36DR432A, M36DR432B8/46
Table4. BankSizeand Sectorization
Table5. BankA, Top Boot Block Addresses
M36DR432A
Table6. BankB, Top Boot Block Addresses
M36DR432A
9/46
M36DR432A, M36DR432B
Table7. BankB, Bottom Boot BlockAddresses
M36DR432B
Table8. BankA, Bottom Boot Block Addresses
M36DR432B
M36DR432A, M36DR432B10/46
Table9. User Bus Operations(1)Note:1.X= Don't care.
Table 10. Read Electronic Signature (AS and Read CFI instructions)
Table 11. Read Block Protection (AS and Read CFI instructions)
Table 12. Read Configuration Register (AS and Read CFI instructions)
11/46
M36DR432A, M36DR432B
INSTRUCTIONS AND COMMANDSSeventeen instructions are defined (see Table
15), and the internal P/E.C. automatically handles
all timing and verification of the Program and
Erase operations. The Status Register Data Poll-
ing, Toggle, Error bits canbe readat any time, dur-
ing programmingor erase,to monitor the progress the operation.
Instructions, madeupof oneor more commands
writtenincycles, can begivento theProgram/
Erase Controller througha Command Interface
(C.I.). The C.I. latches commands writtento the
memory. Commands are madeof address and
data sequences. Two Coded Cycles unlock the
Command Interface. They are followedbyan input
commandora confirmation command. The Coded
Sequence consistsof writing the data AAhat the
address 555h during the first cycle and the data
55hat the address 2AAh during the second cycle.
Instructions are composedofuptosix cycles. The
first two cycles inputa Coded Sequenceto the
Command Interface whichis commonto all in-
structions (see Table 15). The third cycle inputs
the instruction set-up command. Subsequent cy-
cles output the addressed data, Electronic Signa-
ture, Block Protection, Configuration Register
Statusor CFI Queryfor Read operations.In order give additional data protection, the instructions
for Block Erase and Bank Erase require further
command inputs. Fora Program instruction, the
fourth command cycle inputs the address and databe programmed. Fora Double Word Program-
ming instruction, the fourth and fifth command cy-
cles input the address and data to be
programmed. Fora Block Erase and Bank Erase
instructions, the fourth and fifth cycles inputa fur-
ther Coded Sequence before the Erase confirm
command on the sixth cycle. Any combinationof
blocksof the same memory bank canbe erased.
Erasureofa memory block maybe suspended,in
orderto read data from another blockorto pro-
gram datain another block, and then resumed.
When poweris first applied the command interface resetto Read Array.
Command sequencing must be followed exactly.
Any invalid combinationof commands will reset
the deviceto Read Array. The increased number cycles has been chosento ensure maximum
data security.
Table 13. Commands
Read/Reset (RD) Instruction. The Read/Reset
instruction consistsof one write cycle giving the
command F0h.It can be optionally precededby
the two Coded Cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read.
CFI Query (RCFI) Instruction. Common Flash
Interface Query modeis entered writing 98hat ad-
dress 55h. The CFI data structure gives informa-
tionon the device, suchas the sectorization, the
command set and some electrical specifications.
Table 18, 19,20 and21 show the addresses used retrieve each data. The CFI data structure con-
tains alsoa security area;in this section,a64bit
unique security numberis written, startingat ad-
dress 80h. This area canbe accessed onlyin read
modeby the final user and there are no waysof
changing the code afterit has been writtenby ST.
Writea read instruction (RD)to returnto Read
mode.
Auto Select (AS) Instruction. This instruction uses
two Coded Cycles followedby one write cycle giv-
ing the command 90hto address 555h for com-
mand set-up.A subsequent read will output the
Manufactureror the Device Code (Electronic Sig-
nature), the Block Protection statusor the Config-
uration Register status dependingon the levelsof and A1 (see Table 10,11 and 12). A7-A2 mustat VIL, while other address input are ignored.
M36DR432A, M36DR432B12/46
The bank addressis don’t carefor this instruction.
The Electronic Signature can be read from the
memory allowing programming equipmentor ap-
plicationsto automatically match their interfaceto
the characteristicsof Flash Chip. The Manufactur- Codeis output when the address lines A0 and areat VIL, the Device Codeis output when A0at VIH with A1at VIL.
The codes are output on DQ0-DQ7 with DQ8-
DQ15at 00h. The AS instruction also allows the
accessto the Block Protection Status. After giving
the AS instruction, A0is setto VIL with A1at VIH,
while A12-A20 define the addressof the blockto verified.A readin these conditions will outputa
01hif the blockis protected anda 00hif the block not protected.
The AS Instruction finally allows the accessto the
Configuration Register statusif both A0 and A1
are setto VIH.If DQ10is'0' only the Reset function activeas RPFis setto VIL (defaultat power-up). DQ10is'1' both the Reset and the Power Down
functions will be achievedby pulling RPFto VIL.
The other bitsof the Configuration Register arere-
served and must be ignored.A reset command
puts the devicein read array mode.
Write Configuration Register (CR) Instruc-
tion. This instruction uses two Coded Cycles fol-
lowedby one write cycle giving the command 60h address 555h.A further write cycle giving the
command 03h writes the contentsof address bits
A0-A15to the 16 bits configuration register. Bits
writtenby inputs A0-A9 and A11-A15 are reserved
for future use. Address input A10 defines the sta-
tusof the Reset/Power Down functions.It mustbe
setto VILto enable only the Reset function andto
VIHto enable also the Power Down function.At
Power Upall the Configuration Register bits are
resetto '0'.
Enter Bypass Mode (EBY) Instruction. This in-
struction uses the two Coded cycles followedby
one write cycle giving the command 20hto ad-
dress 555h for mode set-up. Oncein Bypass
mode, the device will accept the Exit Bypass
(XBY) and Programor Double Word Programin
Bypass mode (PGBY, DPGBY) commands. The
Bypass mode allowsto reduce the overall pro-
gramming time when large memory arrays needto programmed.
Exit Bypass Mode (XBY) Instruction. This in-
struction uses two write cycles. The first inputsto
the memory the command 90h and the secondin-
puts the Exit Bypass mode confirm (00h). After the
XBY instruction, the device resetsto Read Memo- Array mode.
Program in Bypass Mode (PGBY) Instruc-
tion. This instruction uses two write cycles. The
Program command A0his writtento any Address the first cycle and the second write cycle latch- the Addresson the falling edgeof WForEF and
the Datatobe writtenon the rising edge and starts
the P/E.C. Read operations within the same bank
output the Status Register bits after the program-
ming has started. Memory programmingis made
onlyby writing'0'in placeof '1'. Status bits DQ6
and DQ7 determineif programmingis on-going
and DQ5 allows verificationof any possible error.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0his
writtento address 555hon the third cycle after two
Coded Cycles.A fourth write operation latches the
Address and the Datato be written and starts the
P/E.C. Read operations within the same bank out-
put the Status Register bits after the programming
has started. Memory programmingis made only writing'0'in placeof '1'. Status bits DQ6 and
DQ7 determineif programmingis on-going and
DQ5 allows verificationof any possible error. Pro-
gramming at an address notin blocks being
erasedis also possible during erase suspend.
Double Word Program (DPG) Instruction. This
featureis offeredto improve the programming
throughput, writinga pageof two adjacent words parallel. High voltage (11.4Vto 12.6V)on VPP
pinis required. This instruction uses five write cy-
cles. The double word program command 40his
writtento address 555hon the third cycle after two
Coded Cycles.A fourth write cycle latches the ad-
dress and datatobe writtento the first location.A
fifth write cycle latches the new datato be written the second location and starts the P/E.C.. Note
that the two locations must have the same address
except for the addressbit A0. The Double Word
Program canbe executedin Bypass mode (DPG-
BY)to skip the two coded cyclesat the beginning each command.
Block Protect (BP), Block Unprotect (BU),
Block Lock (BL) Instructions. All blocks are
protectedat power-up. Each blockof the array has
two levelsof protection against programor erase
operation. The first levelis setby the Block Protect
instruction;a protected block cannot be pro-
grammedor erased untila Block Unprotect in-
structionis given for that block.A second levelof
protectionis setby the Block Lock instruction, and
requires the useof the WPF pin, accordingto the
following scheme: when WPFisat VIH, the Lock statusis overrid-
den andall blocks can be protectedor unpro-
tected; when WPFisat VIL, Lock statusis enabled; the
locked blocks are protected, regardlessof their
previous protect state, and protection status
cannot be changed. Blocks that are not locked
can still change their protection status, and pro-
gramor erase accordingly;
13/46
M36DR432A, M36DR432B the lock statusis clearedforall blocksat power
up; oncea block has been locked state canbe
cleared only witha reset command. The protec-
tion and lock status canbe monitored for each
block using the Autoselect (AS) instruction. Pro-
tected blocks will outputa‘1’on DQ0 and locked
blocks will outputa‘1’on DQ1.
Referto Table14fora listof the protection states.
Block Erase (BE) Instruction. This instruction
usesa minimumof six write cycles. The Erase
Set-up command 80his writtento address 555h third cycle after the two Coded cycles. The
Block Erase Confirm command 30his similarly
writtenon the sixth cycle after another two Coded
cycles and an address within the blockto be
erasedis given and latched into the memory.
Additional block Erase Confirm commands and
block addresses can be written subsequentlyto
erase other blocksin parallel, without further Cod- cycles. All blocks must belongto the same
bankof memory;ifa new block belongingto the
other bankis given, the operationis aborted. The
erase will start after an erase timeout periodof
100μs. Thus, additional Erase Confirm commands
for other blocks must be given within this delay.
The inputofa new Erase Confirm command will
restart the timeout period. The statusof the inter-
nal timer can be monitored through the levelof
DQ3,if DQ3is'0' the Block Erase Command has
been given and the timeoutis running,if DQ3is'1',
the timeout has expired and the P/E.C.is erasing
the Block(s).If the second command givenis not erase confirmorif the Coded cycles are wrong,
the instruction aborts, and the deviceis resetto
Read Array.Itis not necessaryto program the
block with 00has the P/E.C. willdo this automati-
cally before erasingto FFh. Read operations with- the same bank, after the sixth rising edgeof WF EF, output the status register bits.
During the executionof the eraseby the P/E.C.,
the memory accepts only the Erase Suspend ES
instruction; the Read/Reset RD instructionis ac-
cepted during the 100μs time-out period. Data
Polling bit DQ7 returns'0' while the erasureisin
progress and'1' whenit has completed. The Tog-
gle bit DQ6 toggles during the erase operation,
and stops when eraseis completed.
After completion the Status Register bit DQ5 re-
turns'1'if there has beenan erase failure.In such situation, the Togglebit DQ2 canbe usedto de-
termine which blockis not correctly erased.In the
caseof erase failure,a Read/Reset RD instruction necessaryin orderto reset the P/E.C.
Bank Erase (BKE) Instruction. This instruction
uses six write cycles andis usedto eraseall the
blocks belongingto the selected bank. The Erase
Set-up command 80his writtento address 555h the third cycle after the two Coded cycles. The
Bank Erase Confirm command 10his similarly
writtenon the sixth cycle after another two Coded
cyclesat an address within the selected bank.If
the second command givenis notan erase con-
firmorif the Coded cycles are wrong, the instruc-
tion aborts and the deviceis resetto Read Array.is not necessaryto program the array with 00h
firstas the P/E.C. will automaticallydo this before
erasingitto FFh. Read operations within the same
bank after the sixth rising edgeof WFor EF output
the Status Register bits. During the executionof
the eraseby the P/E.C., Data Pollingbit DQ7 re-
turns '0', then'1' on completion. The Toggle bit
DQ6 toggles during erase operation and stops
when eraseis completed. After completion the
Status Register bit DQ5 returns'1'if there has
beenan Erase Failure.
Erase Suspend (ES) Instruction.Ina dual bank
memory the Erase Suspend instructionis usedto
read data within the bank where eraseisin
progress.Itis also possibleto program datain
blocks not being erased.
The Erase Suspend instruction consistsof writing
the command B0h without any specific address. Coded Cycles are required. Erase suspendis
accepted only during the Block Erase instruction
execution. The Toggle bit DQ6 stops toggling
when the P/E.C.is suspended within 15μs after
the Erase Suspend (ES) command has been writ-
ten. The device will then automatically be setto
Read Memory Array mode. When eraseis sus-
pended,a Read from blocks being erased will out-
put DQ2 toggling and DQ6at '1'.A Read froma
block not being erased returns valid data. During
suspension the memory will respond onlyto the
Erase Resume ER and the Program PG instruc-
tions.A Program operation canbe initiated during
erase suspendin oneof the blocks not being
erased.It will resultin DQ6 toggling when the data being programmed.
Erase Resume (ER) Instruction.If an Erase
Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h,atan address within the bank be-
ing erased and without any Coded Cycle.
M36DR432A, M36DR432B14/46
Table 14. Protection States(1)Note:1.All blocksare protectedat power-up,sothe default configurationis001or 101 accordingto WPF status. Current state and Next state givesthe protection statusofa block. The protection statusis definedbythe write protectpinandby
DQ1(=1foralockedblock)and DQ0(=1foraprotectedblock)as readinthe Autoselect instruction withA1=VIH andA0=VIL. Next stateisthe protection statusofa block aftera Protector Unprotector Lock commandhas been issuedor after WPF has
changedits logic value.A WPF transitiontoVIHona locked blockwill restorethe previous DQ0 value, givinga111or 110.
Table 15. Instructions (1,2)
15/46
M36DR432A, M36DR432BNote:1. Commandsnot interpretedinthis tablewill defaultto read array mode. For Coded cycles address inputs A11-A20are don't care.X= Don't Care. The first cyclesoftheRDorAS instructionsare followedby read operations. Any numberof read cycles can occur afterthe com-
mand cycles. During Erase Suspend, Read and Data Program functionsare allowedin blocksnot being erased. Program Address1 and ProgramAddress2 mustbe consecutive addresses differing onlyfor addressbitA0. High voltageon VPPF (11.4Vto 12.6V)is requiredforthe proper executionofthe Double Word Program instruction.
M36DR432A, M36DR432B16/46
STATUS REGISTER BITSP/E.C. statusis indicated during executionby Data
Pollingon DQ7, detectionof Toggleon DQ6 and
DQ2,or Erroron DQ5 bits. Any read attempt within
the Bank being modified and during Programor
Erase command execution will automatically out-
put these five Status Register bits. The P/E.C. au-
tomatically sets bits DQ2, DQ5, DQ6 and DQ7.
Other bits (DQ0, DQ1 and DQ4) are reserved for
future use and shouldbe masked (see Tables17
and 16). Read attempts within the bank not being
modified will output array data.
Data Polling Bit (DQ7). When Programming op-
erations arein progress, thisbit outputs the com-
plementof thebit being programmed on DQ7.In
caseofa double word program operation, the
complementis doneon DQ7of the last word writ-
tento the command interface, i.e. the data written the fifth cycle. During Erase operation,it outputs '0'. After completionof the operation, DQ7 will
output thebit last programmedora'1' after eras-
ing. Data Pollingis valid and only effective
P/E.C. operation, thatis after the fourth WF pulse
for programmingor after the sixth WF pulse for
erase.It mustbe performedat the address being
programmedoratan address within the block be-
ing erased. See Figure 25 for the Data Polling
flowchart and Figure12for the Data Polling wave-
forms. DQ7 will also flag the Erase Suspend mode switching from'0'to'1'at the startof the Erase
Suspend.In orderto monitor DQ7in the Erase
Suspend mode an address withina block being
erased mustbe provided. Fora Read Operationin
Suspend mode, DQ7 will output'1'if the readisat-
temptedona block being erased and the data val- on other blocks. During Program operationin
Erase Suspend Mode, DQ7 will have the same be-
haviorasin the normal program execution outside the suspend mode.
Toggle Bit (DQ6). When Programmingor Eras-
ing operations arein progress, successive at-
temptsto read DQ6 will output complementary
data. DQ6 will toggle following togglingof either
GF,or EF when GFisat VIL. The operationis com-
pleted when two successive reads yield the same
output data. The next read will output thebit last
programmedora'1' after erasing. The togglebit
DQ6is valid only during P/E.C. operations, thatis
after the fourth WF pulsefor programmingor after
the sixth WF pulse for Erase. DQ6 willbe setto'1'a Read operationis attemptedonan Erase Sus-
pend block. When eraseis suspended DQ6 will
toggle during programming operationsina block
different from the blockin Erase Suspend. Eitheror GF toggling will cause DQ6to toggle. See
Figure 25 for Toggle Bit flowchart and Figure 13
for Toggle Bit waveforms.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, canbe usedto determine the device status
during the Erase operations. During Erase Sus-
penda read froma block being erased will cause
DQ2to toggle.A read froma block not being
erased will output data. DQ2 willbe setto'1' during
program operation andto‘0’in Erase operation.
After erase completion andif the errorbit DQ5is
setto '1', DQ2 will toggleif the faulty blockis ad-
dressed.
Error Bit (DQ5). Thisbitis setto'1'by the P/E.C.
when thereisa failureof programmingor block
erase, that resultsin invalid datain the memory
block.In caseof an errorin block eraseor pro-
gram, the blockin which the error occurredorto
which the programmed data belongs, mustbe dis-
carded. Other Blocks may stillbe used. The error
bit resets aftera Read/Reset (RD) instruction.In
caseof successof Programor Erase, the errorbit
willbe setto'0'.
Erase Timer Bit (DQ3). Thisbitis setto‘0’by the
P/E.C. when the last block Erase command has
been enteredto the Command Interface anditis
awaiting the Erase start. When the erase timeout
periodis finished, DQ3 returnsto ‘1’,in the range 80μsto 120μs.
Table 16. Polling and Toggle Bits
17/46
M36DR432A, M36DR432B
Table 17. Status Register Bits(1)Note:1. Logic level'1'is High,'0'is Low. -0-1-0-0-0-1-1-1-0- representbit valuein successive Read operations.In caseof double word program DQ7referstothelast word input.
M36DR432A, M36DR432B18/46
POWER CONSUMPTION
Power DownThe memory provides Reset/Power Down control
input RPF. The Power Down function canbe acti-
vated onlyif the relevant Configuration Registerbit setto '1'.In this case, when the RPF signalis
pulledat VSS the supply current dropsto typically
ICC2 (see Table 24), the memoryis deselected and
the outputs arein high impedance.If RPFis pulled VSS duringa Programor Erase operation, this
operationis abortedin tPLQ7V and the memory
contentisno longer valid (see Reset/Power Down
input description).
Power UpThe memory Command Interfaceis reseton Pow- Upto Read Array. Either EFor WF mustbe tied VIH during Power Upto allow maximum security
and the possibilityto writea commandon the first
rising edgeof WF.
Supply RailsNormal precautions mustbe taken for supply volt-
age decoupling; each deviceina system should
have the VCCF rails decoupled witha 0.1μF capac-
itor closetothe VCCF and VSS pins. The PCB trace
widths should be sufficientto carry the required
VCCF program and erase currents.
19/46
M36DR432A, M36DR432B
COMMON FLASH INTERFACE (CFI)The Common Flash Interface (CFI) specificationis JEDEC approved, standardised data structure
that can be read from the Flash memory device.
CFI allowsa system softwareto query the flash
deviceto determine various electrical and timing
parameters, density information and functions
supportedby the device. CFI allows the systemto
easily interfaceto the Flash memory,to learn
aboutits features and parameters, enabling the
softwareto configure itself when necessary.
Tables 18, 19, 20, and21 show the address used retrieve each data.
The CFI data structure gives information on the
device, such as the sectorization, the command
set and some electrical specifications. Tables 18,
19, 20, and 21 show the addresses usedto re-
trieve each data. The CFI data structure contains
alsoa security area;in this section,a64bit unique
security numberis written, startingat address 81h.
This area canbe accessed onlyin read mode and
there areno waysof changing the code afterit has
been writtenby ST. Writea read instructionto re-
turnto Read mode. Referto the CFI Query instruc-
tionto understand how the M36DR432 enters the
CFI Query mode.
Table 18. Query Structure OverviewNote: The Flash memory displaytheCFI data structure whenCFI Query commandis issued.Inthis tableare listedthe main sub-sections
detailedin Tables19,20 and21. Query dataare always presentedonthe lowest order data outputs.
Table 19. CFI Query Identification StringNote:1. Query dataare always presentedonthe lowest- order data outputs (DQ7-DQ0) only. DQ8-DQ15are‘0’.
M36DR432A, M36DR432B20/46
Table 20. CFI Query System Interface Information
21/46
M36DR432A, M36DR432B
Table 21. Device Geometry Definition
M36DR432A, M36DR432B22/46
SRAM COMPONENT
Device OperationsThe following operations canbe performed using
the appropriate bus cycles: Read Array, Write Ar-
ray, Output Disable, Power Down (see Table 3).
Read. Read operations are usedto output the
contentsof the SRAM Array. The SRAMisin Read
mode whenever Write Enable (WS)isat VIH with
Output Enable (GS)at VIL, and both Chip Enables
(E1S and E2S) and UBS,LBS combinations are
asserted.
Valid data willbe availableat the output pins within
tAVQV after the last stable address, providing GSis
Low, E1Sis Low and E2Sis High.If Chip Enable Output Enable access times are not met, data
access willbe measured from the limiting parame-
ter (tE1LQV,tE2HQV,or tGLQV) rather than the ad-
dress. Data out may be indeterminateat tE1LQX,
tE2HQX and tGLQX, but data lines will alwaysbe val-at tAVQV (see Table 31, Figures 16 and 17).
Write. Write operations are usedto write datain
the SRAM. The SRAMisin Write mode whenever
the WS and E1S pins areat VIL, with E2Sat VIH.
Either the Chip Enable inputs (E1S and E2S)or
the Write Enable input (WS) mustbe de-asserted
during address transitionsfor subsequent write cy-
cles. Write begins with the concurrenceof both
Chip Enables being active with WSat VIL.AWrite
beginsat the latest transition among E1S goingto
VIL, E2S goingtoVIH and WS goingto VIL. There-
fore, address setup timeis referencedto Write En-
able and both Chip Enablesas tAVWL,tAVE1L and
tAVE2H respectively, andis determinedby the latter
occurring edge. The Write cycle canbe terminated therisingedgeof E1S, the rising edgeof WSor
the falling edgeof E2S, whichever occurs first. the Outputis enabled (E1S=VIL,E2S=VIH and
GS=VIL), then WS will return the outputsto high
impedance within tWLQZofits falling edge. Care
mustbe takento avoid bus contentionin this type operation. Data input must be valid for tDVWH
before the rising edgeof Write Enable, or for
tDVE1H before the rising edgeof E1Sorfor tDVE2L
before the falling edgeof E2S, whichever occurs
first, and remain valid for tWHDX,tE1HAXor tE2LAX
(see Table 32, Figure 19, 21, 23).
Standby/Power-Down. The SRAM chip hasa
Chip Enable power-down feature which invokes automatic standby mode (see Table 31, Figure
18) whenever either Chip Enableis de-asserted
(E1S=VIHor E2S=VIL).
Data RetentionThe SRAM data retention performancesas VCCS downto VDR are describedin Table33 and Fig-
ure 23, 24.In E1S controlled data retention mode,
minimum standby current modeis entered when
E1S≥ VCCS– 0.2V and E2S≤ 0.2V or
E2S≥ VCCS– 0.2V.In E2S controlled data reten-
tion mode, minimum standby current modeis en-
tered when E2S≤ 0.2V.
Output Disable. The data outputs are high im-
pedance when the Output Enable (GS)isat VIH
with Write Enable (WS)at VIH.
23/46
M36DR432A, M36DR432B
Table 23. Device Capacitance(1) (TA=25 °C,f=1 MHz)
Note:1. Sampled only,not 100% tested.
