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M35080
8 Kbit Serial SPI Bus EEPROM With Incremental Registers
1/18
PRELIMINARY DATAJune 1999
M350808 Kbit Serial SPI Bus EEPROM
With Incremental RegistersCompatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)Single Supply Voltage: 4.5V to 5.5V5 MHz Clock Rate (maximum)Sixteen 16-bit Incremental RegistersBYTE and PAGE WRITE (up to 32 Bytes)
(except for the Incremental Registers)Self-Timed Programming CycleHardware Protection of the Status RegisterResizeable Read-Only EEPROM AreaEnhanced ESD Protection1 Million Erase/Write Cycles (minimum)40 Year Data Retention (minimum)
DESCRIPTIONThe M35080 device consists of 1024x8 bits of low
power EEPROM, fabricated with
STMicroelectronics’ proprietary High Endurance
Double Polysilicon CMOS technology.
The device is accessed by a simple SPI-compati-
ble serial interface. The bus signals consist of a
serial clock input (C), a serial data input (D) and a
serial data output (Q), as shown in Table 1.
The device is selected when the chip select input
(S) is held low. Data is clocked in during the low to
high transition of the clock, C. Data is clocked out
during the high to low transition of the clock.
Table 1. Signal Names
M35080
Figure 2. DIP and SO Connections
Note:1.NC = Not Connected.
Table 2. Absolute Maximum Ratings 1
Note:1.Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and
other relevant quality documents.MIL-STD-883C, 3015.7 (100pF, 1500W).EIAJ IC-121 (Condition C) (200pF, 0W).
The memory is organized in pages of 32 bytes.
However, the first page is not treated in the same
way as the others. Instead, it is considered to con-
sist of sixteen 16-bit incremental registers. Each
register can be modified using the conventional
write instructions, but the new value will only be
accepted if it is greater than the current value.
Thus, each register is restricted to being modified
monotonically upwards.
This is useful in applications where it is necessary
to implement a counter that is protected from
fraudulent tampering (such as in a car odometer,
an electricity meter, or a tally for remaining credit).
SIGNAL DESCRIPTION
Serial Output (Q)
The output pin is used to transfer data serially out
of the Memory. Data is shifted out on the falling
edge of the serial clock.
Serial Input (D)
The input pin is used to transfer data serially into
the device. Instructions, addresses, and the data
to be written, are each received this way. Input is
latched on the rising edge of the serial clock.
Serial Clock (C)
The serial clock provides the timing for the serial
interface (as shown in Figure 3). Instructions, ad-
dresses, or data are latched, from the input pin, on
the rising edge of the clock input. The output data
on the Q pin changes state after the falling edge of
the clock input.
Chip Select (S)
When S is high, the memory device is deselected,
and the Q output pin is held in its high impedance
state. Unless an internal write operation is under-
way, the memory device is placed in its stand-by
power mode.
After power-on, a high-to-low transition on S is re-
quired prior to the start of any operation.
Write Protect (W)
The protection features of the memory device are
summarized in Table 3.
The hardware write protection, controlled by the W
pin, restricts write access to the Status Register
3/18
M35080
Figure 3. Data and Clock Timing
(though not to the WIP and WEL bits, which are
set or reset by the device’s internal logic).
Bit 7 of the status register (as shown in Table 4) is
the Status Register Write Disable bit (SRWD).
When this is set to 0 (its initial delivery state) it is
possible to write to the status register if the WEL
bit (Write Enable Latch) has been set by the
WREN instruction (irrespective of the level being
applied to the W input).
When bit 7 (SRWD) of the status register is set to
1, the ability to write to the status register depends
on the logic level being presented at pin W:
–If W pin is high, it is possible to write to the sta-
tus register, after having set the WEL bit using
the WREN instruction (Write Enable Latch).
–If W pin is low, any attempt to modify the status
register is ignored by the device, even if the
WEL bit has been set. As a consequence, all the
data bytes in the EEPROM area, protected by
the BP1 and BP0 bits of the status register, are
also hardware protected against data corrup-
tion, and appear as a Read Only EEPROM area
for the microcontroller. This mode is called the
Hardware Protected Mode (HPM).
It is possible to enter the Hardware Protected
Mode (HPM) either by setting the SRWD bit after
pulling low the W pin, or by pulling low the W pin
after setting the SRWD bit.
The only way to abort the Hardware Protected
Mode, once entered, is to pull high the W pin.
If W pin is permanently tied to the high level, the
Hardware Protected Mode is never activated, and
the memory device only allows the user to protect
a part of the memory, using the BP1 and BP0 bits
of the status register, in the Software Protected
Mode (SPM).
IMPORTANT: if W pin is left floating, not driven by
the application, W is read as a logical ’0’.
Table 3. Write Protection Control
Table 4. Status Register Format
Note:1.BP0, BP1: Read and write bitsUV, INC, WEL, WIP: Read only bits.SRWD: Read and Write bit.
b7 b0
M35080
OPERATIONS
All instructions, addresses and data are shifted se-
rially in and out of the chip (along the bus, as
shown in Figure 4). The most significant bit is pre-
sented first, with the data input (D) sampled on the
first rising edge of the clock (C) after the chip se-
lect (S) goes low (as shown in Figure 5, Figure 9,
and Figure 12).
Every instruction, as summarized in Table 5, starts
with a single-byte code. If an invalid instruction is
sent (one not contained in Table 5), the chip auto-
matically deselects itself.
The instruction code is entered via the data input
(D), and latched on the rising edge of the clock in-
put (C). To enter an instruction code, the device
must have been previously selected (S held low).
Protection of the First 32 Bytes
The first 32-byte page is organized as 16 words
(two bytes each). The initial content of each word
on this page is 0000h. When writing to byte-pair, a
logic comparator verifies that the new two-byte
value is larger than the value currently stored. If
the new value is smaller than the current one, no
operation is performed. It is impossible to write a
value lower than the previous one, irrespective of
the state of W pin and status register, as indicated
in Table 6.
Write Enable (WREN) and Write Disable (WRDI)
The write enable latch, inside the memory device,
must be set prior to each WRITE and WRSR oper-
ation. The WREN instruction (write enable) sets
this latch, and the WRDI instruction (write disable)
resets it.
Figure 4. EEPROM and SPI Bus
Table 5. Instruction Set
5/18
M35080
The latch becomes reset by any of the following
events:Power onWRDI instruction completionWRSR instruction completionWRITE instruction completion.
As soon as the WREN or WRDI instruction is re-
ceived, the memory device first executes the in-
struction, then enters a wait mode until the device
is deselected.
Read Status Register (RDSR)
The RDSR instruction allows the status register to
be read, and can be sent at any time, even during
a Write operation. Indeed, when a Write is in
progress, it is recommended that the value of the
Write-In-Progress (WIP) bit be checked. The value
in the WIP bit (whose position in the status register
is shown in Table 4) can be continuously polled,
before sending a new WRITE instruction. This can
be performed in one of two ways:Repeated RDSR instructions (each one
consisting of S being taken low, C being clocked
8 times for the instruction and 8 times for the
read operation, and S being taken high)A single, prolonged RDSR instruction
(consisting of S being taken low, C being
clocked 8 times for the instruction and kept
running for repeated read operations), as
shown in Figure 6.
The Write-In-Process (WIP) bit is read-only, and
indicates whether the memory is busy with a Write
operation. A ’1’ indicates that a write is in progress,
and a ’0’ that no write is in progress.
The Write Enable Latch (WEL) bit indicates the
status of the write enable latch. It, too, is read-only.
Its value can only be changed by one of the events
listed earlier, or as a result of executing WREN or
WRDI instruction. It cannot be changed using a
WRSR instruction. A ’1’ indicates that the latch is
set (the forthcoming Write instruction will be exe-
cuted), and a ’0’ that it is reset (and any forthcom-
ing Write instructions will be ignored).
The Block Protect (BP0 and BP1) bits indicate the
amount of the memory that is to be write-protect-
ed. These two bits are non-volatile. They are set
using a WRSR instruction.
During a Write operation (whether it be to the
memory area or to the status register), all bits of
the status register remain valid, and can be read
using the RDSR instruction. However, during a
Write operation, the values of the non-volatile bits
Figure 5. Read EEPROM Array Operation Sequence
Note:1.The most significant address bits, A15-A10, are treated as Don’t Care.
Table 6. Memory Mapping
M35080
(SRWD, BP0, BP1) become frozen at a constant
value. The updated value of these bits becomes
available when a new RDSR instruction is execut-
ed, after completion of the write cycle. On the oth-
er hand, the two read-only bits (WEL, WIP) are
dynamically updated during internal write cycles.
Using this facility, it is possible to poll the WIP bit
to detect the end of the internal write cycle.
The Comparator bit (INC) indicates if the new val-
ue written in the 16 first word is lower ‘1’ or higher
‘0’ than the previous stored value.
The UV bit indicates if the memory chip has been
erased.
Write Status Register (WRSR)
The format of the WRSR instruction is shown in
Figure 7. After the instruction and the eight bits of
the status register have been latched-in, the inter-
nal Write cycle is triggered by the rising edge of
the S line. This must occur after the falling edge of
the 16th clock pulse, and before the rising edge of
the 17th clock (as indicated in Figure 7), otherwise
the internal write sequence is not performed.
The WRSR instruction is used for the following:to select the size of memory area that is to be
write-protectedto select between SPM (Software Protected
Mode) and HPM (Hardware Protected Mode).
The size of the write-protection area applies equal-
ly in SPM and HPM. The BP1 and BP0 bits of the
status register have the appropriate value (see Ta-
ble 7) written into them after the contents of the
protected area of the EEPROM have been written.
The initial delivery state of the BP1 and BP0 bits is
00, indicating a write-protection size of 0.
Figure 7. WRSR: Write Status Register Sequence
Figure 6. RDSR: Read Status Register Sequence
7/18
M35080
Software Protected Mode (SPM)
The act of writing a non-zero value to the BP1 and
BP0 bits causes the Software Protected Mode
(SPM) to be started. All attempts to write a byte or
page in the protected area are ignored, even if the
Write Enable Latch is set. However, writing is still
allowed in the unprotected area of the memory ar-
ray and to the SRWD, BP1 and BP0 bits of the sta-
tus register, provided that the WEL bit is first set.
Hardware Protected Mode (HPM)
The Hardware Protected Mode (HPM) offers a
higher level of protection, and can be selected by
setting the SRWD bit after pulling down the W pin
or by pulling down the W pin after setting the
SRWD bit. The SRWD is set by the WSR instruc-
tion, provided that the WEL bit is first set. The set-
ting of the SRWD bit can be made independently
of, or at the same time as, writing a new value to
the BP1 and BP0 bits.
Once the device is in the Hardware Protected
Mode, the data bytes in the protected area of the
memory array, and the content of the status regis-
ter, are write-protected. The only way to re-enable
writing new values to the status register is to pull
the W pin high. This cause the device to leave the
Hardware Protected Mode, and to revert to being
in the Software Protected Mode. (The value in the
BP1 and BP0 bits will not have been changed).
Further details of the operation of the Write Protect
pin (W) are given earlier, on page 2.
Typical Use of HPM and SPM
The W pin can be dynamically driven by an output
port of a microcontroller. It is also possible,
though, to connect it permanently to VSS (by a sol-
der connection, or through a pull-down resistor).
The manufacturer of such a printed circuit board
can take the memory device, still in its initial deliv-
ery state, and can solder it directly on to the board.
After power on, the microcontroller can be instruct-
ed to write the protected data into the appropriate
area of the memory. When it has finished, the ap-
propriate values are written to the BP1, BP0 and
SRWD bits, thereby putting the device in the hard-
ware protected mode.
An alternative method is to write the protected da-
ta, and to set the BP1, BP0 and SRWD bits, before
soldering the memory device to the board. Again,
this results in the memory device being placed in
its hardware protected mode.
If the W pin has been connected to VSS by a pull-
down resistor, the memory device can be taken
out of the hardware protected mode by driving the
W pin high, to override the pull-down resistor.
If the W pin has been directly soldered to VSS,
there is only one way of taking the memory device
out of the hardware protected mode: the memory
device must be de-soldered from the board, and
connected to external equipment in which the W
pin is allowed to be taken high.
Read Operation
The chip is first selected by holding S low. The se-
rial one byte read instruction is followed by a two
byte address (A15-A0), each bit being latched-in
during the rising edge of the clock (C). The data
stored in the memory, at the selected address, is
shifted out on the Q output pin. Each bit is shifted
out during the falling edge of the clock (C) as
shown in Figure 5.
The internal address counter is automatically in-
cremented to the next higher address after each
byte of data has been shifted out. The data stored
in the memory, at the next address, can be read by
successive clock pulses. When the highest ad-
dress is reached, the address counter rolls over to
“0000h”, allowing the read cycle to be continued
indefinitely. The read operation is terminated by
deselecting the chip. The chip can be deselected
at any time during data output. If a read instruction
is received during a write cycle, it is rejected, and
the memory device deselects itself.
Byte Write Operation
Before any write can take place, the WEL bit must
be set, using the WREN instruction, as shown in
Figure 8. The write state is entered by selecting
the chip, issuing three bytes of instruction and ad-
dress, and one byte of data. Chip Select (S) must
remain low throughout the operation, as shown in
Figure 9. The device must be deselected just after
the eighth bit of the data byte has been latched in,
Table 7. Write Protected Block Size
Note:1.Except for the first sixteen pairs of bytes (see Table 6).
M35080
Figure 8. Write Enable Latch Sequence
Figure 9. Byte Write Operation Sequence
Note:1.The most significant address bits, A15-A10, are treated as Don’t Care.
as shown in Figure 9, otherwise the write process
is cancelled. As soon as the memory device is de-
selected, the self-timed internal write cycle is initi-
ated. While the write is in progress, the status
register may be read to check the status of the SR-
WD, BP1, BP0, WEL and WIP bits. In particular,
WIP contains a ‘1’ during the self-timed write cy-
cle, and a ‘0’ when the cycle is complete, (at which
point the write enable latch is also reset).
Write Data In the Incremental Registers
Due to the special control on the first page of the
memory, the byte write operation is not usable on
the first 32 bytes. Instead, the WRINC instruction
must be used, the timing of which is shown in Fig-
ure 10.
Prior to any write attempt, the write enable latch
must be set by issuing the WREN instruction. First
the device is selected (by taking S low) and a seri-
al WREN instruction is issued. Then the device is
deselected, by taking S high for at least tSHSL. The
device sets the write enable latch, and remains in
its stand-by state, until it is deselected. Then the
write state is entered by selecting the chip, by tak-
ing S low. The WRINC instruction is issued, and
the address is sent (always an even address, with
A0=0) along with two bytes of data. The Chip Se-
lect input (S) must remain low for the entire dura-
tion of the operation.
The device must be deselected just after the
eighth bit of the second data byte has been
latched in. Otherwise, the write process is can-
celled. As a further protection, the WRINC instruc-
tion is cancelled if its duration is not exactly equal
to 40 clock pulses.
As soon as the device is deselected, the self-timed
write cycle is initiated. While the write is in
progress, the status register may be read, to check
the values of the UV, INC, BP1, BP0, WEL and
9/18
M35080
WIP bits. WIP is high during the self-timed write
cycle. When the cycle is completed, the write en-
able latch is reset.
Page Write Operation
A maximum of 32 bytes of data can be written dur-
ing one Write time, tW, provided that they are all to
the same page (see Figure 11). The Page Write
operation is the same as the Byte Write operation,
except that instead of deselecting the device after
the first byte of data, up to 31 additional bytes can
be shifted in (and the device is deselected after the
last byte).
Any address of the memory can be chosen as the
first address to be written. If the address counter
reaches the end of the page (an address of the
form xxxx xxxx xxx1 1111) and the clock contin-
ues, the counter rolls over to the first address of
the same page (xxxx xxxx xxx0 0000) and over-
writes any previously written data.
As before, the Write cycle only starts if the S tran-
sition occurs just after the eighth bit of the last data
byte has been received, as shown in Figure 12.
DATA PROTECTION AND PROTOCOL SAFETY
To protect the data in the memory from inadvertent
corruption, the memory device only responds to
correctly formulated commands. The main securi-
ty measures can be summarized as follows:The WEL bit is reset at power-up.
–S must rise after the eighth clock count (or mul-
tiple thereof) in order to start a non-volatile write
cycle (in the memory array or in the status reg-
ister).Accesses to the memory array are ignored dur-
ing the non-volatile programming cycle, and the
programming cycle continues unaffected.After execution of a WREN, WRDI, or RDSR in-
struction, the device enters a wait state, and
waits to be deselected.Invalid S transitions are ignored.
Figure 10. Write Data to Incremental Registers (WRINC)
Note:1.The most significant address bits, A15-A10, are treated as Don’t Care.
