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M34116B1STN/a200avaiPCM CONFERENCE CALL AND TONE GENERATION CIRCUIT
M34116C1STN/a500avaiPCM CONFERENCE CALL AND TONE GENERATION CIRCUIT


M34116C1 ,PCM CONFERENCE CALL AND TONE GENERATION CIRCUITELECTRICAL CHARACTERISTICS (Tamb = 0 to 70°C, VCC = 5V ± 5%)All DC characteristic are valid 250μs a ..
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M34116B1-M34116C1
PCM CONFERENCE CALL AND TONE GENERATION CIRCUIT
M34116
PCM CONFERENCE CALL
AND TONE GENERATION CIRCUIT
PRELIMINARY DATA

HW AND SW COMPATIBLE WITH M116TO 64 SERIAL CHANNELS PER FRAME
(CONTROLLED BY SYNC SIGNAL PERIOD)
29 MAXIMUM CONFERENCES
1 TO 64 SERIAL CHANNELS PER CONFER-
ENCES
3 SIMULTANEOUS OPERATION MODES
AVAILABLE:
CONFERENCE, TRANSPARENT AND TONE
GENERATION
TYPICAL BIT RATES:
1536/1544/2048/4096 Kbits/s
COMPATIBLE WITH ALL KINDS OF PCM
FORMAT
μ AND A LAW (PIN PROGRAMMABLE)
EQUAL PRIORITY TO EVERY CHANNEL
ONE FRAME AND ONE CHANNEL DELAY
FROM SENDING TO RECEIVING
OVERFLOW INFORMATION FOR EACH CON-
FERENCE BY PIN OS (OVERFLOW SIGNAL-
LING) AND ON DATA BUS ON MPU RE-
QUEST
INSTRUCTION SET COMPATIBLE WITH M3488
PROGRAMMABLE INPUT AND OUTPUT AT-
TENUATION OR GAIN FROM 0 TO 15dB
WITH STEP OF 1dB FOR EACH CHANNEL
TONE GENERATION FROM 3.9Hz TO
3938Hz WITH MIN. STEP OF 3.9Hz
TOTAL OF 7 DIFFERENT TONE OUTPUTS
IN PARALLEL PROGRAMMABLE VIA MPU
(MAXIMUM 4 DIFFERENT FREQUENCIES
AND DURATIONS)
1 MELODY OF MAXIMUM 32 PROGRAMMA-
BLE FREQUENCIES AND DURATIONS
5V POWER SUPPLY
TTL COMPATIBLE INPUT LEVELS,
CMOS/TTL COMPATIBLE OUTPUT LEVELS
MAIN INSTRUCTIONS CONTROLLED BY MI-
CROPROCESSOR INTERFACE:
– Channel connection to a conference
– Channel attenuation or gain
– Channel disconnection from both conference
and transparent modes
– Tone and melody generation
– Overflow status
– Operating mode
– Channel status
DESCRIPTION

The M34116 is a product specifically designed for
applications in PCM digital exchanges. It is able
to handle up to 64 channels in any conferences
combination from 1 to 29 conferences in parallel
and to generate seven different tones and one
melody.
The parties in a conference must previously be al-
located through the Digital Switching Matrix
(M3488) in a single serial wire at M34116 PCM
input (IN PCM pin).
The M34116 is full pin and function compatible
with the M116. In addition, it has the capability to
generate tone directly coded in PCM.
For the conference function, each channel is con-
verted inside the chip from PCM law to linear law
(14 bits). Then it is added to its conference, and
the sample of the previous frame is subtracted
from the conference.
In this way a new conference sum signal is gener-
ated.
The channel output signal will contain the infor-
mation of all the other channels in its conference
except its own.
After the PCM encoding, the data is serialized by
the M34116 in the same sequence as the PCM
input frame, with one frame (plus one channel)
delay and will be reallocated by the DSM (M3488)
at the final channel and bus position.programmable attenuation or gain can be set
on each channel and for every function: confer-
ence, tone generation and transparent mode.
PIN CONNECTIONS (Top view)
ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1: PCM Conference Call Insertion Scheme
M34116
PIN DESCRIPTION
M34116
RECOMMENDED OPERATING CONDITIONS
CAPACITANCES (measurements frequency = 1MHz; 0 to 70°C; unused pins tied to VSS)
ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70°C, VCC = 5V ± 5%)

All DC characteristic are valid 250μs after VCC and clock have been applied.
(*) Only in M34116 Operating Mode.
(**) Pin numbers referred to the DIP24.
(***) Schimitt-trigger inputs.
M34116
ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70°C, VCC = 5V ± 5%)
All DC characteristic are valid 250μs after VCC and clock have been applied. CL is the max. capacitive
load and RL the test pull up resistor.
Notes:

1. With Extra Bit operating mode insert this time becomes 3 tCK.
2. With Extra Bit operating mode insert these times are 80ns longer.
3. With OPCODE (C/D = I), this time becomes 4tck (6tck if E = 1). E: extra bit indication in "operating mode" instruction.
4. For tone generation instruction, this time becomes 4tck (6tck if E = 1) E: extra bit indication in "operating mode" instruction.
5. With extra bit operating mode insert, this time becomes 6tck.
6. The initialization routine takes 2 frames time starting from the rising edge of RESET - Any access to the device should take place after the
initialization routine is completed. (2 frames time).
M34116
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