M30LW128D110ZA6 ,128 MBIT (TWO 64MBIT, X8/X16, UNIFORM BLOCK, FLASH MEMORIES) 3V SUPPLY, MULTIPLE MEMORY PRODUCTLogic Diagram . . 6Table 1. Signal Names . . 6Figure 3. TSOP56 Connections . . ..
M30LW128D-110ZA6 ,128 MBIT (TWO 64MBIT, X8/X16, UNIFORM BLOCK, FLASH MEMORIES) 3V SUPPLY, MULTIPLE MEMORY PRODUCTFEATURES SUMMARY■ TWO M58LW064D 64Mbit FLASH Figure 1. PackagesMEMORIES STACKED IN A SINGLE PACKAGE ..
M3131 , 5x7 mm, 3.3/2.5/1.8 Volt, LVPECL/LVDS/CML/HCMOS Output
M3131 , 5x7 mm, 3.3/2.5/1.8 Volt, LVPECL/LVDS/CML/HCMOS Output
M32000D4BFP-80 , SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
M32000D4BFP-80 , SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
M-522CT , DC Line Fileters
M-522CT , DC Line Fileters
M52303ASP , NTSC System Single-Chip color TV Signal processor
M52303ASP , NTSC System Single-Chip color TV Signal processor
M5230FP , VARIABLE OUTPUT VOLTAGE REGULATOR(DUAL TRACKING TYPE)
M5230FP , VARIABLE OUTPUT VOLTAGE REGULATOR(DUAL TRACKING TYPE)
M30LW128D110ZA6-M30LW128D-110ZA6
128 MBIT (TWO 64MBIT, X8/X16, UNIFORM BLOCK, FLASH MEMORIES) 3V SUPPLY, MULTIPLE MEMORY PRODUCT
1/58September 2004
M30LW128D128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories)
3V Supply, Multiple Memory Product
FEATURES SUMMARYTWO M58LW064D 64Mbit FLASH
MEMORIES STACKED IN A SINGLE
PACKAGEWIDE x8 or x16 DATA BUS for HIGH
BANDWIDTHSUPPLY VOLTAGE
–VDD = 2.7 to 3.6V for Program, Erase and
Read operations
–VDDQ = 1.8 to VDD for I/O buffersACCESS TIMERandom Read 110nsPage Mode Read 110/25nsPROGRAMMING TIME16 Word Write Buffer16µs Word effective programming time128 UNIFORM 64 KWord/128KByte
MEMORY BLOCKSBLOCK PROTECTION/ UNPROTECTIONPROGRAM and ERASE SUSPEND128 bit PROTECTION REGISTER COMMON FLASH INTERFACE100, 000 PROGRAM/ERASE CYCLES per
BLOCKELECTRONIC SIGNATUREManufacturer Code: 0020hDevice Code M30LW128D: 8817hPACKAGESCompliant with Lead-Free Soldering
ProcessesLead-Free Versions
M30LW128D
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Figure 2.Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 1.Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 3.TSOP56 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 4.TBGA64 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 5.LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SIGNAL DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Address Inputs (A0-A23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Status/(Ready/Busy) (STS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Program/Erase Enable (VPEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VDD Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VSSQ Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
MEMORY ENABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 2.Single M58LW064D Device Enable, E2, E1 and E0. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 3.M30LW128D Device Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 6.Stacked Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 7.Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Automatic Low Power.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 4.Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3/58
M30LW128DRead Electronic Signature Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Word/Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Write to Buffer and Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Block Protect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Configure STS Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 5.Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 6.Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7.Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 8.Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 8.Word-Wide Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 9.Byte-Wide Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 10.Program/Erase Times and Program/Erase Endurance Cycles. . . . . . . . . . . . . . . . . . . .25
STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Erase Status (Bit 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
VPEN Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 11.Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Table 12.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Table 13.Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 9.AC Measurement Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 10.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 14.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 15.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 11.Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 16.Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 12.Page Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 17.Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 13.Write AC Waveform, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
M30LW128DTable 18.Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 14.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 19.Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 15.Reset, Power-Down and Power-Up AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 20.Reset, Power-Down and Power-Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .36
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37Figure 16.TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . .37
Table 21.TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data.37
Figure 17.TBGA64 - 10x13mm, 8 x 8 ball array 1mm pitch, Package Outline . . . . . . . . . . . . . . . .38
Table 22.TBGA64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, Package Mechanical Data. . . . . . . .38
Figure 18.LFBGA88 8x10 mm - 8x10 ball array, 0.8mm pitch, Bottom View Package Outline. . . .39
Table 23.LFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data . . . . . . .39
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40Table 24.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
APPENDIX A.BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Table 25.Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
APPENDIX B.COMMON FLASH INTERFACE - CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43Table 26.Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 27.CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 28.CFI - Device Voltage and Timing Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 29.Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 30.Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 31.Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
APPENDIX C.FLOW CHARTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47Figure 19.Write to Buffer and Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . .47
Figure 20.Program Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . .48
Figure 21.Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Figure 22.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 23.Block Protect Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Figure 24.Blocks Unprotect Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 25.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . .53
Figure 26.Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . . .54
Figure 27.Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . . .55
Figure 28.Command Interface and Program Erase Controller Flowchart (c).. . . . . . . . . . . . . . . . .56
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57Table 32.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
5/58
M30LW128D
SUMMARY DESCRIPTIONThe M30LW128D is a 128 Mbit device that is com-
posed of two separate 64 Mbit M58LW064D Flash
memories. The device can be erased electrically
at block level and programmed in-system using a
2.7V to 3.6V (VDD) supply for the circuitry and a
1.8V to VDD (VDDQ) supply for the Input/Output
pins.
The bus width can be configured for x8 or x16 for
the devices available in the TSOP56 (14 x 20 mm)
and TBGA64 (10x13mm, 1mm pitch) packages.
The bus width is set to x16 for the devices avail-
able in the LFBGA88 (8x10mm, 0.8mm pitch)
package.
Each internal M58LW064D has 3 Chip Enable sig-
nals to allow up to 4 memories to be connected to-
gether without the use of additional glue logic. In
this way the address space is contiguous and the
microprocessor only requires one Chip Enable, E,
to control both memories.
The device is divided into 128 blocks of 1Mbit (2 x
64 x 1Mb) that can be erased independently so it
is possible to preserve valid data while old data is
erased. Program and Erase commands are written
to the Command Interface of the device. An on-
chip Program/Erase Controller (P/E.C) simplifies
the process of programming or erasing the device
by taking care of all of the special operations that
are required to update the memory contents. The
end of a Program or Erase operation can be de-
tected and any error conditions identified in the
Status Register. The command set required to
control the device is consistent with JEDEC stan-
dards.
The Write Buffer allows the microprocessor to pro-
gram from 1 to 16 Words in parallel, both speeding
up the programming and freeing up the micropro-
cessor to perform other work. A Word Program
command is available to program a single word.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Program can be suspended to Read data
in any other block and then resumed. Each block
can be programmed and erased over 100,000 cy-
cles.
Individual block protection against Program or
Erase is provided for data security. All blocks are
protected during power-up. The protection of the
blocks is non-volatile; after power-up the protec-
tion status of each block is restored to the state
when power was last removed. Software com-
mands are provided to allow protection of some or
all of the blocks and to cancel all block protection
bits simultaneously. All Program or Erase opera-
tions are blocked when the Program Erase Enable
input VPEN is low.
The Reset/Power-Down pin is used to apply a
Hardware Reset to the enabled memory and to set
the device in power-down mode.
The STS signal is an open drain output that can be
used to identify the Program/Erase Controller sta-
tus. It can be configured in two modes: Ready/
Busy mode where a static signal indicates the sta-
tus of the P/E.C, and Status mode where a pulsing
signal indicates the end of a Program or Block
Erase operation. In both modes it can be used as
a system interrupt signal, useful for saving CPU
time. The STS signal is only available with the
TSOP56 and TBGA64 packages.
Each memory includes a 128 bit Protection Regis-
ter. The Protection Register is divided into two 64
bit segments, the first one is written by the manu-
facturer (contact STMicroelectronics to define the
code to be written here), while the second one is
programmable by the user. The user programma-
ble segment can be locked.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
M30LW128D
Table 1. Signal NamesNote:1.A0-A22 for LFBGA package (x16 only), A0 is the least
significant address.A0-A23 for TSOP and TFBGA packages, in x8 mode A0
is the least significant address, in x16 mode A1 is the
least significant address and A0 is don’t care.Not available with LFBGA package.
7/58
M30LW128D
M30LW128D
9/58
M30LW128D
M30LW128D
SIGNAL DESCRIPTIONSSee Figure 2.,Logic Diagram and Table 1.,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A23).The Address Inputs
are used to select the cells to access in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Command Interface.
The device must be enabled (refer to Table
3.,M30LW128D Device Enable) when selecting
the addresses. The address inputs are latched on
the rising edge of Write Enable, W, or Chip En-
able, E, whichever occurs first.
For the TSOP and TFBGA packages the address
inputs are A0-A23. A0 is used to select the higher
or lower byte in x8 mode; it's not used in x16 mode
where A1 is the least significant address.
Address input A23 is used to select between the
two internal memories. When it is High, VIH, it se-
lects the Upper Memory, when it is Low, VIL, it se-
lects the Lower Memory. Refer to Memory Enable
section for more details.
As the LFBGA package only supports x16 mode
this package has all the addresses shifted down
by one with respect to the TSOP and TFBGA
packages. So for the LFBGA package the address
inputs are A0-A22 and address input A22 is used
to select between the two internal memories.
When it is High, VIH, it selects the Upper Memory,
when it is Low, VIL, it selects the Lower Memory.
Refer to Memory Enable section for more details.
Data Inputs/Outputs (DQ0-DQ15).The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. Dur-
ing Bus Write operations they represent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, E, whichever
occurs first.
When the device is enabled and Output Enable is
low, VIL, the data bus outputs data from the mem-
ory array, the Electronic Signature, the Block Pro-
tection status, the CFI Information or the contents
of the Status Register. The data bus is high imped-
ance when the device is deselected, Output En-
able is high, VIH, or the Reset/Power-Down signal
is low, VIL. When the Program/Erase Controller is
active the Ready/Busy status is given on DQ7.
Chip Enable (E).The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. The M30LW128D
stacked memory uses the A23 (A22 for LFBGA
package) address input and the external Chip En-
able, E, to select and enable the internal memo-
ries. Refer to Memory Enable section and Table 3,
for more details.
When the Chip Enable deselects the memory,
power consumption is reduced to the Standby lev-
el, IDD1.
Output Enable (G).The Output Enable, G, gates
the outputs through the data output buffers during
a read operation. When Output Enable, G, is at VIH
the outputs are high impedance.
Write Enable (W).The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able.
Reset/Power-Down (RP).The Reset/Power-
Down signal can be used to apply a Hardware Re-
set to the memory.
A Hardware Reset is achieved by holding Reset/
Power-Down Low, VIL, for at least tPLPH. When
Reset/Power-Down is Low, VIL, the Status Regis-
ter information is cleared and the power consump-
tion is reduced to power-down level. The device is
deselected and outputs are high impedance. If Re-
set/Power-Down goes low, VIL,during a Block
Erase, a Write to Buffer and Program or a Block
Protect/Unprotect the operation is aborted and the
data may be corrupted. In this case the STS pin
stays low, VIL, for a maximum timing of tPLPH + tPH-
BH, until the completion of the Reset/Power-Downpulse.
After Reset/Power-Down goes High, VIH, the de-
vice will be ready for Bus Read and Bus Write op-
erations after tPHQV. Note that STS does not fall
during a reset, see Ready/Busy Output section.
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset opera-
tion occurs while the device is performing an
Erase or Program operation, the device may out-
put the Status Register information instead of be-
ing initialized to the default Asynchronous
Random Read.
Byte/Word Organization Select (BYTE).The
Byte/Word Organization Select signal is used to
switch between the x8 and x16 bus widths of the
memory. When Byte/Word Organization Select is
Low, VIL, the memory is in x8 mode, when it is
High, VIH, the memory is in x16 mode.
The Byte/Word Organization Select signal is not
available with the LFBGA88 package.
11/58
M30LW128D
Status/(Ready/Busy) (STS).The STS signal is
an open drain output that can be used to identify
the Program/Erase Controller status. It can be
configured in two modes: Ready/Busy - the pin is Low, VOL, during
Program and Erase operations and high
impedance when the memory is ready for any
Read, Program or Erase operation. Status - the pin gives a pulsing signal to
indicate the end of a Program or Block Erase
operation.
After power-up or reset the STS pin is configured
in Ready/Busy mode. The pin can be configured
for Status mode using the Configure STS com-
mand.
When the Program/Erase Controller is idle, or sus-
pended, STS can float High through a pull-up re-
sistor. The use of an open-drain output allows the
STS pins from several devices to be connected to
a single pull-up resistor (a Low will indicate that
one, or more, of the memories is busy).
STS is not Low during a reset unless the reset was
applied when the Program/Erase controller was
active.
The STS signal is not available with the LFBGA88
package.
Program/Erase Enable (VPEN).The Program/
Erase Enable input, VPEN, is used to protect all
blocks, preventing Program and Erase operations
from affecting their data.
Program/Erase Enable must be kept High during
all Program/Erase Controller operations, other-
wise the operations is not guaranteed to succeed
and data may become corrupt.
VDD Supply Voltage.VDD provides the power
supply to the internal core of the device. It is the
main power supply for all operations (Read, Pro-
gram and Erase).
VDDQ Supply Voltage.VDDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from VDD. VDDQ can be
tied to VDD or can use a separate supply.
It is recommended to power-up and power-down
VDD and VDDQ together to avoid any condition that
would result in data corruption.
VSS Ground.Ground, VSS, is the reference for
the core power supply. It must be connected to the
system ground.
VSSQ Ground.VSSQ ground is the reference for
the input/output circuitry driven by VDDQ. VSSQ
must be connected to VSS.
Note: Each device in a system should have
VDD and VDDQ decoupled with a 0.1µF ceramic
capacitor close to the pin (high frequency, in-
herently low inductance capacitors should be
as close as possible to the package). See Fig-
ure 10.,AC Measurement Load Circuit.
M30LW128D
MEMORY ENABLEEach internal M58LW064D memory has 3 Chip
Enable signals to allow up to 4 memories to be
connected together without the use of additional
glue logic, see Table 2.,Single M58LW064D De-
vice Enable, E2, E1 and E0. In this way the ad-
dress space is contiguous and the microcontroller
only requires one Chip Enable, E, to control both
memories.
Figure 6 shows how a 128Mbit Stacked Flash
memory is created using two M58LW064D memo-
ries. One of the memories is located in the Upper
Address space and is referred to as the Upper
Memory, the other is located in the lower address
space and is referred to as the Lower Memory, see
Figure 7.,Block Addresses.
The E0, E1 and E2 Chip Enables of each
M58LW064D memory are connected internally, as
shown in Figure 6.
The external signal A23 (A22 for LFBGA package)
is used to select between the Upper and Lower
memories. A23 (A22 for LFBGA) is connected to
E2 of the Upper Memory and to E1 of the Lower
Memory.
E1 of the Upper Memory is always connected to
VDD while E2 of the Lower Memory is always con-
nected to VSS.
The external Chip Enable, E, is used to enable or
disable the memory selected by A23 (A22 for LF-
BGA), see Table 3.,M30LW128D Device Enable.
E is connected to the E0 signal of both memories.
The M30LW128D (TSOP56 and TBGA64 packag-
es only) supports both x8 and x16 bus widths. It is
also possible to have a x32 bus width by connect-
ing two x16 bus width M30LW128D devices to-
gether. Note that the two M30LW128D devices
must use the same E0 as Chip Enable, as E1 and
E2 are not connected internally.
Table 2. Single M58LW064D Device Enable, E2, E1 and E0
Table 3. M30LW128D Device EnableNote:1.UM = Upper Memory, LM = Lower Memory.A22 for LFBGA package.
13/58
M30LW128D
M30LW128D
15/58
M30LW128D
BUS OPERATIONSThere are 6 bus operations that control each mem-
ory. Each of these is described in this section, see
Table 4.,Bus Operations, for a summary.
On Power-up or after a Hardware Reset the device
defaults to Read Array mode (Page Read).
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the device and do
not affect bus operations.
Bus Read.Bus Read operations read from the
memory cells, or specific registers (Electronic Sig-
nature, Status Register, CFI and Block Protection
Status) in the Command Interface.
A valid bus operation involves setting the desired
address on the Address inputs, enabling the de-
vice (refer to Table 3), applying a Low signal, VIL,
to Output Enable and keeping Write Enable High,
VIH.
The Data Inputs/Outputs will output the value, see
Figure 11.,Bus Read AC Waveforms, and Table
16.,Bus Read AC Characteristics, for details of
when the output becomes valid.
Page Read.Page Read operations are used to
read from several addresses within the same
memory page.
Each memory page is a 4 Words or 8 Bytes and
has the same A3-A23 (A2-A22 for LFBGA pack-
age). In x8 mode only A0, A1 and A2 may change,
in x16 mode only A1 and A2 (A0 and A1 for LFB-
GA package) may change.
Valid bus operations are the same as Bus Read
operations but with different timings. The first read
operation within the page has identical timings,
subsequent reads within the same page have
much shorter access times. If the page changes
then the normal, longer timings apply again. See
Figure 12.,Page Read AC Waveforms, and Table
17.,Page Read AC Characteristics for details on
when the outputs become valid.
Bus Write.Bus Write operations write to the
Command Interface in order to send commands to
the device or to latch addresses and input data to
program.
A valid Asynchronous Bus Write operation begins
by setting the desired address on the Address In-
puts and enabling the device (refer to Chip Enable
section).
Both the Address Inputs and Data Input/Outputs
are latched by the Command Interface on the ris-
ing edge of Write Enable or Chip Enable, whichev-
er occurs first.
Output Enable must remain High, VIH, during the
whole Bus Write operation. See Figures 13, and
14, Write AC Waveforms, and Tables 18 and 19,
Write and Chip Enable Controlled Write AC Char-
acteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when the Output Enable
is High.
Standby.When Chip Enable is High, VIH, the de-
vice enters Standby mode and the Data Inputs/
Outputs pins are placed in the high impedance
state regardless of Output Enable or Write Enable.
The Supply Current is reduced to the Standby
Supply Current, IDD1.
During Program or Erase operations the device
will continue to use the Program/Erase Supply
Current, IDD3, for Program or Erase operations un-
til the operation completes.
Automatic Low Power.If there is no change in
the state of the bus for a short period of time during
Asynchronous Bus Read operations the device
enters Auto Low Power mode where the internal
Supply Current is reduced to the Auto-Standby
Supply Current, IDD5. The Data Inputs/Outputs will
still output data if a Bus Read operation is in
progress.
Automatic Low Power is only available in Asyn-
chronous Read modes.
Power-Down.The device is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, IDD2, and the outputs are high impedance,
independent of Chip Enable, Output Enable or
Write Enable.
M30LW128D
Table 4. Bus Operations Note:1.DQ8-DQ15 are High Z in x8 mode.X = Don’t Care VIL or VIH. High = VIH or VHH.A22 for LFBGA package.
17/58
M30LW128D
COMMAND INTERFACEAll Bus Write operations to the device are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. As the device contains two internal memo-
ries care must be taken to issue the commands to
the correct address. Commands issued with A23
(A22 for LFBGA package) High will be addressed
to the Upper Memory, commands issued with A23
(A22 for LFBGA) Low will be addressed to the
Lower Memory.
The Commands are summarized in Table
5.,Commands. Refer to Table 5 in conjunction
with the text descriptions below.
After power-up or a Reset operation the device en-
ters Read mode.
Read Memory Array Command.The Read Mem-
ory Array command is used to return the ad-
dressed internal memory to Read mode.
One Bus Write cycle is required to issue the Read
Memory Array command and return the addressed
internal memory to Read mode. Once the com-
mand is issued the internal memory remains in
Read mode until another command is issued.
From Read mode Bus Read operations will access
the memory arrays. After power-up or a reset the
device (both internal memories) defaults to Read
Array mode (Page Read).
While the Program/Erase Controller is executing a
Program, Erase, Block Protect, Blocks Unprotect
or Protection Register Program operation the de-
vice will not accept the Read Memory Array com-
mand until the operation completes.
Read Electronic Signature Command.The Read
Electronic Signature command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status and the Protection Register.
One Bus Write cycle is required to issue the Read
Electronic Signature command. Once the com-
mand is issued subsequent Bus Read operations
read the Manufacturer Code, the Device Code, the
Block Protection Status or the Protection Register
until another command is issued. Refer to Table
7.,Read Electronic Signature, Tables 8 and 9,
Word and Byte-wide Read Protection Register
and Figure 8.,Protection Register Memory Map
for information on the addresses.
Read Query Command.The Read Query Com-
mand is used to read data from the Common Flash
Interface (CFI) Memory Area. One Bus Write cycle
is required to issue the Read Query Command.
Once the command is issued subsequent Bus
Read operations read from the Common Flash In-
terface Memory Area. See Appendix B, Tables 26,
27, 28, 29, 30 and 31 for details on the information
contained in the Common Flash Interface (CFI)
memory area.
Read Status Register Command.The Read Sta-
tus Register command is used to read the Status
Register. One Bus Write cycle is required to issue
the Read Status Register command. As the device
contains two Status Registers (one for each inter-
nal memory) the command must be issued to the
same address as the previous operation (Block
Erase, Write to Buffer, Word Program etc.). Once
the command is issued subsequent Bus Read op-
erations to the same internal memory (A23 (A22
for LFBGA) Low or A23 (A22 for LFBGA) High de-
pending on where the command was issued to)
read the Status Register until another command is
issued. If the Bus Read operation is issued to the
other internal memory, then the other Status Reg-
ister will be read, giving the status of the last com-
mand issued in the other internal memory.
The Status Register information is present on the
output data bus (DQ1-DQ7) when the device is en-
abled and Output Enable is Low, VIL.
See the section on the Status Register and Table
11 for details on the definitions of the Status Reg-
ister bits
Clear Status Register Command.The Clear Sta-
tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear Status Register
command. The command must be issued to the
same address as the previous operation (Block
Erase, Write to Buffer, Word Program etc.).
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Write to
Buffer and Program, Erase, Block Protect, Block
Unprotect or Protection Register Program com-
mand is issued. If any error occurs then it is essen-
tial to clear any error bits in the Status Register by
issuing the Clear Status Register command before
attempting a new Program, Erase or Resume
command.
Block Erase Command.The Block Erase com-
mand can be used to erase a block. It sets all of
the bits in the block to ‘1’. All previous data in the
block is lost. If the block is protected then the
Erase operation will abort, the data in the block will
not be changed and the Status Register will output
the error.
Two Bus Write operations are required to issue the
command; the second Bus Write cycle latches the
block address in the internal state machine and
starts the Program/Erase Controller. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register. See the section on
the Status Register for details on the definitions of
the Status Register bits.
During Erase, the device being erased will only ac-
cept the Read Status Register and Program/Erase
M30LW128DSuspend commands, ignoring all other com-
mands. The device not being erased will accept
any command. Typical Erase times are given in
Table 10.
See Appendix C, Figure 21.,Erase Flowchart and
Pseudo Code, for a suggested flowchart on using
the Block Erase command.
Word/Byte Program Command.The Word/
Byte Program command is used to program a sin-
gle Word or Byte in the memory array. Two Bus
Write operations are required to issue the com-
mand; the first write cycle sets up the Word Pro-
gram command, the second write cycle latches the
address and data to be programmed in the internal
state machine and starts the Program/Erase Con-
troller.
If the block being programmed is protected an er-
ror will be set in the Status Register and the oper-
ation will abort without affecting the data in the
memory array. The block must be unprotected us-
ing the Blocks Unprotect command.
Write to Buffer and Program Command.The
Write to Buffer and Program command is used to
program the memory array. If the command is is-
sued with A23 (A22 for LFBGA) High the Upper
Memory will be programmed, if the command is is-
sued with A23 (A22 for LFBGA) Low the Lower
Memory will be programmed.
Up to 16 Words/32 Bytes can be loaded into the
Write Buffer and programmed into the memory ar-
ray. Each Write Buffer has the same A5-A23 (A4-
A22 for LFBGA) addresses. In Byte-wide mode
only A0-A4 may change, in Word-wide mode only
A1-A4 (A0-A3 for LFBGA package) may change.
Four successive steps are required to issue the
command.One Bus Write operation is required to set up
the Write to Buffer and Program Command.
Issue the set up command with the selected
memory Block Address where the program
operation should occur (any address in the
block where the values will be programmed
can be used). Any Bus Read operations will
start to output the Status Register after the 1st
cycle.Use one Bus Write operation to write the same
block address along with the value N on the
Data Inputs/Output, where N+1 is the number
of Words/Bytes to be programmed.Use N+1 Bus Write operations to load the
address and data for each Word into the Write
Buffer. The addresses must have the same
A5-A22. Finally, use one Bus Write operation to issue
the final cycle to confirm the command and
start the Program operation.
Invalid address combinations or failing to follow
the correct sequence of Bus Write cycles will set
an error in the Status Register and abort the oper-
ation without affecting the data in the memory ar-
ray. The Status Register should be cleared before
re-issuing the command.
If the block being programmed is protected an er-
ror will be set in the Status Register and the oper-
ation will abort without affecting the data in the
memory array. The block must be unprotected us-
ing the Blocks Unprotect command.
See Appendix C, Figure 19.,Write to Buffer and
Program Flowchart and Pseudo Code, for a sug-
gested flowchart on using the Write to Buffer and
Program command.
Program/Erase Suspend Command.The Pro-
gram/Erase Suspend command is used to pause a
Write to Buffer and Program or Erase operation.
The command will only be accepted during a Pro-
gram or an Erase operation. It can be issued at
any time during an Erase operation but will only be
accepted during a Write to Buffer and Program
command if the Program/Erase Controller is run-
ning.
One Bus Write cycle is required to issue the Pro-
gram/Erase Suspend command and pause the
Program/Erase Controller. The command must be
issued to the same address as the current Pro-
gram or Erase operation. Once the command is is-
sued it is necessary to poll the Program/Erase
Controller Status bit (bit 7) to find out when the
Program/Erase Controller has paused; no other
commands will be accepted until the Program/
Erase Controller has paused. After the Program/
Erase Controller has paused, the device will con-
tinue to output the Status Register until another
command is issued.
During the polling period between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing, it is possible for the op-
eration to complete. Once the Program/Erase
Controller Status bit (bit 7) indicates that the Pro-
gram/Erase Controller is no longer active, the Pro-
gram Suspend Status bit (bit 2) or the Erase
Suspend Status bit (bit 6) can be used to deter-
mine if the operation has completed or is suspend-
ed. For timing on the delay between issuing the
Program/Erase Suspend command and the Pro-
gram/Erase Controller pausing see Table 10.
During Program/Erase Suspend the Read Memo-
ry Array, Read Status Register, Read Electronic
Signature, Read Query and Program/Erase Re-
sume commands will be accepted by the Com-
mand Interface. Additionally, if the suspended
operation was Erase then the Word Program,
Write to Buffer and Program, and Program Sus-
pend commands will also be accepted.
19/58
M30LW128DWhen one of the devices is being Program or
Erase Suspended, any command issued to the
other internal Flash memory will be accepted.
When a program operation is completed inside a
Block Erase Suspend the Read Memory Array
command must be issued to reset the device in
Read mode, then the Erase Resume command
can be issued to complete the whole sequence.
Only the blocks not being erased may be read or
programmed correctly.
See Appendix C, Figure 20.,Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
22.,Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
Program/Erase Resume Command.The Pro-
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after a
Program/Erase Suspend operation has paused it.
One Bus Write cycle is required to issue the Pro-
gram/Erase Resume command. The command
must be issued to the same address as the Pro-
gram/Erase Suspend command. Once the com-
mand is issued subsequent Bus Read operations
read the Status Register.
Block Protect Command.The Block Protect
command is used to protect a block and prevent
Program or Erase operations from changing the
data in it. Two Bus Write cycles are required to is-
sue the Block Protect command; the second Bus
Write cycle latches the block address in the inter-
nal state machine and starts the Program/Erase
Controller. Once the command is issued subse-
quent Bus Read operations read the Status Reg-
ister. See the section on the Status Register for
details on the definitions of the Status Register
bits.
During the Block Protect operation the device will
only accept the Read Status Register command.
All other commands will be ignored. Typical Block
Protection times are given in Table 10.
The Block Protection bits are non-volatile, once
set they remain set through reset and power-
down/power-up. They are cleared by a Blocks Un-
protect command.
See Appendix C, Figure 23.,Block Protect Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Block Protect command.
Blocks Unprotect Command.The Blocks Un-
protect command is used to unprotect all of the
blocks. To unprotect all of the blocks in both of the
internal memories the command must be issued to
both memories, that is first with A23 (A22 for LFB-
GA) Low and then with A23 (A22 for LFBGA) High.
Four Bus Write cycles are required to issue the
Blocks Unprotect command; the first two are writ-
ten with A23 (A22 for LFBGA) Low, the second
two are written with A23 (A22 for LFBGA) High.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits.
During the Blocks Unprotect operation the device
will only accept the Read Status Register com-
mand. All other commands will be ignored. Typical
Block Protection times are given in Table 10.
See Appendix C, Figure 24.,Blocks Unprotect
Flowchart and Pseudo Code, for a suggested flow-
chart on using the Blocks Unprotect command.
Protection Register Program Command.The Protection Register Program command is
used to Program the 64 bit user segment of the
Protection Register. Only the lower address Pro-
tection Register is available to the customer (A23
or A22 Low), the other Protection Register is re-
served.
Two write cycles are required to issue the Protec-
tion Register Program command. The first bus cycle sets up the Protection
Register Program command.The second latches the Address and the Data
to be written to the Protection Register and
starts the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started.
The user-programmable segment can be locked
by programming bit 1 of the Protection Register
Lock location to ‘0’ (see Table 8 and x for Word-
wide and Byte-wide protection addressing). Bit 0
of the Protection Register Lock location locks the
factory programmed segment and is programmed
to ‘0’ in the factory. The locking of the Protection
Register is not reversible, once the lock bits are
programmed no further changes can be made to
the values stored in the Protection Register, see
Figure 8.,Protection Register Memory Map. At-
tempting to program a previously protected Pro-
tection Register will result in a Status Register
error.
The Protection Register Program cannot be sus-
pended. See C, Figure 25.,Protection Register
Program Flowchart and Pseudo Code, for the
flowchart for using the Protection Register Pro-
gram command.
Configure STS Command.The Configure STS command is used to configure
the Status/(Ready/Busy) pin. It has to be config-
ured for both internal memories, that is the com-
mand has to be issued first with A23 (A22 for
LFBGA) Low and then with A23 (A22 for LFBGA)
High. After power-up or reset the STS pin is con-
figured in Ready/Busy mode. The pin can be con-
figured in Status mode using the Configure STS
M30LW128Dcommand (refer to Status/(Ready/Busy) section
for more details.
Four Bus Write cycles are required to issue the
Configure STS command. The first two cycles
must be written with A23 (A22 for LFBGA) Low
and the second two with A23 (A22 for LFBGA)
High.The first bus cycle sets up the Configure STS
command. A23 (A22 for LFBGA) must be Low.The second Bus Write cycle specifies one of
the four possible configurations, A23 (A22 for
LFBGA) must be Low, (refer to Table
6.,Configuration Codes): Ready/Busy modePulse on Erase complete modePulse on Program complete mode Pulse on Erase or Program complete
modeThe third Bus Write cycle re-sets up the
Configure STS command. This time A23 (A22
for LFBGA) must be High.The fourth re-specifies the configuration code
given in the second Bus Write cycle. A23 (A22
for LFBGA) must be High.
The device will not accept the Configure STS com-
mand while the Program/Erase controller is busy
or during Program/Erase Suspend. When STS pin
is pulsing it remains Low for a typical time of
250ns. Any invalid Configuration Code will set an
error in the Status Register.
The Configure STS command is not available with
the LFBGA88 package.
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M30LW128D
Table 5. CommandsNote:1.X Don’t Care; RA Read Address, RD Read Data, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program
Address, PD Program Data, QA Query Address, QD Query Data, BA Any address in Block, PRA Protection register address, PRD
Protection Register Data, CC Configuration Code.A23 (A22 for LFBGA) selects which internal memory will enter Read Query or Read Electronic signature mode. To verify the block
protection in the CFI BA has to be in the internal memory selected by A23 (A22 for LFBGA). To verify the protection of all memory
blocks the command has to be issued with A23 (A22 for LFBGA) both High and Low.Not available with LFBGA88 package.
M30LW128D
Table 6. Configuration CodesNote:1.DQ2-DQ7 are reservedWhen STS pin is pulsing it remains Low for a typical time of 250ns.
Table 7. Read Electronic SignatureNote:1.SBA is the Start Base Address of each block, PRD is Protection Register Data.Base Address, refer to Figure 8 and Tables 8 and 9 for more information. A23 (A22 for LFBGA) must be Low to address the cus-
tomer’s Protection Register. The other Protection Register is reserved.A1-A23 for TFBGA and TSOP; A0-A22 for LFBGA.
23/58
M30LW128D
M30LW128D
Table 9. Byte-Wide Read Protection Register Note:To read the Protection Register, A23 must be VIL.
25/58
M30LW128D
Table 10. Program/Erase Times and Program/Erase Endurance CyclesNote:1.Typical values measured at room temperature and nominal voltages.Sampled, but not 100% tested.Effective byte programming time 6µs, effective word programming time 12µs.Maximum value measured at worst case conditions for both temperature and VDD after 100,000 program/erase cycles.Maximum value measured at worst case conditions for both temperature and VDD.
M30LW128D
STATUS REGISTERThe Status Register provides information on the
current or previous Program, Erase, Block Protect
or Blocks Unprotect operation. The various bits in
the Status Register convey information and errors
on the operation. They are output on DQ7-DQ0.
To read the Status Register the Read Status Reg-
ister command can be issued. The Status Register
is automatically read after Program, Erase, Block
Protect, Blocks Unprotect and Program/Erase Re-
sume commands. As the device contains two Sta-
tus Registers (one for each internal memory) the
Status Register must be read at the same address
as the previous operation.
The contents of the Status Register can be updat-
ed during an Erase or Program operation by tog-
gling the Output Enable pin or by dis-activating
and then reactivating the device (refer to Table 3).
Status Register bits 5, 4, 3 and 1 are associated
with various error conditions and can only be reset
with the Clear Status Register command. The Sta-
tus Register bits are summarized in Table
11.,Status Register Bits. Refer to Table 11 in con-
junction with the following text descriptions.
Program/Erase Controller Status (Bit 7).The Pro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
Low, VOL, the Program/Erase Controller is active
and all other Status Register bits are High Imped-
ance; when the bit is High, VOH, the Program/
Erase Controller is inactive.
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
During Program, Erase, Block Protect and Blocks
Unprotect operations the Program/Erase Control-
ler Status bit can be polled to find the end of the
operation. The other bits in the Status Register
should not be tested until the Program/Erase Con-
troller completes the operation and the bit is High.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status and
Block Protection Status bits should be tested for
errors.
Erase Suspend Status (Bit 6).The Erase Sus-
pend Status bit indicates that an Erase operation
has been suspended and is waiting to be re-
sumed. The Erase Suspend Status should only be
considered valid when the Program/Erase Con-
troller Status bit is High (Program/Erase Controller
inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is Low, VOL,
the Program/Erase Controller is active or has com-
pleted its operation; when the bit is High, VOH, a
Program/Erase Suspend command has been is-
sued and the memory is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status (Bit 5).The Erase Status bit can be
used to identify if the device has failed to verify that
the block has erased correctly or that all blocks
have been unprotected successfully. The Erase
Status bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive).
When the Erase Status bit is Low, VOL, the device
has successfully verified that the block has erased
correctly or all blocks have been unprotected suc-
cessfully. When the Erase Status bit is High, VOH,
the erase operation has failed. Depending on the
cause of the failure other Status Register bits may
also be set to High, VOH.If only the Erase Status bit (bit 5) is set High,
VOH, then the Program/Erase Controller has
applied the maximum number of pulses to the
block and still failed to verify that the block has
erased correctly or that all the blocks have
been unprotected successfully.If the failure is due to an erase or blocks
unprotect with VPEN low, VOL, then VPEN
Status bit (bit 3) is also set High, VOH. If the failure is due to an erase on a protected
block then Block Protection Status bit (bit 1) is
also set High, VOH. If the failure is due to a program or erase
incorrect command sequence then Program
Status bit (bit 4) is also set High, VOH.
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status (Bit 4).The Program Status bit
is used to identify a Program or Block Protect fail-
ure. The Program Status bit should be read once
the Program/Erase Controller Status bit is High
(Program/Erase Controller inactive).
When the Program Status bit is Low, VOL, the de-
vice has successfully verified that the Write Buffer
has programmed correctly or the block is protect-
ed. When the Program Status bit is High, VOH, the
program or block protect operation has failed. De-
pending on the cause of the failure other Status
Register bits may also be set to High, VOH.
27/58
M30LW128DIf only the Program Status bit (bit 4) is set
High, VOH, then the Program/Erase Controller
has applied the maximum number of pulses to
the byte and still failed to verify that the Write
Buffer has programmed correctly or that the
Block is protected.If the failure is due to a program or block
protect with VPEN low, VOL, then VPEN Status
bit (bit 3) is also set High, VOH. If the failure is due to a program on a protected
block then Block Protection Status bit (bit 1) is
also set High, VOH. If the failure is due to a program or erase
incorrect command sequence then Erase
Status bit (bit 5) is also set High, VOH.
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
VPEN Status (Bit 3).The VPEN Status bit can be
used to identify if a Program, Erase, Block Protec-
tion or Block Unprotection operation has been at-
tempted when VPEN is Low, VIL.
When the VPEN Status bit is Low, VOL, no Pro-
gram, Erase, Block Protection or Block Unprotec-
tion operations have been attempted with VPEN
Low, VIL, since the last Clear Status Register com-
mand, or hardware reset. When the VPEN Status
bit is High, VOH, a Program, Erase, Block Protec-
tion or Block Unprotection operation has been at-
tempted with VPEN Low, VIL.
Once set High, the VPEN Status bit can only be re-
set by a Clear Status Register command or a hard-
ware reset. If set High it should be reset before a
new Program, Erase, Block Protection or Block
Unprotection command is issued, otherwise the
new command will appear to fail.
Program Suspend Status (Bit 2).The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended and is waiting to be re-
sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive); after a Program/Erase Suspend
command is issued the device may still complete
the operation rather than entering the Suspend
mode.
When the Program Suspend Status bit is Low,
VOL, the Program/Erase Controller is active or has
completed its operation; when the bit is High, VOH,
a Program/Erase Suspend command has been is-
sued and the device is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Block Protection Status (Bit 1).The Block Pro-
tection Status bit can be used to identify if a Pro-
gram or Erase operation has tried to modify the
contents of a protected block.
When the Block Protection Status bit is Low, VOL,
no Program or Erase operations have been at-
tempted to protected blocks since the last Clear
Status Register command or hardware reset;
when the Block Protection Status bit is High, VOH,
a Program (Program Status bit 4 set High) or
Erase (Erase Status bit 5 set High) operation has
been attempted on a protected block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new Program or Erase command is
issued, otherwise the new command will appear to
fail.
Reserved (Bit 0).Bit 0 of the Status Register is
reserved. Its value should be masked.
M30LW128D
Table 11. Status Register Bits
29/58
M30LW128D
MAXIMUM RATINGStressing the device above the ratings listed in Ta-
ble 12.,Absolute Maximum Ratings, may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 12. Absolute Maximum RatingsNote:1.Maximum one output short-circuited at a time and for no longer than 1 second.Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
