M29W800AT120ZA5T ,8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash MemoryM29W800ATM29W800AB8 Mbit (1Mb x8 or 512Kb x16, Boot Block)Low Voltage Single Supply Flash Memoryn 2 ..
M29W800DB45ZE6E , 8-Mbit (1 Mbit x 8 or 512 Kbits x 16, boot block) 3 V supply flash memory
M29W800DB45ZE6E , 8-Mbit (1 Mbit x 8 or 512 Kbits x 16, boot block) 3 V supply flash memory
M29W800DB70M6 ,8 MBIT (1MB X8 OR 512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Packages–V = 2.7V to 3.6V for Program, Erase CC and Rea ..
M29W800DB70N1 ,8 MBIT (1MB X8 OR 512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYLogic Diagram . . 5Table 1. Signal Names . . 5Figure 3. SO Connections . 6Figur ..
M29W800DB-70N1 ,8 MBIT (1MB X8 OR 512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Packages–V = 2.7V to 3.6V for Program, Erase CC and Rea ..
M51203FP , VOLTAGE COMPARATOR
M51203FP , VOLTAGE COMPARATOR
M51203FP , VOLTAGE COMPARATOR
M51204TL , VOLTAGE COMPARATOR
M51206FP , VOLTAGE COMPARATOR
M51391ASP , PAL/NTSC VIDEO CHROMA DEFLECTION
M29W800AB100M1T-M29W800AB120N6T-M29W800AT120ZA5T
8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash Memory
1/33March 2000
M29W800AT
M29W800AB Mbit (1Mb x8 or 512Kb x16, Boot Block)
Low Voltage Single Supply Flash Memory 2.7Vto 3.6V SUPPLY VOLTAGEfor
PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 80ns PROGRAMMING TIME: 10μs typical PROGRAM/ERASE CONTROLLER (P/E.C.) Program Byte-by-Byteor Word-by-Word Status Register bits and Ready/Busy Output SECURITY PROTECTION MEMORY AREA INSTRUCTION ADDRESS CODING:3 digits MEMORY BLOCKS Boot Block (Topor Bottom location) Parameter and Main blocks BLOCK, MULTI-BLOCK and CHIP ERASE MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES ERASE SUSPEND and RESUME MODES Read and Program another Block during
Erase Suspend LOW POWER CONSUMPTION Stand-by and Automatic Stand-by 100,000 PROGRAM/ERASE CYCLESper
BLOCK 20 YEARS DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M29W800AT: D7h Bottom Device Code, M29W800AB: 5Bh
Figure1. Logic DiagramAI02599
A0-A18
DQ0-DQ14
VCC
M29W800AT
M29W800ABESS
DQ15A–1
BYTE
FBGA
TSOP48(N)x 20mm
SO44(M)
LFBGA48 (ZA)x6 solder balls
M29W800AT, M29W800AB2/33
Figure2. TSOP ConnectionsDQ3
DQ9
DQ2
DQ0
DQ6
DQ13
A17
A10 DQ14
DQ12
DQ10
DQ15A–1
VCC
DQ4
DQ5
DQ7
AI02179
M29W800T
M29W800B 25
DQ8
A18
DQ1
DQ11
A12
A13
A16
A11
BYTE
A15
A14
VSS
VSS
Figure3.SO ConnectionsDQ0
DQ8
VSS
A13
VSS
A14
A15
DQ7
A12
A16
BYTE
DQ15A–1
DQ5DQ2
DQ3
VCCDQ11
DQ4
DQ14
AI02181
M29W800T
M29W800B22DQ1
DQ9
DQ6
DQ13
A11
A10
DQ10
DQ12
A17 A8
A18
Table1. Signal NamesA0-A18 Address Inputs
DQ0-DQ7 Data Input/Outputs, Command Inputs
DQ8-DQ14 Data Input/Outputs
DQ15A–1 Data Input/Outputor Address Input Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output
BYTE Byte/Word Organization
VCC Supply Voltage
VSS Ground Not Connected Internally Don’tUseas Internally Connected
DESCRIPTIONThe M29W800Aisa non-volatilememory that may erased electricallyatthe blockor chip level and
programmed in-systemona Byte-by-Byteor
Word-by-Word basis using onlya single 2.7Vto
3.6V VCC supply.For Program and Erase opera-
tionsthe necessary high voltagesare generated
internally. The device can alsobe programmedin
standard programmers.
The array matrix organisation allows each blockto erased and reprogrammed without affecting
other blocks. Blocks canbe protected against pro-
graming and eraseon programming equipment,
and temporarily unprotectedto make changesin
the application. Each block canbe programmed
and erased over 100,000 cycles.
Instructionsfor Read/Reset, Auto Selectfor read-
ingthe Electronic Signatureor Block Protection
status, Programming, Block and Chip Erase,
Erase Suspend and Resumeare writtentothede-
vicein cyclesof commandstoa Command Inter-
face using standard microprocessor write timings.
The deviceis offeredin TSOP48(12x 20mm),
SO44 and LFBGA480.8 mmball pitch packages.
3/33
M29W800AT, M29W800AB
Figure4. LFBGA Connections (Top view through package)AI006567654321SSDQ15
A–1A15A14A12A13
DQ3DQ11DQ10A18DURB
DQ1DQ9DQ8DQ0A6A17A7EA0 A4A3
DQ2
DQ6DQ13DQ14A10A8A9
DQ4VCCDQ12DQ5DUDURPW
A11 DQ7 A2 VSS
A16 BYTE
Memory BlocksThe devices feature asymmetrically blocked archi-
tecture providing system memory integration. Both
M29W800AT and M29W800AB devices havean
arrayof19 blocks, one Boot Blockof16 KBytesor KWords, two Parameter Blocksof8 KBytesor4
KWords, one Main Blockof32 KBytesor16
KWords and fifteen Main Blocksof64 KBytesor KWords. The M29W800AT hasthe Boot Blockthetopofthe memory address space andthe
M29W800AB locatesthe Boot Block startingatthe
bottom. The memory mapsare showedin Figure
Each block canbe erased separately, any combi-
nationof blocks canbe specifiedfor multi-block
eraseorthe entire chip maybe erased. The Erase
operations are managed automaticallybytheP/
E.C. The block erase operation canbe suspended orderto read fromor programto any blocknot
being erased, and then resumed.
Block protection provides additional data security.
Each block canbe separately protectedor unpro-
tected against Programor Eraseon programming
equipment.All previously protected blocks canbe
temporarily unprotectedinthe application.
OrganisationThe M29W800Ais organisedas1Mx8or 512K
x16 bits selectableby the BYTE signal. When
BYTEis Lowthe Byte-widex8 organisationisse-
lected andthe address lines are DQ15A–1 and
A0-A18. The Data Input/Output signal DQ15A–1
actsas address line A–1 which selectsthe lower upper Byteofthe memory wordfor outputon
DQ0-DQ7, DQ8-DQ14 remainat High impedance.
When BYTE isHighthe memory usesthe address
inputs A0-A18 andthe Data Input/Outputs DQ0-
DQ15. Memorycontrol isprovidedby Chip Enable Output EnableG and Write EnableW inputs. Reset/Block Temporary UnprotectionRP tri-lev- input providesa hardware reset when pulled
Low, and when held High(at VID) temporarilyun-
protects blocks previously protected allowing thembe programed and erased. Erase and Program
operationsare controlledbyan internal Program/
Erase Controller (P/E.C.). Status Register data
outputon DQ7 providesa Data Polling signal, and
DQ6 and DQ2 provide Toggle signalsto indicate
the stateofthe P/E.C operations.A Ready/Busy output indicatesthe completionofthe internal
algorithms.
M29W800AT, M29W800AB4/33
Bus OperationsThe following operations canbe performed using
the appropriate bus cycles: Read (Array, Electron- Signature, Block Protection Status), Write com-
mand, Output Disable, Stan-by, Reset, Block
Protection, Unprotection, Protection Verify, Unpro-
tection Verify and Block Temporary Unprotection.
See Tables5 and6.
Command InterfaceInstructions, madeupof commands writtenincy-
cles,canbe giventothe Program/Erase Controller
througha Command Interface (C.I.). For added
data protection, programor erase execution starts
after4or6 cycles. The first, second, fourth and
fifth cyclesare usedto input Coded cyclestothe
C.I. This Coded sequenceisthe sameforall Pro-
gram/Erase Controller instructions. The ’Com-
mand’ itself andits confirmation, when applicable,
are givenonthe third, fourthor sixth cycles. Any
incorrect commandor any improper commandse-
quencewill resetthe deviceto Read Array mode.
InstructionsSeven instructions are definedto perform Read
Array, Auto Select(to readthe Electronic Signa-
tureor Block Protection Status), Program, Block
Erase, Chip Erase, Erase Suspend and EraseRe-
sume.
The internal P/E.C. automatically handlesall tim-
ing and verificationofthe Program and Eraseop-
erations. The Status Register Data Polling,
Toggle, Errorbits andtheRB output maybe read any time, during programmingor erase,to mon-
itorthe progressofthe operation.
Instructionsare composedofuptosix cycles. The
first two cycles inputa Coded sequencetothe
Command Interface whichis commontoallin-
structions (see Table9).
The third cycle inputsthe instruction set-up com-
mand. Subsequent cycles outputthe addressed
data, Electronic Signatureor Block Protection Sta-
tusfor Read operations. Inorderto give additional
data protection,the instructionsfor Program and
Blockor Chip Erase require further commandin-
puts. Fora Program instruction,the fourth com-
mand cycle inputs the address and datatobe
programmed. Foran Erase instruction (Blockor
Chip), the fourth and fifth cycles inputa further
Coded sequence beforethe Erase confirm com-
mandon the sixth cycle. Erasureofa memory
block maybe suspended,in orderto read data
from another blockorto program datain another
block, and then resumed. When poweris firstap-
pliedorif VCC falls below VLKO,the commandin-
terfaceis resetto Read Array.
Table2. Absolute Maximum Ratings(1)Note:1. Exceptforthe rating ”Operating Temperature Range”, stresses above those listedinthe Table ”Absolute Maximum Ratings”may
cause permanent damagetothe device. Theseare stressratingsonlyand operationofthe deviceat theseorany other conditions
above those indicated inthe Operating sectionsofthis specificationisnot implied. Exposureto Absolute Maximum Rating condi-
tions forextended periods mayaffect device reliability. Referalso totheSTMicroelectronics SURE Programand other relevantqual-
ity documents. Minimum Voltagemay undershootto–2V during transition andforlessthan 20ns during transitions. Dependson range.
Symbol Parameter Value Unit Ambient Operating Temperature(3) –40to85 °C
TBIAS Temperature Under Bias –50to125 °C
TSTG Storage Temperature –65to150 °C
VIO(2) Inputor Output Voltage –0.6to5 V
VCC Supply Voltage –0.6to5 V
V(A9,E, G,RP)(2) A9,E,G,RP Voltage –0.6to 13.5 V
5/33
M29W800AT, M29W800AB
Table3. Top Boot Block Addresses,
M29W800AT Size
(Kbytes)
Address Range
(x8)
Address Range
(x16) 16 FC000h-FFFFFh 7E000h-7FFFFh 8 FA000h-FBFFFh 7D000h-7DFFFh 8 F8000h-F9FFFh 7C000h-7CFFFh 32 F0000h-F7FFFh 78000h-7BFFFh 64 E0000h-EFFFFh 70000h-77FFFh 64 D0000h-DFFFFh 68000h-6FFFFh 64 C0000h-CFFFFh 60000h-67FFFh 64 B0000h-BFFFFh 58000h-5FFFFh 64 A0000h-AFFFFh 50000h-57FFFh 64 90000h-9FFFFh 48000h-4FFFFh 64 80000h-8FFFFh 40000h-47FFFh 64 70000h-7FFFFh 38000h-3FFFFh 64 60000h-6FFFFh 30000h-37FFFh 64 50000h-5FFFFh 28000h-2FFFFh 64 40000h-4FFFFh 20000h-27FFFh 64 30000h-3FFFFh 18000h-1FFFFh 64 20000h-2FFFFh 10000h-17FFFh 64 10000h-1FFFFh 08000h-0FFFFh 64 00000h-0FFFFh 00000h-07FFFh
Table4. Bottom Boot Block Addresses,
M29W800AB Size
(Kbytes)
Address Range
(x8)
Address Range
(x16) 64 F0000h-FFFFFh 78000h-7FFFFh 64 E0000h-EFFFFh 70000h-77FFFh 64 D0000h-DFFFFh 68000h-6FFFFh 64 C0000h-CFFFFh 60000h-67FFFh 64 B0000h-BFFFFh 58000h-5FFFFh 64 A0000h-AFFFFh 50000h-57FFFh 64 90000h-9FFFFh 48000h-4FFFFh 64 80000h-8FFFFh 40000h-47FFFh 64 70000h-7FFFFh 38000h-3FFFFh 64 60000h-6FFFFh 30000h-37FFFh 64 50000h-5FFFFh 28000h-2FFFFh 64 40000h-4FFFFh 20000h-27FFFh 64 30000h-3FFFFh 18000h-1FFFFh 64 20000h-2FFFFh 10000h-17FFFh 64 10000h-1FFFFh 08000h-0FFFFh 32 08000h-0FFFFh 04000h-07FFFh 8 06000h-07FFFh 03000h-03FFFh 8 04000h-05FFFh 02000h-02FFFh 16 00000h-03FFFh 00000h-01FFFh
M29W800AT, M29W800AB6/33
SIGNAL DESCRIPTIONSSee Figure1 and Table1.
Address Inputs (A0-A18). The address inputs
for thememory array arelatched duringa writeop-
erationonthe falling edgeat Chip EnableEor
Write EnableW.In Word-wide organisationthe
address linesare A0-A18,in Byte-wide organisa-
tion DQ15A–1 actsasan additional LSB address
line. WhenA9is raisedto VID, eithera Read Elec-
tronic Signature Manufactureror Device Code,
Block Protection Statusora Write BlockProtection BlockUnprotectionis enabled depending onthe
combination oflevelsonA0,A1,A6, A12and A15.
Data Input/Outputs (DQ0-DQ7). These Inputs/
Outputsare usedinthe Byte-wide and Word-wide
organisations. Theinputis datatobe programmedthe memory arrayora commandtobe writtento
the C.I. Bothare latchedonthe rising edgeof Chip
EnableEor Write EnableW. The outputis data
fromthe Memory Array,the Electronic Signature
Manufactureror Device codes,the Block Protec-
tion Statusorthe Status register Data Pollingbit
DQ7,the Toggle Bits DQ6 and DQ2,the Errorbit
DQ5orthe Erase Timerbit DQ3. Outputsare valid
when Chip EnableE and Output EnableGareac-
tive. The outputis high impedance whenthe chip deselectedor the outputs are disabled and
whenRPisata Low level.
Data Input/Outputs (DQ8-DQ14 and DQ15A–
1). These Inputs/Outputsare additionally usedin
the Word-wide organisation. When BYTEis High
DQ8-DQ14 and DQ15A–1actasthe MSBofthe
Data Inputor Output, functioningas describedfor
DQ0-DQ7 above, and DQ8-DQ15are ’don’t care’
for command inputsor status outputs. When
BYTEis Low, DQ0-DQ14 are high impedance,
DQ15A–1isthe Address A–1 input.
Chip Enable (E). The Chip Enable input acti-
vatesthe memory control logic, input buffers,de-
coders and sense amplifiers.E High deselectsthe
memory and reduces the power consumptionto
the stan-by level.E can alsobe usedto control
writingtothe command register andtothe memo- array, whileW remainsatalow level. The Chip
Enable mustbe forcedtoVID duringthe Block Un-
protection operation.
Output Enable (G). The Output Enable gatesthe
outputs throughthe data buffers duringa readop-
eration. WhenGis Highthe outputsare Highim-
pedance.G mustbe forcedto VID level during
Block Protection and Unprotection operations.
Write Enable (W). This input controls writingto
the Command Register and Address and Data
latches.
Byte/Word Organization Select (BYTE). The BYTE
input selectsthe output configurationforthede-
vice: Byte-wide (x8) modeor Word-wide (x16)
mode. When BYTEis Low,the Byte-wide modeis
selected andthe datais read and programmedon
DQ0-DQ7.In this mode, DQ8-DQ14areat high
impedance and DQ15A–1is the LSB address.
When BYTEis High,the Word-wide modeisse-
lected andthe datais read and programmedon
DQ0-DQ15.
Ready/Busy Output (RB). Ready/Busy is an
open-drain output and givesthe internal stateof
the P/E.C.ofthe device. WhenRBis Low,thede-
viceis Busy witha Programor Erase operation
anditwill not accept any additional programor
erase instructions exceptthe Erase Suspendin-
struction. WhenRBis High,the deviceis readyfor
any Read, Programor Erase operation. TheRB
will alsobe High whenthe memoryisputin Erase
Suspendor Stan-by modes.
Reset/Block Temporary Unprotect Input (RP).TheRP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Resetofthe memoryis achievedby pullingRPto
VILforat least tPLPX. Whenthe reset pulseis giv-
en,ifthe memoryisin Reador Stan-by modes,it
willbe availablefor new operationsin tPHEL after
the rising edgeof RP.Ifthe memoryisin Erase,
Erase Suspendor Program modesthe resetwill
take tPLYH during whichtheRB signalwillbe heldVIL. The endofthe memory resetwillbe indicat-bythe rising edgeof RB.A hardware reset dur-
ingan Eraseor Program operationwill corruptthe
data being programmedor the sector(s) being
erased. See Tables15,16, and Figure11.
Temporary block unprotectionis madeby holdingat VID.In this condition previously protected
blocks canbe programmedor erased. The transi-
tionof RP fromVIHto VID must slower than tPH-
PHH. See Tables17,18, and Figure11. WhenRP returned from VIDtoVIHall blocks temporarily
unprotectedwillbe again protected.
VCC Supply Voltage. The power supplyforall
operations (Read, Program and Erase).
VSS Ground. VSSisthe referenceforall voltage
measurements.
7/33
M29W800AT, M29W800AB
DEVICE OPERATIONSSee Tables5,6 and7.
Read. Read operations are usedto output the
contentsofthe Memory Array,the Electronic Sig-
nature,the Status Registerorthe Block Protection
Status. Both Chip EnableE and Output EnableG
mustbelowin orderto read theoutputofthe mem-
ory.A new operationis initiated eitheronthefol-
lowing edgeof Chip EnableEoron any address
transition withEatVIL.
Write. Write operationsare usedto give Instruc-
tion Commandsto the memoryorto latch input
datatobe programmed.A write operationis initi-
ated when Chip EnableEis Low and Write Enableis Low with Output EnableG High. Addresses
are latchedonthe falling edgeofWorE whichever
occurs last. Commands and Input Data are
latchedonthe rising edgeofWorE whicheveroc-
curs first.
Output Disable. The data outputs are high im-
pedance whenthe Output EnableGis High with
Write EnableW High.
Stan-by. The memoryisin stan-by when Chip
EnableEis High andthe P/E.C.is idle. The power
consumptionis reducedtothe stan-by level and
the outputsare high impedance, independentof
the Output EnableGor Write EnableW inputs.
Automatic Stan-by. After 150nsof bus inactivity
(no address transition, CE= VIL) and when CMOS
levelsare drivingthe addresses,the chip automat-
ically entersa pseudo-stan-by mode where con-
sumptionis reducedtothe CMOS stan-by value,
while outputsstill drivethe bus(ifG= VIL).
Electronic Signature. Two codes identifyingthe
manufacturer andthe devicecanbe read fromthe
memory. The manufacturer’s codefor STMicro-
electronicsis 20h,the device codeis D7hforthe
M29W800AT (Top Boot) and 5Bh for the
M29W800AB (Bottom Boot). These codes allow
programming equipmentor applicationsto auto-
matically match their interfacetothe characteris-
ticsofthe M29W800A. The Electronic Signatureis
outputbya Read operation whenthe voltageap-
pliedtoA9isatVID and address inputsA1is Low.
The manufacturer codeis output whenthe Ad-
dress inputA0is Low andthe device code when
this inputis High. Other Address inputs areig-
nored. The codesare outputon DQ0-DQ7.
The Electronic Signature can also beread, without
raisingA9to VID,by giving the memorytheIn-
struction AS.Ifthe Byte-wide configurationisse-
lected the codes are outputon DQ0-DQ7 with
DQ8-DQ14at High impedance;ifthe Word-wide
configurationis selectedthe codesare outputon
DQ0-DQ7 with DQ8-DQ15at 00h.
Block Protection. Each block canbe separately
protected against Programor Eraseon program-
ming equipment. Block protection provides addi-
tional data security,asit disablesall programor
erase operations. This modeis activated when
bothA9 andGare raisedtoVID andan addressin
the blockis appliedon A12-A18. Block protection initiatedonthe edgeofW fallingto VIL. Thenaf-
tera delayof 100μs,the edgeofW risingtoVIH
ends the protection operations. Block protection
verifyis achievedby bringingG,E,A0 andA6to
VIL andA1to VIH, whileWisatVIH andA9at VID.
Under these conditions, readingthe data output
will yield 01hifthe block definedbythe inputson
A12-A18is protected. Any attemptto programor
erasea protected blockwillbe ignoredbythede-
vice.
Block Temporary Unprotection. Any previously
protected block canbe temporarily unprotectedin
orderto change stored data. The temporaryun-
protection modeis activatedby bringingRPto VID.
Duringthe temporary unprotection modethe pre-
viously protected blocksare unprotected.A block
canbe selected and datacanbe modifiedby exe-
cutingthe Eraseor Program instruction withthe signal heldat VID. WhenRPis returnedto VIH,
allthe previously protected blocksare again pro-
tected.
Block Unprotection.All protected blocks canbe
unprotectedon programming equipmentto allow
updatingofbit contents.All blocks must firstbe
protected beforethe unprotection operation. Block
unprotectionis activated whenA9,G andEareat
VID and A12, A15at VIH. Unprotectionis initiatedthe edgeofW fallingto VIL. Aftera delayof
10ms,the unprotection operationwill end. Unpro-
tection verifyis achievedby bringingG andEto
VIL whileA0isatVIL,A6 andA1areatVIH andA9
remainsat VID.In these conditions, reading the
output datawill yield 00hifthe block definedbythe
inputs A12-A18 has been successfully unprotect-
ed. Each block mustbe separately verifiedby giv-
ingits addressin orderto ensure thatit has been
unprotected.
M29W800AT, M29W800AB8/33
Table5. User Bus Operations(1)Note:1.X=VILorVIH. Block Addressmustbe givenan A12-A18bits.See Table7. Operation performedon programming equipment.
Table6. Read Electronic Signature (followingAS instructionor withA9= VID)
Table7. Read Block Protection withAS Instruction
Operation E G W RP BYTE A0 A1 A6 A9 A12 A15 DQ0-
DQ7
DQ8-
DQ14
DQ15
A–1Read Word VIL VIL VIH VIH VIH A0 A1 A6 A9 A12 A15 Data
Output
Data
Output
Data
Output
Read Byte VIL VIL VIH VIH VIL A0 A1 A6 A9 A12 A15 Data
Output Hi-Z Address
Input
Write Word VIL VIH VIL VIH VIH A0 A1 A6 A9 A12 A15 Data
Input
Data
Input
Data
Input
Write Byte VIL VIH VIL VIH VIL A0 A1 A6 A9 A12 A15 Data
Input Hi-Z Address
Input
Output Disable VIL VIH VIH VIH X XXXX X X Hi-Z Hi-Z Hi-Z
Stan-by VIH XX VIH X XXXX X X Hi-Z Hi-Z Hi-Z
Reset X X X VIL X XXXX X X Hi-Z Hi-Z Hi-Z
Block
Protection(2,4) VIL VID VIL Pulse VIH X XXX VID XX X X X
Blocks
Unprotection(4) VID VID VIL Pulse VIH X XXX VID VIH VIH XX X
Block
Protection
Verify(2,4)
VIL VIL VIH VIH X VIL VIH VIL VID A12 A15
Block
Protect
Status(3)
Block
Unprotection
Verify(2,4)
VIL VIL VIH VIH X VIL VIH VIH VID A12 A15
Block
Protect
Status(3)
Block
Temporary
Unprotection X VID X XXXX X X X X X
Org. Code Device E G W BYTE A0 A1 Other
Addresses
DQ0-
DQ7
DQ8-
DQ14
DQ15
A–1Word-
wide
Manufact.
Code VIL VIL VIH VIH VIL VIL Don’t Care 20h 00h 0
Device
Code
M29W800AT VIL VIL VIH VIH VIH VIL Don’t Care D7h 00h 0
M29W800AB VIL VIL VIH VIH VIH VIL Don’t Care 5Bh 00h 0
Code E G W A0 A1 A12-A18 Other
Addresses DQ0-DQ7Protected Block VIL VIL VIH VIL VIH Block Address Don’t Care 01h
Unprotected Block VIL VIL VIH VIL VIH Block Address Don’t Care 00h
9/33
M29W800AT, M29W800AB
Table8. Commands
Hex Code Command00h Invalid/Reserved
10h Chip Erase Confirm
20h Reserved
30h Block Erase Resume/Confirm
80h Set-up Erase
90h Read Electronic Signature/
Block Protection Status
A0h Program
B0h Erase Suspend
F0h Read Array/Reset
INSTRUCTIONS AND COMMANDSThe Command Interface latches commands writ-
tentothe memory. Instructionsare madeup from
oneor more commandsto perform Read Memory
Array, Read Electronic Signature, Read BlockPro-
tection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
madeof address and data sequences. Thein-
structions require from1to6 cycles,thefirstorfirst
threeof whichare always write operations usedto
initiatethe instruction. Theyare followedby either
further write cyclesto confirmthefirst commandor
executethe command immediately. Commandse-
quencing mustbe followed exactly. Any invalid
combinationof commandswill resetthe deviceto
Read Array. The increased numberof cycles has
been chosento assure maximum data security.In-
structionsare initialisedbytwo initial Coded cycles
which unlockthe Command Interface.In addition,
for Erase, instruction confirmationis again preced-bythetwo Coded cycles.
Status Register BitsP/E.C. statusis indicated during executionby Data
Pollingon DQ7, detectionof Toggleon DQ6 and
DQ2,or Erroron DQ5 and Erase Timer DQ3 bits.
Any read attempt during Programor Erase com-
mand execution will automatically output these
five Status Register bits. The P/E.C. automatically
sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other
bits (DQ0, DQ1 and DQ4)are reservedfor future
use and shouldbe masked. See Tables10 and11.
Data PollingBit (DQ7). When Programmingop-
erationsarein progress,thisbit outputsthe com-
plementof thebit being programmedon DQ7.
During Erase operation,it outputsa’0’. After com-
pletionofthe operation, DQ7will outputthebit last
programmedora’1’ after erasing. Data Pollingis
valid and only effective during P/E.C. operation,
thatis afterthe fourthW pulsefor programmingor
afterthe sixthW pulsefor erase.It mustbe per-
formedatthe address being programmedoratan
address withinthe block being erased.Ifallthe
blocks selectedfor erasureare protected, DQ7willsetto’0’for about 100μs, and then returntothe
previous addressed memory data value. See Fig-
ure13forthe Data Polling flowchart and Figure12
forthe Data Polling waveforms. DQ7will also flag
the Erase Suspend modeby switching from’0’to
’1’atthe startofthe Erase Suspend.In orderto
monitor DQ7inthe Erase Suspend modeanad-
dress withina block being erased mustbe provid-
ed. Fora Read Operationin Erase Suspend
mode, DQ7will output’1’ifthe readis attempteda block being erased andthe data valueon oth- blocks. During Program operationin Erase Sus-
pend Mode, DQ7will havethe same behavioras the normal program execution outsideof the
suspend mode.
ToggleBit (DQ6). When Programmingor Eras-
ing operations arein progress, successiveat-
temptsto read DQ6 will output complementary
data. DQ6will toggle following togglingof eitherG,E whenGis low. The operationis completed
whentwo successive reads yieldthe same output
data. The next read will output thebit last pro-
grammed ora’1’ after erasing. The togglebit DQ6 valid only during P/E.C. operations, thatis after
the fourthW pulsefor programmingor after the
sixthW pulsefor Erase.Ifthe blocks selectedfor
erasureare protected, DQ6will togglefor about
100μs and then return backto Read. DQ6willbe
setto’1’ifa Read operationis attemptedonan
Erase Suspend block. When eraseis suspended
DQ6will toggle during programming operationsin block differenttothe blockin Erase Suspend.Ei-
therEorG togglingwill cause DQ6to toggle. See
Figure14for ToggleBit flowchart and Figure15
for ToggleBit waveforms.
M29W800AT, M29W800AB10/33
Table9. Instructions(1)Note:1. Commandsnot interpretedinthistablewill defaulttoread array mode.Awaitof tPLYH isnecessary aftera Read/Reset commandifthe memorywasinan Erase orProgram mode before starting anynew
operation(see Tables15,16and Figure11).X= Don’t Care.Thefirst cyclesoftheRDorAS instructionsare followedbyread operations.Any numberofread cyclescan occurafterthe com-
mand cycles. Signature AddressbitsA0,A1,atVILwill output Manufacturer code (20h). AddressbitsA0atVIHand A1,atVIL willoutput Device
code. Block Protection Address:A0,at VIL,A1atVIHand A15-A18 withinthe Blockwill outputthe Block Protection status.For Coded cycles address inputs A11-A18aredon’tcare. Optional, additional Blocks addresses mustbe entered withinthe erase timeout delayafterlastwrite entry, timeout statuscanbe
verified throughDQ3 value(see Erase TimerBitDQ3 description). Whenfull commandis entered,readData Pollingor Togglebit
until Eraseis completedor suspended. ReadData Polling, TogglebitsorRBuntil Erase completes.
10. During Erase Suspend, ReadandData Program functionsare allowedin blocksnot being erased.
Mne. Instr. Cyc. 1stCyc. 2ndCyc. 3rdCyc. 4thCyc. 5thCyc. 6thCyc. 7thCyc.(2,4) Read/Reset
Memory Array
Addr.(3,7) X Read Memory Arrayuntilanewwrite cycleis initiated.
Data F0h Addr.(3,7) Byte AAAh 555h AAAh Read Memory Arrayuntilanewwrite cycleis
initiated.
Word 555h 2AAh 555h
Data AAh 55h F0h(4) Auto Select 3+
Addr.(3,7) Byte AAAh 555h AAAh
Read Electronic Signatureor Block Protection
Statusuntil anew writecycleis initiated.SeeNoteand6.
Word 555h 2AAh 555h
Data AAh 55h 90h Program 4
Addr.(3,7) Byte AAAh 555h AAAh Program
Address ReadData Pollingor ToggleBituntil
Program completes.
Word 555h 2AAh 555h
Data AAh 55h A0h Program
Data Block Erase 6
Addr.(3,7) Byte AAAh 555h AAAh AAAh 555h Block
Address
Additional
Block(8)Word 555h 2AAh 555h 555h 2AAh
Data AAh 55h 80h AAh 55h 30h 30h Chip Erase 6
Addr.(3,7) Byte AAAh 555h AAAh AAAh 555h AAAh
Note9Word 555h 2AAh 555h 555h 2AAh 555h
Data AAh 55h 80h AAh 55h 10h(10) Erase
Suspend 1
Addr.(3,7) X Readuntil Toggle stops,thenreadallthedata neededfromany Block(s)
not being erasedthen Resume Erase.Data B0h Erase
Resume 1 Addr.(3,7) X ReadData Pollingor ToggleBitsuntil Erase completesor Eraseis
suspended anothertime.Data 30h
11/33
M29W800AT, M29W800AB
Table10. Status Register BitsNote: Logiclevel’1’is High,’0’is Low.-0-1-0-0-0-1-1-1-0- representbit valuein successive Read operations.
Name Logic Level Definition Note Data
Polling
’1’ Erase Completeor erase block Erase Suspend
Indicatesthe P/E.C. status, check during
Programor Erase,andon completion before
checkingbits DQ5for programor Erase
Success.
’0’ Erase On-going
Program Completeor dataof
non erase block during Erase
Suspend Program On-going ToggleBit
’-1-0-1-0-1-0-1-’ Eraseor Program On-going Successive reads output complementary
dataon DQ6 while Programmingor Erase
operationsare on-going. DQ6 remainsat
constant levelwhen P/E.C.operationsare
completedor Erase Suspendis
acknowledged. Program Complete
’-1-1-1-1-1-1-1-’
Erase Completeor Erase
Suspendon currently
addressed block ErrorBit
’1’ Programor Erase Error Thisbitissetto‘1’inthe caseof
Programmingor Erase failure.’0’ Programor Erase On-going Reserved Erase
TimeBit
’1’ Erase Timeout Period Expired
P/E.C. Erase operationhas started. Only
possible command entryis Erase Suspend
(ES).
’0’ Erase Timeout Period On-going An additional blocktobe erasedin parallel
canbe enteredtothe P/E.C. ToggleBit
’-1-0-1-0-1-0-1-’
Chip Erase, Eraseor Erase
Suspendonthe currently
addressed block.
Erase Errorduetothe currently
addressed block
(when DQ5=‘1’). Indicatesthe erase statusand allowsto
identifythe erased block
Program on-going, Eraseon-
goingon another blockor
Erase Complete Erase Suspend readonnon
Erase Suspend block Reserved Reserved
M29W800AT, M29W800AB12/33
Duringthe second cyclethe Coded cycles consist writingthe data55hat address555hinthe Byte-
wide configuration andat address 2AAhin the
Word-wide configuration.Inthe Byte-wide config-
urationthe address lines A–1to A10are valid,in
Word-wideA0to A11are valid, other address lines
are ’don’t care’. The Coded cycles happenonfirst
and second cyclesofthe command writeoronthe
fourth and fifth cycles.
InstructionsSee Table9.
Read/Reset (RD) Instruction. The Read/Reset
instruction consistsof one write cycle giving the
command F0h.It canbe optionally precededby
the two Coded cycles. Subsequent read opera-
tionswill readthe memory array addressed and
outputthe data read.A wait stateof 10μsis nec-
essary after Read/Reset priorto any valid readif
the memory wasinan Erase mode whentheRD
instructionis given. The Read/Reset commandis
not accepted during Erase and erase Suspend.
Auto Select (AS) Instruction. This instruction
usesthe two Coded cycles followedby one write
cycle givingthe command 90hto address AAAhin
the Byte-wide configurationor address 555hinthe
Word-wide configurationfor command set-up.A
subsequent read will output the manufacturer
code andthe device codeorthe block protection
status dependingonthe levelsofA0 andA1. The
manufacturer code, 20h,is output when thead-
dresses linesA0 andA1are Low, thedevice code,
EEhfor Top Boot, EFhfor Bottom Bootis output
whenA0is High withA1 Low.
TheAS instruction also allows accesstothe block
protection status. After givingtheAS instruction,issettoVIL withA1at VIH, while A12-A18de-
finethe addressofthe blocktobe verified.A read these conditionswill outputa 01hifthe blockis
protected anda 00hifthe blockisnot protected.
Program (PG) Instruction. This instruction uses
four write cycles. Bothfor Byte-wide configuration
andfor Word-wide configuration. The Program
command A0his writtento address AAAhin the
Byte-wide configurationorto address 555hinthe
Word-wide configurationon the third cycle after
two Coded cycles.A fourth write operation latches
the Addressonthe falling edgeofWorE andthe
Datatobe writtenonthe rising edge and startsthe
P/E.C. Read operations outputthe Status Register
bits after the programming has started. Memory
programmingis made onlyby writing’0’in placeof
’1’. Status bits DQ6 and DQ7 determineif pro-
grammingis on-going and DQ5 allows verification any possible error. Programmingatan address
notin blocks being erasedis also possible during
erase suspend.Inthis case, DQ2will toggleatthe
address being programmed.
Table11. Polling and Toggle BitsNote:1. Toggleifthe addressis withina block being erased.
’1’ifthe addressis withina blocknot being erased.
Mode DQ7 DQ6 DQ2Program DQ7 Toggle 1
Erase 0 Toggle Note1
Erase Suspend Read
(in Erase Suspend
block) 1 Toggle
Erase Suspend Read
(outside Erase Suspend
block)
DQ7 DQ6 DQ2
Erase Suspend Program DQ7 Toggle N/A
ToggleBit (DQ2). This togglebit, together with
DQ6, canbe usedto determinethe device status
duringthe Erase operations.Itcan alsobe usedto
identifythe block being erased. During Eraseor
Erase Suspenda read froma block being erased
will cause DQ2to toggle.A read froma blocknot
being erasedwillset DQ2to’1’ during erase and DQ2 during Erase Suspend. During Chip Erase read operationwill cause DQ2to toggleasall
blocksare being erased. DQ2willbesetto ’1’dur-
ing program operation and when eraseis com-
plete. After erase completion andifthe errorbit
DQ5issetto’1’, DQ2will toggleifthe faulty block addressed.
ErrorBit (DQ5). Thisbitissetto’1’bythe P/E.C.
when thereisa failureof programming, block
erase,or chip erase that resultsin invalid datain
the memory block.In caseofan errorin block
eraseor program,the blockin whichthe erroroc-
curredorto whichthe programmed data belongs,
mustbe discarded. The DQ5 failure conditionwill
also appearifa user triesto programa’1’toalo-
cation thatis previously programmedto’0’. Other
Blocks maystillbe used. The errorbit resets after Read/Reset (RD) instruction.In caseof success Programor Erase,the errorbitwillbesetto’0’.
Erase TimerBit (DQ3). Thisbitissetto’0’bythe
P/E.C. when the last block Erase command has
been enteredtothe Command Interface anditis
awaitingthe Erase start. Whenthe erase timeout
periodis finished, after 50μsto 90μs, DQ3 returns’1’.
Coded CyclesThetwo Coded cycles unlockthe Command Inter-
face. Theyare followedbyan input commandora
confirmation command. The Coded cycles consist writingthe data AAhat address AAAhinthe
Byte-wide configuration andat address 555hin
the Word-wide configuration duringthe first cycle.
13/33
M29W800AT, M29W800AB
Figure5.AC Testing Input Output WaveformAI01417
1.5V
Figure6.AC Testing Load CircuitAI01968
0.8V
OUTL= 30pF or100pF includesJIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Table13. Capacitance(1)(TA =25°C,f=1 MHz)
Note: Sampledonly,not 100% tested.
Table14.DC Characteristics(TA=0to 70°C, –20to 85°Cor –40to 85°C; VCC= 2.7Vto 3.6V)
Note:1. Sampledonly,not 100% tested.
Symbol Parameter Test Condition Min Max UnitCIN Input Capacitance VIN =0V 6pF
COUT Output Capacitance VOUT =0V 12 pF
Symbol Parameter Test Condition Min Typ. Max UnitILI Input Leakage Current 0V≤VIN≤VCC ±1 μA
ILO Output Leakage Current 0V≤ VOUT≤ VCC ±1 μA
ICC1 Supply Current (Readby Word) E= VIL,G= VIH,f= 6MHz 310 mA
ICC2 Supply Current (Readby Word) E= VIL,G=VIL,f= 6MHz 4.5 10 mA
ICC3 Supply Current (Stan-by) E=VCC ±0.2V 30 100 μA
ICC4(1) Supply Current
(Programor Erase)
Byte program, Blockor
Chip Erasein progress 20 mA
VIL InputLow Voltage –0.5 0.8 V
VIH Input High Voltage 0.7VCC VCC+0.3 V
VOL OutputLow Voltage IOL= 1.8mA 0.45 V
VOH Output High Voltage CMOS IOH= –100μAVCC –0.4V V
VID A9 Voltage (Electronic Signature) 11.5 12.5 V
IID A9 Current (Electronic Signature) A9=VID 30 100 μA
VLKO(1) Supply Voltage (Eraseand
Program lock-out) 2.0 2.3 V
Table12.AC Measurement ConditionsInput RiseandFall Times ≤10ns
Input Pulse Voltages 0to3V
Inputand Output Timing Ref. Voltages 1.5V
M29W800AT, M29W800AB14/33
Table15. ReadAC Characteristics(TA=0to 70°C, –20to 85°Cor –40to 85°C)
Note:1. Sampledonly,not 100% tested.Gmaybe delayedbyupto tELQV -tGLQVafterthe falling edgeofE without increasing tELQV.Tobe consideredonlyifthe Reset pulseis given whilethe memoryisin Eraseor Program mode.
Symbol Alt Parameter Test
Condition
M29W800AT/ M29W800AB
Unit 90
VCC= 3.0Vto 3.6V= 30pF
VCC= 3.0Vto 3.6V= 30pF
Min Max Min MaxtAVAV tRC Address Validto Next
Address ValidVIL,VIL 80 90 ns
tAVQV tACC Address Validto Output
ValidVIL,VIL 80 90 ns
tAXQX tOH Address Transitionto
Output TransitionVIL,VIL 00 ns
tBHQV tFHQV BYTE Switching Highto
Output Valid 50 50 ns
tBLQZ tFLQZ BYTE Switching Lowto
Output HighZ 50 50 ns
tEHQX tOH Chip Enable Highto Output
Transition G=VIL 00 ns
tEHQZ(1) tHZ Chip Enable Highto Output
Hi-Z G=VIL 30 30 ns
tELBH
tELBL
tELFH
tELFL
Chip Enableto BYTE
Switching Lowor High 55 ns
tELQV(2) tCE Chip EnableLowto Output
Valid G=VIL 80 90 ns
tELQX(1) tLZ Chip EnableLowto Output
Transition G=VIL 00 ns
tGHQX tOH Output Enable Highto
Output Transition E=VIL 00 ns
tGHQZ(1) tDF Output Enable Highto
Output Hi-Z E=VIL 30 30 ns
tGLQV(2) tOE Output Enable Lowto
Output Valid E=VIL 35 35 ns
tGLQX(1) tOLZ Output Enable Lowto
Output Transition E=VIL 00 ns
tPHEL tRH RP Highto Chip Enable
Low 50 50 ns
tPLYH(1,3) tRRB
tREADY RPLowto Read Mode 10 10 μs
tPLPX tRP RP Pulse Width 500 500 ns
15/33
M29W800AT, M29W800AB
Table16. ReadAC Characteristics(TA=0to 70°C, –20to 85°Cor –40to 85°C)
Note:1. Sampledonly,not 100% tested.Gmaybe delayedbyupto tELQV -tGLQVafterthe falling edgeofE without increasing tELQV.Tobe consideredonlyifthe Reset pulseis given whilethe memoryisin Eraseor Program mode.
Symbol Alt Parameter Test
Condition
M29W800AT/ M29W800AB
Unit
100 120
VCC= 2.7Vto 3.6V= 30pF
VCC= 2.7Vto 3.6V= 30pF
Min Max Min MaxtAVAV tRC Address Validto Next
Address ValidVIL,VIL 100 120 ns
tAVQV tACC Address Validto Output
ValidVIL,VIL 100 120 ns
tAXQX tOH Address Transitionto
Output TransitionVIL,VIL 00 ns
tBHQV tFHQV BYTE Switching Highto
Output Valid 50 60 ns
tBLQZ tFLQZ BYTE Switching Lowto
Output HighZ 50 60 ns
tEHQX tOH Chip Enable Highto Output
Transition G=VIL 00 ns
tEHQZ(1) tHZ Chip Enable Highto Output
Hi-Z G=VIL 30 30 ns
tELBH
tELBL
tELFH
tELFL
Chip Enableto BYTE
Switching Lowor High 55 ns
tELQV(2) tCE Chip EnableLowto Output
Valid G=VIL 100 120 ns
tELQX(1) tLZ Chip EnableLowto Output
Transition G=VIL 00 ns
tGHQX tOH Output Enable Highto
Output Transition E=VIL 00 ns
tGHQZ(1) tDF Output Enable Highto
Output Hi-Z E=VIL 30 30 ns
tGLQV(2) tOE Output Enable Lowto
Output Valid E=VIL 40 50 ns
tGLQX(1) tOLZ Output Enable Lowto
Output Transition E=VIL 00 ns
tPHEL tRH RP Highto Chip Enable
Low 50 50 ns
tPLYH(1,3) tRRB
tREADY RPLowto Read Mode 10 10 μs
tPLPX tRP RP Pulse Width 500 500 ns
M29W800AT, M29W800AB16/33
Figure7. Read ModeAC WaveformsAI02182
tAVAV
tAVQV
tAXQX
tELQX
tEHQX
tGLQV
tGLQX
tGHQX
VALID
A0-A18/ A–1 E G DQ0-DQ7/ DQ8-DQ15
tELQV
VALID
ADDRESS
VALID
AND
CHIP
ENABLE
OUTPUT
ENABLE
DATA
VALID
BYTE
tBLQZ
tELBL/tELBH
tEHQZ
tGHQZ
tBHQV
Note:
Write
Enable
(W)
High.
17/33
M29W800AT, M29W800AB
Table17. WriteAC Characteristics,W Controlled(TA=0to 70°C, –20to 85°Cor –40to 85°C)
Note:1. Sampledonly,not 100% tested.This timingisfor Temporary Block Unprotection operation.
Symbol Alt Parameter
M29W800AT/ M29W800AB
Unit 90
VCC= 3.0Vto 3.6V= 30pF
VCC= 3.0Vto 3.6V= 30pF
Min Max Min MaxtAVAV tWC Address Validto Next Address Valid 80 90 ns
tAVWL tAS Address Validto Write EnableLow 0 0 ns
tDVWH tDS Input Validto Write Enable High 35 45 ns
tELWL tCS Chip EnableLowto Write EnableLow 0 0 ns
tGHWL Output Enable Highto Write Enable Low 0 0 ns
tPHPHH(1,2) tVIDR RP Rise TimetoVID 500 500 ns
tPHWL(1) tRSP RP Highto Write EnableLow 4 4 μs
tPLPX tRP RP Pulse Width 500 500 ns
tVCHEL tVCS VCC Highto Chip EnableLow 50 50 μs
tWHDX tDH Write Enable Highto Input Transition 0 0 ns
tWHEH tCH Write Enable Highto Chip Enable High 0 0 ns
tWHGL tOEH Write Enable Highto Output Enable Low 0 0 ns
tWHRL(1) tBUSY Program Erase ValidtoRB Delay 90 90 ns
tWHWL tWPH Write Enable Highto Write EnableLow 30 30 ns
tWLAX tAH Write Enable Lowto Address Transition 45 45 ns
tWLWH tWP Write Enable Lowto Write Enable High 35 35 ns
Block Erase (BE) Instruction. This instruction
usesa minimumofsix write cycles. The Erase
Set-up command 80his writtento address AAAhthe Byte-wide configurationor address 555hin
the Word-wide configurationon third cycle after
the two Coded cycles. The Block Erase Confirm
command 30his similarly written onthe sixth cycle
after anothertwo Coded cycles. Duringthe inputof
the second commandan address withinthe blockbe erasedis given and latched intothe memory.
Additional block Erase Confirm commands and
block addresses canbe written subsequentlyto
erase other blocksin parallel, without further Cod- cycles. The erasewill start afterthe erase tim-
eout period (see Erase TimerBit DQ3 description).
Thus, additional Erase Confirm commandsfor oth- blocks mustbe given withinthis delay. The inputa new Erase Confirm commandwill restartthe
timeout period. The statusofthe internal timer can monitored throughthe levelof DQ3,if DQ3is’0’
the Block Erase Command has been given and
the timeoutis running,if DQ3is’1’,the timeouthas
expired andthe P/E.C.is erasingthe Block(s).If
the second command givenisnotan erase con-
firmorifthe Coded cyclesare wrong,the instruc-
tion aborts, andthe deviceis resetto Read Array.isnot necessaryto programthe block with 00hthe P/E.C.willdo this automatically beforeto
erasingto FFh. Read operations afterthe sixthris-
ing edgeofWorE outputthe status register status
bits.
