M29W800AT ,8 MBIT (1MB X8 OR 512KB X16, BOOT BLOCK) LOW VOLTAGE SINGLE SUPPLY FLASH MEMORYM29W800ATM29W800AB8 Mbit (1Mb x8 or 512Kb x16, Boot Block)Low Voltage Single Supply Flash Memory■ 2 ..
M29W800AT120ZA5T ,8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash MemoryM29W800ATM29W800AB8 Mbit (1Mb x8 or 512Kb x16, Boot Block)Low Voltage Single Supply Flash Memoryn 2 ..
M29W800DB45ZE6E , 8-Mbit (1 Mbit x 8 or 512 Kbits x 16, boot block) 3 V supply flash memory
M29W800DB45ZE6E , 8-Mbit (1 Mbit x 8 or 512 Kbits x 16, boot block) 3 V supply flash memory
M29W800DB70M6 ,8 MBIT (1MB X8 OR 512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Packages–V = 2.7V to 3.6V for Program, Erase CC and Rea ..
M29W800DB70N1 ,8 MBIT (1MB X8 OR 512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYLogic Diagram . . 5Table 1. Signal Names . . 5Figure 3. SO Connections . 6Figur ..
M51203FP , VOLTAGE COMPARATOR
M51203FP , VOLTAGE COMPARATOR
M51203FP , VOLTAGE COMPARATOR
M51204TL , VOLTAGE COMPARATOR
M51206FP , VOLTAGE COMPARATOR
M51391ASP , PAL/NTSC VIDEO CHROMA DEFLECTION
M29W800AB-M29W800AT
8 MBIT (1MB X8 OR 512KB X16, BOOT BLOCK) LOW VOLTAGE SINGLE SUPPLY FLASH MEMORY
1/34June 2001
M29W800AT
M29W800AB8 Mbit (1Mb x8 or 512Kb x16, Boot Block)
Low Voltage Single Supply Flash Memory 2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 80ns PROGRAMMING TIME: 10μs typical PROGRAM/ERASE CONTROLLER (P/E.C.) Program Byte-by-Byte or Word-by-Word Status Register bits and Ready/Busy Output SECURITY PROTECTION MEMORY AREA INSTRUCTION ADDRESS CODING: 3 digits MEMORY BLOCKS Boot Block (Top or Bottom location) Parameter and Main blocks BLOCK, MULTI-BLOCK and CHIP ERASE MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES ERASE SUSPEND and RESUME MODES Read and Program another Block during
Erase Suspend LOW POWER CONSUMPTION Stand-by and Automatic Stand-by 100,000 PROGRAM/ERASE CYCLES per
BLOCK 20 YEARS DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M29W800AT: D7h Bottom Device Code, M29W800AB: 5Bh
Figure 1. Logic Diagram
M29W800AT, M29W800AB
Figure 2. TSOP Connections
Figure 3. SO Connections
Table 1. Signal Names
DESCRIPTIONThe M29W800A is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte or
Word-by-Word basis using only a single 2.7V to
3.6V VCC supply. For Program and Erase opera-
tions the necessary high voltages are generated
internally. The device can also be programmed in
standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase,
Erase Suspend and Resume are written to the de-
vice in cycles of commands to a Command Inter-
face using standard microprocessor write timings.
The device is offered in TSOP48 (12 x 20mm),
SO44 and TFBGA48 0.8 mm ball pitch packages.
3/34
M29W800AT, M29W800AB
Figure 4. TFBGA Connections (Top view through package)A Reset/Block Temporary Unprotection RP tri-lev-
el input provides a hardware reset when pulled
Low, and when held High (at VID) temporarily un-
protects blocks previously protected allowing them
to be programed and erased. Erase and Program
operations are controlled by an internal Program/
Erase Controller (P/E.C.). Status Register data
output on DQ7 provides a Data Polling signal, and
DQ6 and DQ2 provide Toggle signals to indicate
the state of the P/E.C operations. A Ready/Busy
RB output indicates the completion of the internal
algorithms.
OrganisationThe M29W800A is organised as 1M x8 or 512K
x16 bits selectable by the BYTE signal. When
BYTE is Low the Byte-wide x8 organisation is se-
lected and the address lines are DQ15A–1 and
A0-A18. The Data Input/Output signal DQ15A–1
acts as address line A–1 which selects the lower
or upper Byte of the memory word for output on
DQ0-DQ7, DQ8-DQ14 remain at High impedance.
When BYTE is High the memory uses the address
inputs A0-A18 and the Data Input/Outputs DQ0-
DQ15. Memory control is provided by Chip Enable
E, Output Enable G and Write Enable W inputs.
M29W800AT, M29W800AB
Memory BlocksThe devices feature asymmetrically blocked archi-
tecture providing system memory integration. Both
M29W800AT and M29W800AB devices have an
array of 19 blocks, one Boot Block of 16 KBytes or
8 KWords, two Parameter Blocks of 8 KBytes or 4
KWords, one Main Block of 32 KBytes or 16
KWords and fifteen Main Blocks of 64 KBytes or
32 KWords. The M29W800AT has the Boot Block
at the top of the memory address space and the
M29W800AB locates the Boot Block starting at the
bottom. The memory maps are showed in Figure
5.
Each block can be erased separately, any combi-
nation of blocks can be specified for multi-block
erase or the entire chip may be erased. The Erase
operations are managed automatically by the P/
E.C. The block erase operation can be suspended
in order to read from or program to any block not
being erased, and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
Bus OperationsThe following operations can be performed using
the appropriate bus cycles: Read (Array, Electron-
ic Signature, Block Protection Status), Write com-
mand, Output Disable, Stan-by, Reset, Block
Protection, Unprotection, Protection Verify, Unpro-
tection Verify and Block Temporary Unprotection.
See Tables 5 and 6.
Command InterfaceInstructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and
fifth cycles are used to input Coded cycles to the
C.I. This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The ’Com-
mand’ itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset the device to Read Array mode.
Table 2. Absolute Maximum Ratings (1)Note:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions. Depends on range.
5/34
M29W800AT, M29W800AB
Table 3. Top Boot Block Addresses,
M29W800AT
Table 4. Bottom Boot Block Addresses,
M29W800AB
Instructions Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signa-
ture or Block Protection Status), Program, Block
Erase, Chip Erase, Erase Suspend and Erase Re-
sume.
The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase op-
erations. The Status Register Data Polling,
Toggle, Error bits and the RB output may be read
at any time, during programming or erase, to mon-
itor the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all in-
structions (see Table 9).
The third cycle inputs the instruction set-up com-
mand. Subsequent cycles output the addressed
data, Electronic Signature or Block Protection Sta-
tus for Read operations. In order to give additional
data protection, the instructions for Program and
Block or Chip Erase require further command in-
puts. For a Program instruction, the fourth com-
mand cycle inputs the address and data to be
programmed. For an Erase instruction (Block or
Chip), the fourth and fifth cycles input a further
Coded sequence before the Erase confirm com-
mand on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data
from another block or to program data in another
block, and then resumed. When power is first ap-
plied or if VCC falls below VLKO, the command in-
terface is reset to Read Array.
M29W800AT, M29W800AB
SIGNAL DESCRIPTIONSSee Figure 1 and Table 1.
Address Inputs (A0-A18). The address inputs
for the memory array are latched during a write op-
eration on the falling edge at Chip Enable E or
Write Enable W. In Word-wide organisation the
address lines are A0-A18, in Byte-wide organisa-
tion DQ15A–1 acts as an additional LSB address
line. When A9 is raised to VID, either a Read Elec-
tronic Signature Manufacturer or Device Code,
Block Protection Status or a Write Block Protection
or Block Unprotection is enabled depending on the
combination of levels on A0, A1, A6, A12 and A15.
Data Input/Outputs (DQ0-DQ7). These Inputs/
Outputs are used in the Byte-wide and Word-wide
organisations. The input is data to be programmed
in the memory array or a command to be written to
the C.I. Both are latched on the rising edge of Chip
Enable E or Write Enable W. The output is data
from the Memory Array, the Electronic Signature
Manufacturer or Device codes, the Block Protec-
tion Status or the Status register Data Polling bit
DQ7, the Toggle Bits DQ6 and DQ2, the Error bit
DQ5 or the Erase Timer bit DQ3. Outputs are valid
when Chip Enable E and Output Enable G are ac-
tive. The output is high impedance when the chip
is deselected or the outputs are disabled and
when RP is at a Low level.
Data Input/Outputs (DQ8-DQ14 and DQ15A–
1). These Inputs/Outputs are additionally used in
the Word-wide organisation. When BYTE is High
DQ8-DQ14 and DQ15A–1 act as the MSB of the
Data Input or Output, functioning as described for
DQ0-DQ7 above, and DQ8-DQ15 are 'don't care'
for command inputs or status outputs. When
BYTE is Low, DQ0-DQ14 are high impedance,
DQ15A–1 is the Address A–1 input.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E High deselects the
memory and reduces the power consumption to
the stan-by level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at a low level. The Chip
Enable must be forced to VID during the Block Un-
protection operation.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G is High the outputs are High im-
pedance. G must be forced to VID level during
Block Protection and Unprotection operations.
Write Enable (W). This input controls writing to
the Command Register and Address and Data
latches.
Byte/Word Organization Select (BYTE). The BYTE
input selects the output configuration for the de-
vice: Byte-wide (x8) mode or Word-wide (x16)
mode. When BYTE is Low, the Byte-wide mode is
selected and the data is read and programmed on
DQ0-DQ7. In this mode, DQ8-DQ14 are at high
impedance and DQ15A–1 is the LSB address.
When BYTE is High, the Word-wide mode is se-
lected and the data is read and programmed on
DQ0-DQ15.
Ready/Busy Output (RB). Ready/Busy is an
open-drain output and gives the internal state of
the P/E.C. of the device. When RB is Low, the de-
vice is Busy with a Program or Erase operation
and it will not accept any additional program or
erase instructions except the Erase Suspend in-
struction. When RB is High, the device is ready for
any Read, Program or Erase operation. The RB
will also be High when the memory is put in Erase
Suspend or Stan-by modes.
Reset/Block Temporary Unprotect Input (RP).The RP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Reset of the memory is achieved by pulling RP to
VIL for at least tPLPX. When the reset pulse is giv-
en, if the memory is in Read or Stan-by modes, it
will be available for new operations in tPHEL after
the rising edge of RP. If the memory is in Erase,
Erase Suspend or Program modes the reset will
take tPLYH during which the RB signal will be held
at VIL. The end of the memory reset will be indicat-
ed by the rising edge of RB. A hardware reset dur-
ing an Erase or Program operation will corrupt the
data being programmed or the sector(s) being
erased. See Tables 15, 16, and Figure 11.
Temporary block unprotection is made by holding
RP at VID. In this condition previously protected
blocks can be programmed or erased. The transi-
tion of RP from VIH to VID must slower than tPH-
PHH. See Tables 17, 18, and Figure 11. When RPis returned from VID to VIH all blocks temporarily
unprotected will be again protected.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
VSS Ground. VSS is the reference for all voltage
measurements.
7/34
M29W800AT, M29W800AB
DEVICE OPERATIONSSee Tables 5, 6 and 7.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register or the Block Protection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the mem-
ory. A new operation is initiated either on the fol-
lowing edge of Chip Enable E or on any address
transition with E at VIL.
Write. Write operations are used to give Instruc-
tion Commands to the memory or to latch input
data to be programmed. A write operation is initi-
ated when Chip Enable E is Low and Write Enable
W is Low with Output Enable G High. Addresses
are latched on the falling edge of W or E whichever
occurs last. Commands and Input Data are
latched on the rising edge of W or E whichever oc-
curs first.
Output Disable. The data outputs are high im-
pedance when the Output Enable G is High with
Write Enable W High.
Stan-by. The memory is in stan-by when Chip
Enable E is High and the P/E.C. is idle. The power
consumption is reduced to the stan-by level and
the outputs are high impedance, independent of
the Output Enable G or Write Enable W inputs.
Automatic Stan-by. After 150ns of bus inactivity
(no address transition, CE = VIL) and when CMOS
levels are driving the addresses, the chip automat-
ically enters a pseudo-stan-by mode where con-
sumption is reduced to the CMOS stan-by value,
while outputs still drive the bus (if G = VIL).
Electronic Signature. Two codes identifying the
manufacturer and the device can be read from the
memory. The manufacturer’s code for STMicro-
electronics is 20h, the device code is D7h for the
M29W800AT (Top Boot) and 5Bh for the
M29W800AB (Bottom Boot). These codes allow
programming equipment or applications to auto-
matically match their interface to the characteris-
tics of the M29W800A. The Electronic Signature is
output by a Read operation when the voltage ap-
plied to A9 is at VID and address inputs A1 is Low.
The manufacturer code is output when the Ad-
dress input A0 is Low and the device code when
this input is High. Other Address inputs are ig-
nored. The codes are output on DQ0-DQ7.
The Electronic Signature can also be read, without
raising A9 to VID, by giving the memory the In-
struction AS. If the Byte-wide configuration is se-
lected the codes are output on DQ0-DQ7 with
DQ8-DQ14 at High impedance; if the Word-wide
configuration is selected the codes are output on
DQ0-DQ7 with DQ8-DQ15 at 00h.
Block Protection. Each block can be separately
protected against Program or Erase on program-
ming equipment. Block protection provides addi-
tional data security, as it disables all program or
erase operations. This mode is activated when
both A9 and G are raised to VID and an address in
the block is applied on A12-A18. Block protection
is initiated on the edge of W falling to VIL. Then af-
ter a delay of 100μs, the edge of W rising to VIH
ends the protection operations. Block protection
verify is achieved by bringing G, E, A0 and A6 to
VIL and A1 to VIH, while W is at VIH and A9 at VID.
Under these conditions, reading the data output
will yield 01h if the block defined by the inputs on
A12-A18 is protected. Any attempt to program or
erase a protected block will be ignored by the de-
vice.
Block Temporary Unprotection. Any previously
protected block can be temporarily unprotected in
order to change stored data. The temporary un-
protection mode is activated by bringing RP to VID.
During the temporary unprotection mode the pre-
viously protected blocks are unprotected. A block
can be selected and data can be modified by exe-
cuting the Erase or Program instruction with the
RP signal held at VID. When RP is returned to VIH,
all the previously protected blocks are again pro-
tected.
Block Unprotection. All protected blocks can be
unprotected on programming equipment to allow
updating of bit contents. All blocks must first be
protected before the unprotection operation. Block
unprotection is activated when A9, G and E are at
VID and A12, A15 at VIH. Unprotection is initiated
by the edge of W falling to VIL. After a delay of
10ms, the unprotection operation will end. Unpro-
tection verify is achieved by bringing G and E to
VIL while A0 is at VIL, A6 and A1 are at VIH and A9
remains at VID. In these conditions, reading the
output data will yield 00h if the block defined by the
inputs A12-A18 has been successfully unprotect-
ed. Each block must be separately verified by giv-
ing its address in order to ensure that it has been
unprotected.
M29W800AT, M29W800AB
Table 5. User Bus Operations (1)Note:1. X = VIL or VIH. Block Address must be given an A12-A18 bits. See Table 7. Operation performed on programming equipment.
Table 6. Read Electronic Signature (following AS instruction or with A9 = VID)
Table 7. Read Block Protection with AS Instruction
9/34
M29W800AT, M29W800AB
Table 8. Commands
INSTRUCTIONS AND COMMANDSThe Command Interface latches commands writ-
ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Read Block Pro-
tection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences. The in-
structions require from 1 to 6 cycles, the first or first
three of which are always write operations used to
initiate the instruction. They are followed by either
further write cycles to confirm the first command or
execute the command immediately. Command se-
quencing must be followed exactly. Any invalid
combination of commands will reset the device to
Read Array. The increased number of cycles has
been chosen to assure maximum data security. In-
structions are initialised by two initial Coded cycles
which unlock the Command Interface. In addition,
for Erase, instruction confirmation is again preced-
ed by the two Coded cycles.
Status Register BitsP/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mand execution will automatically output these
five Status Register bits. The P/E.C. automatically
sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other
bits (DQ0, DQ1 and DQ4) are reserved for future
use and should be masked. See Tables 10 and 11.
Data Polling Bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programming or
after the sixth W pulse for erase. It must be per-
formed at the address being programmed or at an
address within the block being erased. If all the
blocks selected for erasure are protected, DQ7 will
be set to '0' for about 100μs, and then return to the
previous addressed memory data value. See Fig-
ure 13 for the Data Polling flowchart and Figure 12
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from '0' to
'1' at the start of the Erase Suspend. In order to
monitor DQ7 in the Erase Suspend mode an ad-
dress within a block being erased must be provid-
ed. For a Read Operation in Erase Suspend
mode, DQ7 will output '1' if the read is attempted
on a block being erased and the data value on oth-
er blocks. During Program operation in Erase Sus-
pend Mode, DQ7 will have the same behavior as
in the normal program execution outside of the
suspend mode.
Toggle Bit (DQ6). When Programming or Eras-
ing operations are in progress, successive at-
tempts to read DQ6 will output complementary
data. DQ6 will toggle following toggling of either G,
or E when G is low. The operation is completed
when two successive reads yield the same output
data. The next read will output the bit last pro-
grammed or a '1' after erasing. The toggle bit DQ6
is valid only during P/E.C. operations, that is after
the fourth W pulse for programming or after the
sixth W pulse for Erase. If the blocks selected for
erasure are protected, DQ6 will toggle for about
100μs and then return back to Read. DQ6 will be
set to '1' if a Read operation is attempted on an
Erase Suspend block. When erase is suspended
DQ6 will toggle during programming operations in
a block different to the block in Erase Suspend. Ei-
ther E or G toggling will cause DQ6 to toggle. See
Figure 14 for Toggle Bit flowchart and Figure 15
for Toggle Bit waveforms.
M29W800AT, M29W800AB
Table 9. Instructions (1)Note:1. Commands not interpreted in this table will default to read array mode. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new
operation (see Tables 15, 16 and Figure 11). X = Don’t Care. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-
mand cycles. Signature Address bits A0, A1, at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will output Device
code. Block Protection Address: A0, at VIL, A1 at VIH and A15-A18 within the Block will output the Block Protection status. For Coded cycles address inputs A11-A18 are don’t care. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout statuscan be
verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or Toggle bit
until Erase is completed or suspended. Read Data Polling, Toggle bits or RB until Erase completes.
10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
11/34
M29W800AT, M29W800AB
Table 10. Status Register BitsNote: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
M29W800AT, M29W800ABDuring the second cycle the Coded cycles consist
of writing the data 55h at address 555h in the Byte-
wide configuration and at address 2AAh in the
Word-wide configuration. In the Byte-wide config-
uration the address lines A–1 to A10 are valid, in
Word-wide A0 to A11 are valid, other address lines
are 'don't care'. The Coded cycles happen on first
and second cycles of the command write or on the
fourth and fifth cycles.
InstructionsSee Table 9.
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read. A wait state of 10μs is nec-
essary after Read/Reset prior to any valid read if
the memory was in an Erase mode when the RD
instruction is given. The Read/Reset command is
not accepted during Erase and erase Suspend.
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address AAAh in
the Byte-wide configuration or address 555h in the
Word-wide configuration for command set-up. A
subsequent read will output the manufacturer
code and the device code or the block protection
status depending on the levels of A0 and A1. The
manufacturer code, 20h, is output when the ad-
dresses lines A0 and A1 are Low, the device code,
EEh for Top Boot, EFh for Bottom Boot is output
when A0 is High with A1 Low.
The AS instruction also allows access to the block
protection status. After giving the AS instruction,
A0 is set to VIL with A1 at VIH, while A12-A18 de-
fine the address of the block to be verified. A read
in these conditions will output a 01h if the block is
protected and a 00h if the block is not protected.
Program (PG) Instruction. This instruction uses
four write cycles. Both for Byte-wide configuration
and for Word-wide configuration. The Program
command A0h is written to address AAAh in the
Byte-wide configuration or to address 555h in the
Word-wide configuration on the third cycle after
two Coded cycles. A fourth write operation latches
the Address on the falling edge of W or E and the
Data to be written on the rising edge and starts the
P/E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing '0' in place of
'1'. Status bits DQ6 and DQ7 determine if pro-
gramming is on-going and DQ5 allows verification
of any possible error. Programming at an address
not in blocks being erased is also possible during
erase suspend. In this case, DQ2 will toggle at the
address being programmed.
Table 11. Polling and Toggle BitsNote:1. Toggle if the address is within a block being erased.
’1’ if the address is within a block not being erased.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. It can also be used to
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to '1' during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to '1' dur-
ing program operation and when erase is com-
plete. After erase completion and if the error bit
DQ5 is set to '1', DQ2 will toggle if the faulty block
is addressed.
Error Bit (DQ5). This bit is set to '1' by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
the memory block. In case of an error in block
erase or program, the block in which the error oc-
curred or to which the programmed data belongs,
must be discarded. The DQ5 failure condition will
also appear if a user tries to program a '1' to a lo-
cation that is previously programmed to '0'. Other
Blocks may still be used. The error bit resets after
a Read/Reset (RD) instruction. In case of success
of Program or Erase, the error bit will be set to '0'.
Erase Timer Bit (DQ3). This bit is set to '0' by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 50μs to 90μs, DQ3 returns
to '1'.
Coded CyclesThe two Coded cycles unlock the Command Inter-
face. They are followed by an input command or a
confirmation command. The Coded cycles consist
of writing the data AAh at address AAAh in the
Byte-wide configuration and at address 555h in
the Word-wide configuration during the first cycle.
13/34
M29W800AT, M29W800AB
Figure 5. AC Testing Input Output Waveform
Figure 6. AC Testing Load Circuit
Table 13. Capacitance (1) (TA = 25 °C, f = 1 MHz)Note: Sampled only, not 100% tested.
Table 14. DC Characteristics(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Note:1. Sampled only, not 100% tested.
Table 12. AC Measurement Conditions
M29W800AT, M29W800AB
Table 15. Read AC Characteristics(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Note:1. Sampled only, not 100% tested. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.
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M29W800AT, M29W800AB
Table 16. Read AC Characteristics(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Note:1. Sampled only, not 100% tested. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.
M29W800AT, M29W800AB
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M29W800AT, M29W800AB
Table 17. Write AC Characteristics, W Controlled(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Note:1. Sampled only, not 100% tested. This timing is for Temporary Block Unprotection operation.
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address AAAh
in the Byte-wide configuration or address 555h in
the Word-wide configuration on third cycle after
the two Coded cycles. The Block Erase Confirm
command 30h is similarly written on the sixth cycle
after another two Coded cycles. During the input of
the second command an address within the block
to be erased is given and latched into the memory.
Additional block Erase Confirm commands and
block addresses can be written subsequently to
erase other blocks in parallel, without further Cod-
ed cycles. The erase will start after the erase tim-
eout period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for oth-
er blocks must be given within this delay. The input
of a new Erase Confirm command will restart the
timeout period. The status of the internal timer can
be monitored through the level of DQ3, if DQ3 is ’0’
the Block Erase Command has been given and
the timeout is running, if DQ3 is ’1’, the timeout has
expired and the P/E.C. is erasing the Block(s). If
the second command given is not an erase con-
firm or if the Coded cycles are wrong, the instruc-
tion aborts, and the device is reset to Read Array.
It is not necessary to program the block with 00h
as the P/E.C. will do this automatically before to
erasing to FFh. Read operations after the sixth ris-
ing edge of W or E output the status register status
bits.
