M29W400BT-55N1 ,4 MBIT (512KB X8 OR 256KB X16, BOOT BLOCK) LOW VOLTAGE SINGLE SUPPLY FLASH MEMORYAbsolute Maximum Ratings" maycause permanent damage to the device. These are stress ratings only an ..
M29W400BT-55N1 ,4 MBIT (512KB X8 OR 256KB X16, BOOT BLOCK) LOW VOLTAGE SINGLE SUPPLY FLASH MEMORYAbsolute Maximum Ratings" maycause permanent damage to the device. These are stress ratings only an ..
M29W400BT55N1AT ,4 MBIT (512KB X8 OR 256KB X16, BOOT BLOCK) LOW VOLTAGE SINGLE SUPPLY FLASH MEMORYM29W400BTM29W400BB4 Mbit (512Kb x8 or 256Kb x16, Boot Block)Low Voltage Single Supply Flash Memory■ ..
M29W400BT55N1AT ,4 MBIT (512KB X8 OR 256KB X16, BOOT BLOCK) LOW VOLTAGE SINGLE SUPPLY FLASH MEMORYM29W400BTM29W400BB4 Mbit (512Kb x8 or 256Kb x16, Boot Block)Low Voltage Single Supply Flash Memory■ ..
M29W400BT55N1T ,4 MBIT (512KB X8 OR 256KB X16, BOOT BLOCK) LOW VOLTAGE SINGLE SUPPLY FLASH MEMORYAbsolute Maximum RatingsSymbol Parameter Value UnitAmbient Operating Temperature (Temperature Range ..
M29W400BT-55ZA1 ,4 Mbit (512Kb x8 or 256Kb x16, Boot Block) Low Voltage Single Supply Flash MemoryM29W400BTM29W400BB4 Mbit (512Kb x8 or 256Kb x16, Boot Block)Low Voltage Single Supply Flash Memory■ ..
M50LPW040K1 ,4 Mbit (512K x8, Uniform Block) 3V Supply Low Pin Count Flash MemoryLogic Diagram, and Table 1, Signal Names.be left to float, they should be driven Low, V orIL,Input/ ..
M50LPW040N1 ,4 Mbit (512K x8, Uniform Block) 3V Supply Low Pin Count Flash MemoryLogic Diagram (LPC Interface)tection– Register Based Read and Write Protection– 5 Additional Genera ..
M50LPW080 ,8 MBIT (1MB X8, UNIFORM BLOCK) 3V SUPPLY LOW PIN COUNT FLASH MEMORYLogic Diagram, and Table 1, Signal Names.be left to float, they should be driven Low, V orIL,Input/ ..
M50LPW080 K1 ,8 Mbit (1M x8, Uniform Block) 3V Supply Low Pin Count Flash MemoryLogic Diagram (A/A Mux Interface) . . 7Table 1. Signal Names (LPC Interface) . . . . . . 7 ..
M50LPW080N1 ,8 Mbit (1M x8, Uniform Block) 3V Supply Low Pin Count Flash MemoryFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Packages–V = 3.0 to 3.6V for Program, Erase and CCRead O ..
M50LPW080N5 ,8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash MemoryLogic Diagram (A/A Mux Interface) . . 7Table 1. Signal Names (LPC Interface) . . . . . . 7 ..
M29W400BB-M29W400BB-55M1-M29W400BB55N1-M29W400BB-55N1-M29W400BB70M1-M29W400BB70N1-M29W400BB-70N1-M29W400BB70N6-M29W400BB-70N6-M29W400BT -M29W400BT-55N1-M29W400BT70N1-M29W400BT-70N1-M29W400BT70N6-M29W400BT-70N6
4 MBIT (512KB X8 OR 256KB X16, BOOT BLOCK) LOW VOLTAGE SINGLE SUPPLY FLASH MEMORY
1/25June 2001
M29W400BT
M29W400BB Mbit (512Kb x8 or 256Kb x16, Boot Block)
Low Voltage Single Supply Flash Memory SINGLE2.7to 3.6V SUPPLY VOLTAGEfor
PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 55ns PROGRAMMING TIME 10μsper Byte/Word typical11 MEMORY BLOCKS1 Boot Block (Topor Bottom Location)2 Parameterand8MainBlocks PROGRAM/ERASE CONTROLLER Embedded Byte/Word Program algorithm Embedded Multi-Block/Chip Erase algorithm Status Register Polling and Toggle Bits Ready/Busy OutputPin ERASE SUSPEND and RESUME MODES Read and Program another Block during
Erase Suspend UNLOCK BYPASS PROGRAM COMMAND Faster Production/Batch Programming TEMPORARY BLOCK UNPROTECTION
MODE LOW POWER CONSUMPTION Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLESper
BLOCK20 YEARS DATA RETENTION Defectivity below1 ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 0020h Top Device Code M29W400BT: 00EEh Bottom Device Code M29W400BB: 00EFh
M29W400BT, M29W400BB2/25
Table1. Signal Names
SUMMARY DESCRIPTIONThe M29W400Bisa4 Mbit (512Kbx8or 256Kb
x16) non-volatile memory thatcanbe read, erased
and reprogrammed. These operationscanbe per-
formed usinga single low voltage (2.7to 3.6V)
supply.On power-upthe memory defaultstoits
Read mode whereit canbe readinthe same waya ROMor EPROM. The M29W400Bis fully
backward compatible withthe M29W400.
The memoryis divided into blocks that canbe
erased independentlysoitis possibleto preserve
valid data whileold datais erased. Each blockcan protected independentlyto prevent accidental
Programor Erase commands from modifyingthe
memory. Program and Erase commandsare writ-
tentothe Command Interfaceofthe memory.An
on-chip Program/Erase Controller simplifies the
processof programmingor erasingthe memoryby
taking careofallofthe special operations thatare
requiredto updatethe memory contents. The enda programor erase operation canbe detected
and any error conditions identified. The command
set requiredto controlthe memoryis consistent
with JEDEC standards.
3/25
M29W400BT, M29W400BBThe blocksinthe memoryare asymmetricallyar-
ranged, see Tables3and4, Block Addresses. The
firstorlast64 Kbytes have been divided into four
additional blocks. The16 Kbyte Boot Block canbe
usedfor small initialization codeto startthe micro-
processor,thetwo8 Kbyte Parameter Blocks can usedfor parameter storage andthe remaining
32Kisa small Main Block wherethe application
maybe stored.
Chip Enable, Output Enable and Write Enablesig-
nals control the bus operationof the memory.
They allow simple connectionto most micropro-
cessors, often without additional logic.
The memoryis offeredin TSOP48(12x 20mm),
TFBGA48 (0.8mm pitch) and SO44 packages andis supplied withallthebits erased (setto ’1’).
M29W400BT, M29W400BB4/25
Table2. Absolute Maximum Ratings(1)Note:1. Exceptforthe rating "Operating Temperature Range", stresses above those listedinthe Table "Absolute Maximum Ratings"may
cause permanent damagetothe device. Theseare stress ratingsonlyand operationofthe deviceat theseorany otherconditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposureto Absolute Maximum Rating condi-
tions forextended periodsmay affect device reliability.Referalsotothe STMicroelectronics SUREProgramand otherrelevantqual-
ity documents. Minimum Voltagemay undershootto–2V during transitionandforlessthan20ns during transitions.
Table3. Top Boot Block Addresses
M29W400BT
Table4. Bottom Boot Block Addresses
M29W400BB
5/25
M29W400BT, M29W400BB
SIGNAL DESCRIPTIONSSee Figure1, Logic Diagram, and Table1, Signal
Names,fora brief overviewofthe signals connect-tothis device.
Address Inputs (A0-A17). The Address Inputs
selectthe cellsinthe memory arrayto access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sentto the
Command Interfaceofthe internal state machine.
Data Inputs/Outputs (DQ0-DQ7). TheDataIn-
puts/Outputs outputthe data storedatthe selected
address duringa Bus Read operation. During Bus
Write operations they represent the commands
senttothe Command Interfaceofthe internal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The DataIn-
puts/Outputs outputthe data storedatthe selected
address duringa Bus Read operation when BYTE High, VIH. When BYTEis Low, VIL, these pins
arenot used andare high impedance. During Bus
Write operationsthe Command Register doesnot
use these bits. When readingthe Status Register
thesebits shouldbe ignored.
Data Input/Outputor Address Input (DQ15A-1).When BYTEis High, VIH, thispin behavesasa
Data Input/Output pin (as DQ8-DQ14). When
BYTEis Low, VIL,thispin behavesasan address
pin; DQ15A–1 Lowwill selectthe LSBofthe Wordthe other addresses, DQ15A–1 Highwill select
the MSB. Throughoutthetext consider referencesthe Data Input/Outputto include thispin when
BYTEis High and referencestothe AddressIn-
putsto include thispin when BYTEis Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable,E, activates
the memory, allowing Bus Read and Bus Writeop-
erationstobe performed. When Chip Enableis
High, VIH,all other pinsare ignored.
Output Enable (G). The Output Enable,G, con-
trolsthe Bus Read operationofthe memory.
WriteEnable(W). The Write Enable,W, controls
the Bus Write operationof the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The Re-
set/Block Temporary Unprotectpin canbe usedto
applya Hardware Resettothe memoryorto tem-
porarily unprotectall Blocks that have been pro-
tected. Hardware Resetis achievedby holding Reset/
Block Temporary Unprotect Low, VIL,forat least
tPLPX. After Reset/Block Temporary Unprotect
goes High, VIH,the memorywillbe readyfor Bus
Read and Bus Write operations after tPHELor
tRHEL, whichever occurs last. Seethe Ready/Busy
Output section, Table17 and Figure 12, Reset/
Temporary UnprotectAC Characteristicsfor more
details.
HoldingRPat VIDwill temporarily unprotect the
protected Blocksin the memory. Program and
Erase operationsonall blockswillbe possible.
The transition fromVIHtoVID mustbe slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pinan open-drain output thatcanbe usedto identify
whenthe memory array canbe read. Ready/Busy high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
Aftera Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table17 and Figure
12, Reset/Temporary UnprotectAC Characteris-
tics.
During Programor Erase operations Ready/Busy Low, VOL. Ready/Busywill remain Low during
Read/Reset commandsor Hardware Resets until
the memoryis readyto enter Read mode.
The useofan open-drain output allowsthe Ready/
Busy pins from several memoriestobe connecteda single pull-up resistor.A Lowwill then indicate
that one,or more,ofthe memoriesis busy.
Byte/Word OrganizationSelect (BYTE). The Byte/
Word Organization Selectpinis usedto switchbe-
tweenthe 8-bit and 16-bit Bus modesofthe mem-
ory. When Byte/Word Organization Selectis Low,
VIL,the memoryisin 8-bit mode, whenitis High,
VIH,the memoryisin 16-bit mode.
VCC Supply Voltage. The VCC Supply Voltage
suppliesthe powerforall operations (Read, Pro-
gram, Erase etc.).
The Command Interfaceis disabled whenthe VCC
Supply Voltageis less thanthe Lockout Voltage,
VLKO. This prevents Bus Write operations fromac-
cidentally damaging the data during power up,
power down and power surges.Ifthe Program/
Erase Controlleris programmingor erasing during
this time thenthe operation aborts andthe memo- contents being alteredwillbe invalid. 0.1μF capacitor shouldbe connected between
the VCC Supply Voltagepin andthe VSS Ground
pinto decouplethe current surges fromthe power
supply. The PCB track widths mustbe sufficientto
carry the currents required during program and
erase operations, ICC3.
VSS Ground. The VSS Groundisthe referencefor
all voltage measurements.
M29W400BT, M29W400BB6/25
BUS OPERATIONSTherearefive standardbus operations that control
the device. Theseare Bus Read, Bus Write, Out-
Put Disable, Standby and Automatic Standby. See
Tables5 and6, Bus Operations,fora summary.
Typically glitchesof less than 5nson Chip Enable Write Enableare ignoredbythe memory anddo
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells,or specific registersin the Com-
mand Interface.A valid Bus Read operationin-
volves settingthe desired addressonthe Address
Inputs, applyinga Low signal, VIL,to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputswill outputthe
value, see Figure9, Read ModeAC Waveforms,
and Table14, ReadAC Characteristics,for details whenthe output becomes valid.
Bus Write. Bus Write operations writeto the
Command Interface.A valid Bus Write operation
beginsby settingthe desired addressonthe Ad-
dress Inputs. The Address Inputs are latchedby
the Command Interfaceonthe falling edgeof Chip
Enableor Write Enable, whichever occurs last.
The Data Inputs/Outputsare latchedbythe Com-
mand Interfaceonthe rising edgeof Chip Enable Write Enable, whichever occurs first. OutputEn-
able must remain High, VIH, duringthe whole Bus
Write operation. See Figures10 and11, WriteAC
Waveforms, and Tables15 and 16, Write AC
Characteristics,for detailsofthe timing require-
ments.
Output Disable. The Data Inputs/Outputs arein
the high impedance state when Output Enableis
High, VIH.
Standby. When Chip Enableis High, VIH,the
memory enters Standby mode and the DataIn-
puts/Outputs pins are placedinthe high-imped-
ance state.To reducethe Supply Currenttothe
Standby Supply Current, ICC2, Chip Enable should held within VCC± 0.2V.Forthe Standby current
level see Table13,DC Characteristics.
During programor erase operationsthe memory
will continueto use the Program/Erase Supply
Current, ICC3,for Programor Erase operationsun-
tilthe operation completes.
Table5. Bus Operations, BYTE =VILNote:X= VILorVIH.
Table6. Bus Operations, BYTE =VIHNote:X= VILorVIH.
7/25
M29W400BT, M29W400BB
Automatic Standby.If CMOS levels (VCC ±0.2V)
are usedto drivethe busandthe busis inactivefor
150nsor more the memory enters Automatic
Standby wherethe internal Supply Currentisre-
ducedtothe Standby Supply Current, ICC2.The
Data Inputs/Outputswillstill output dataifa Bus
Read operationisin progress.
Special Bus OperationsAdditional bus operations canbe performedto
readthe Electronic Signature and alsoto apply
and remove Block Protection. These bus opera-
tionsare intendedfor useby programming equip-
ment and are not usually usedin applications.
They requireVIDtobe appliedto some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that canbe readto identify the memory.
These codes canbe readby applyingthe signals
listedin Tables5 and6, Bus Operations.
Block Protection and
Blocks Unprotection. Each
block canbe separately protected against acci-
dental Programor Erase. Protected blocks canbe
unprotectedto allow datatobe changed.
There are two methods availablefor protecting
and unprotectingthe blocks, onefor useon pro-
gramming equipment andthe otherfor in-system
use. For further information referto Application
Note AN1122, Applying Protection and Unprotec-
tionto M29 Series Flash.
COMMAND INTERFACEAll Bus Write operationstothe memoryare inter-
pretedby the Command Interface. Commands
consistof oneor more sequential Bus Write oper-
ations. Failureto observea valid sequenceof Bus
Write operationswill resultinthe memory return-
ingto Read mode. The long command sequences
are imposedto maximize data security.
The address usedforthe commands changesde-
pendingon whetherthe memoryisin 16-bitor8-
bit mode. See either Table7,or8, dependingon
the configuration thatis being used,fora sum-
maryofthe commands.
Read/Reset Command. The Read/Reset com-
mand returnsthe memorytoits Read mode where behaves likea ROMor EPROM.It also resets
the errorsinthe Status Register. Either oneor
three Bus Write operations canbe usedto issue
the Read/Reset command. the Read/Reset commandis issued duringa
Block Erase operationor followinga Programming Erase error then the memory will takeupto
10μsto abort. Duringthe abort periodno valid data
canbe read fromthe memory. Issuinga Read/Re-
set command duringa Block Erase operationwill
leave invalid datainthe memory.
Auto Select Command. The Auto Select com-
mandis usedto readthe Manufacturer Code,the
Device Code and the Block Protection Status.
Three consecutive Bus Write operationsarere-
quiredto issuethe Auto Select command. Once
the Auto Select commandis issuedthe memory
remainsin Auto Select mode until another com-
mandis issued.
From the Auto Select mode the Manufacturer
Code canbe read usinga Bus Read operation
withA0=VIL andA1= VIL. The other addressbits
maybesetto eitherVILor VIH. The Manufacturer
Codefor STMicroelectronicsis 0020h.
The Device Code canbe read usinga Bus Read
operation withA0=VIH andA1= VIL. The other
address bits maybesetto eitherVILor VIH.The
Device Codeforthe M29W400BTis 00EEh and
forthe M29W400BBis 00EFh.
The Block Protection Statusof each block canbe
read usinga Bus Read operation withA0= VIL,= VIH, and A12-A17 specifyingthe addressof
the block. The other addressbits maybesettoei-
therVILor VIH.Ifthe addressed blockis protected
then 01his outputon Data Inputs/Outputs DQ0-
DQ7, otherwise 00his output.
Program Command. The Program command
canbe usedto programa valueto one addressin
the memory arrayata time. The commandre-
quires four Bus Write operations,the final writeop-
eration latchesthe address and datainthe internal
state machine and startsthe Program/Erase Con-
troller.the address fallsina protected block thenthe
Program commandis ignored,the data remains
unchanged. The Status Registeris never read and error conditionis given.
Duringthe program operationthe memorywillig-
noreall commands.Itisnot possibleto issue any
commandto abortor pausethe operation. Typical
program timesare givenin Table9. Bus Readop-
erations duringthe program operationwill output
the Status Registeron the Data Inputs/Outputs.
Seethe sectiononthe Status Registerfor more
details.
Afterthe program operation has completed the
memorywill returntothe Read mode, unlessan
error has occurred. Whenan error occurs the
memorywill continueto outputthe Status Regis-
ter.A Read/Reset command mustbe issuedtore-
setthe error condition and returnto Read mode.
Note thatthe Program command cannot changea
bitsetat’0’ backto’1. Oneofthe Erase Com-
mands mustbe usedtosetallthebitsina blockorthe whole memory from’0’to’1’.
M29W400BT, M29W400BB8/25
Table7. Commands, 16-bit mode, BYTE =VIH
Table8. Commands, 8-bit mode, BYTE =VILNote:X Don’t Care,PA Program Address,PD Program Data,BAAny addressinthe Block.
All valuesinthetablearein hexadecimal.
The Command Interface usesA–1, A0-A10andto verifythe commands; A11-A17, DQ8-DQ14and DQ15are Don’t Care.
DQ15A–1isA–1 when BYTEisVILor DQ15 when BYTEisVIH.
Read/Reset.Aftera Read/Reset command,readthe memoryas normaluntil another commandis issued.
Auto Select.AfteranAuto Select command,read ManufacturerID, DeviceIDor Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase.After these commandsreadthe Status Registeruntilthe Program/Erase
Controller completesandthe memory returnsto Read Mode.Add additional Blocks during Block Erase Commandwith additionalBus Write
Operationsuntil TimeoutBitisset.
Unlock Bypass.Afterthe Unlock Bypass command issue Unlock Bypass Programor Unlock Bypass Reset commands.
Unlock Bypass Reset.Afterthe Unlock Bypass Reset commandreadthe memoryas normaluntil another commandis issued.
Erase Suspend. AftertheErase Suspend commandread non-erasingmemory blocksas normal, issueAuto Selectand Program commands non-erasing blocksas normal.
Erase Resume.Afterthe Erase Resume commandthe suspended Erase operation resumes,readthe Status Registeruntilthe Program/
Erase Controller completesandthe memory returnsto Read Mode.
9/25
M29W400BT, M29W400BB
Unlock Bypass Command. The Unlock Bypass
commandis usedin conjunction withthe Unlock
Bypass Program commandto programthe memo-
ry. Whenthe access timetothe deviceis long(as
with some EPROM programmers) considerable
time saving canbe madeby using these com-
mands. Three Bus Write operationsare required issuethe Unlock Bypass command.
Oncethe Unlock Bypass command has beenis-
suedthe memorywill only acceptthe UnlockBy-
pass Program command andthe Unlock Bypass
Reset command. The memory canbe readasifin
Read mode.
Unlock Bypass Program Command. The Un-
lock Bypass Program command canbe usedto
program one addressin memoryata time. The
command requires two Bus Write operations,the
final write operation latchesthe address and datathe internal state machine and startsthe Pro-
gram/Erase Controller.
The Program operation usingthe Unlock Bypass
Program command behaves identicallytothe Pro-
gram operation using the Program command.A
protected block cannotbe programmed;the oper-
ation cannotbe aborted andthe Status Registeris
read. Errors mustbe reset usingthe Read/Reset
command, which leavesthe devicein UnlockBy-
pass Mode. Seethe Program commandfor detailsthe behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command canbe usedto returnto
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operationsare requiredto issuethe
Unlock Bypass Reset command.
Chip Erase Command. The Chip Erase com-
mand canbeusedtoerase theentirechip.Six Bus
Write operations are requiredto issuethe Chip
Erase Command and start the Program/Erase
Controller. any blocksare protected then theseare ignored
andall the other blocks are erased.Ifallofthe
blocksare protectedthe Chip Erase operationap-
pearsto startbutwill terminate within about 100μs,
leavingthe data unchanged.No error conditionis
given when protected blocksare ignored.
Duringthe erase operationthe memorywill ignore
all commands.Itisnot possibleto issue any com-
mandto abortthe operation. Typical chip erase
times are givenin Table9.All Bus Read opera-
tions duringthe Chip Erase operationwill output
the Status Registeron the Data Inputs/Outputs.
Seethe sectiononthe Status Registerfor more
details.
Afterthe Chip Erase operation has completedthe
memorywill returntothe Read Mode, unlessan
error has occurred. Whenan error occurs the
memorywill continueto outputthe Status Regis-
ter.A Read/Reset command mustbe issuedtore-
setthe error condition and returnto Read Mode.
The Chip Erase Command setsallofthebitsinun-
protected blocksofthe memoryto’1’.All previous
datais lost.
Block Erase Command. TheBlock Erasecom-
mand can beusedtoerase alistof oneor more
blocks.Six Bus Write operationsare requiredto
selectthe first blockinthe list. Each additional
blockinthelist canbe selectedby repeatingthe
sixth Bus Write operation usingthe addressofthe
additional block. The Block Erase operation starts
the Program/Erase Controller about 50μs afterthe
last Bus Write operation. Oncethe Program/Erase
Controller startsitis not possibleto select any
more blocks. Each additional block must therefore selected within 50μsofthelast block. The 50μs
timer restarts whenan additional blockis selected.
The Status Register canbe read afterthe sixth
Bus Write operation. Seethe Status Registerfor
detailson howto identifyif the Program/Erase
Controller has startedthe Block Erase operation.any selected blocksare protected then theseare
ignored andall the other selected blocks are
erased.Ifallofthe selected blocksare protected
the Block Erase operation appearsto startbutwill
terminate within about 100μs, leavingthe dataun-
changed.No error conditionis given when protect- blocksare ignored.
Duringthe Block Erase operationthe memorywill
ignoreall commands exceptthe Erase Suspend
and Read/Reset commands. Typical block erase
times are givenin Table9.All Bus Read opera-
tions duringthe Block Erase operationwill output
the Status Registeron the Data Inputs/Outputs.
Seethe sectiononthe Status Registerfor more
details.
Afterthe Block Erase operation has completedthe
memorywill returntothe Read Mode, unlessan
error has occurred. Whenan error occurs the
memorywill continueto outputthe Status Regis-
ter.A Read/Reset command mustbe issuedtore-
setthe error condition and returnto Read mode.
The Block Erase Command setsallofthe bitsin
the unprotected selected blocksto’1’.All previous
datainthe selected blocksis lost.
M29W400BT, M29W400BB10/25
Erase Suspend Command. The Erase Suspend
Command maybe usedto temporarily suspenda
Block Erase operation and returnthe memoryto
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controllerwill suspend within
15μsofthe Erase Suspend Command beingis-
sued. Once the Program/Erase Controller has
stoppedthe memorywillbesetto Read mode and
the Erasewillbe suspended.Ifthe Erase Suspend
commandis issued during the period whenthe
memoryis waitingforan additional block (before
the Program/Erase Controller starts) then the
Eraseis suspended immediately andwill startim-
mediately whenthe Erase Resume Commandis
issued.Itwillnotbe possibleto select any further
blocksfor erasure afterthe Erase Resume.
During Erase Suspenditis possibleto Read and
Program cellsin blocks thatarenot being erased;
both Read and Program operations behaveas
normalon these blocks. Reading from blocks that
are being erasedwill outputthe Status Register.It also possibleto enterthe Auto Select mode:the
memorywill behaveasinthe Auto Select modeon
all blocks untila Read/Reset command returnsthe
memoryto Erase Suspend mode.
Erase Resume Command. The Erase Resume
command mustbe usedto restartthe Program/
Erase Controller from Erase Suspend.An erase
canbe suspended and resumed more than once.
Table9. Program, Erase Times and Program, Erase Endurance Cycles(TA=0to 70°Cor –40to 85°C)
Note:1.TA =25°C,VCC =3.3V.
11/25
M29W400BT, M29W400BB
STATUS REGISTERBus Read operations from any address always
read the Status Register during Program and
Erase operations.Itis also read during Erase Sus-
pend whenan address withina block being erased accessed.
Thebitsinthe Status Registerare summarizedin
Table10, Status Register Bits.
Data PollingBit (DQ7). The Data PollingBit can usedto identify whether the Program/Erase
Controller has successfully completedits opera-
tionorifit has respondedtoan Erase Suspend.
The Data PollingBitis outputon DQ7 whenthe
Status Registeris read.
During Program operations the Data PollingBit
outputs the complementof thebit being pro-
grammedto DQ7. After successful completionof
the Program operation the memory returnsto
Read mod and Bus Read operations fromthead-
dress just programmed output DQ7,notits com-
plemente.
During Erase operationsthe Data PollingBit out-
puts’0’,the complementof the erased stateof
DQ7. After successful completionofthe Eraseop-
erationthe memory returnsto Read Mode. Erase Suspend modethe Data PollingBitwill
outputa’1’ duringa Bus Read operation withina
block being erased. The Data PollingBit will
change froma’0’toa’1’ whenthe Program/Erase
Controller has suspendedthe Erase operation.
Figure5, Data Polling Flowchart, givesan exam-
pleof howto usethe Data PollingBit.A ValidAd-
dressis the address being programmedoran
address withinthe block being erased.
ToggleBit (DQ6). The ToggleBit canbe usedto
identify whetherthe Program/Erase Controllerhas
successfully completedits operationorifithasre-
spondedtoan Erase Suspend. The ToggleBitis
outputon DQ6 whenthe Status Registeris read.
During Program and Erase operationsthe Toggle
Bit changes from’0’to’1’to’0’, etc., with succes-
sive Bus Read operationsat any address. After
successful completionofthe operationthe memo- returnsto Read mode.
During Erase Suspend modethe ToggleBitwill
output when addressingacell withina block being
erased. The ToggleBitwill stop toggling whenthe
Program/Erase Controller has suspended the
Erase operation.
Figure6, Data Toggle Flowchart, givesan exam-
pleof howto usethe Data ToggleBit.
ErrorBit (DQ5). TheErrorBit canbeusedto
identify errors detectedby the Program/Erase
Controller. The ErrorBitissetto’1’ whena Pro-
gram, Block Eraseor Chip Erase operation failsto
writethe correct datatothe memory.Ifthe Error
Bitisseta Read/Reset command mustbe issued
before other commandsare issued. The Errorbit outputon DQ5 whenthe Status Registeris read.
Note thatthe Program command cannot changea
bitsetat’0’ backto’1’ and attemptingtodoso may maynotset DQ5at’1’.In both cases,a succes-
sive Bus Read operationwill showthebitisstill’0’.
Oneofthe Erase commands mustbe usedtoset
allthe bitsina blockorinthe whole memory from
’0’to’1’.
Table10. Status Register BitsNote: Unspecifieddatabits shouldbe ignored.
M29W400BT, M29W400BB12/25
Erase TimerBit (DQ3). The Erase TimerBit can usedto identify the startof Program/Erase
Controller operation duringa Block Erase com-
mand. Oncethe Program/Erase Controller starts
erasingthe Erase TimerBitissetto’1’. Beforethe
Program/Erase Controller startsthe Erase Timer
Bitissetto’0’ and additional blockstobe erased
maybe writtento the Command Interface. The
Erase TimerBitis outputon DQ3 whenthe Status
Registeris read.
Alternative ToggleBit (DQ2). The Alternative
ToggleBit canbe usedto monitorthe Program/
Erase controller during Erase operations. TheAl-
ternative ToggleBitis outputon DQ2 whenthe
Status Registeris read.
During Chip Erase and Block Erase operationsthe
ToggleBit changes from’0’to’1’to’0’, etc., with
successive Bus Read operations from addresses
withinthe blocks being erased. Once theoperation
completesthe memory returnsto Read mode.
During Erase Suspendthe Alternative ToggleBit
changes from’0’to’1’to’0’, etc. with successive
Bus Read operations from addresses withinthe
blocks being erased. Bus Read operationstoad-
dresses within blocksnot being erasedwill output
the memorycell dataasifin Read mode.
Afteran Erase operation that causesthe ErrorBitbesetthe AlternativeToggleBit canbeusedto
identify which blockor blocks have causedtheer-
ror. The Alternative ToggleBit changes from’0’to
’1’to’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that havenot
erased correctly. The Alternative ToggleBit does
not changeifthe addressed blockhas erased cor-
rectly.
13/25
M29W400BT, M29W400BB
Table12. Capacitance(TA =25°C,f= 1MHz)
Note: Sampledonly,not 100% tested.
Table11.AC Measurement Conditions
