M29W320DT ,32 MBIT (4MB X8 OR 2MB X16 BOOT BLOCK) 3V SUPPLY FLASH MEMORYTABLE OF CONTENTSSUMMARY DESCRIPTION . . . 5Figure 2.
M29W320DT ,32 MBIT (4MB X8 OR 2MB X16 BOOT BLOCK) 3V SUPPLY FLASH MEMORYM29W320DTM29W320DB32 Mbit (4Mb x8 or 2Mb x16, Boot Block)3V Supply Flash Memory
M29W320DT ,32 MBIT (4MB X8 OR 2MB X16 BOOT BLOCK) 3V SUPPLY FLASH MEMORYAbsolute Maximum Ratings 21DC and AC PARAMETERS . 22Table 9. Operating and AC Measuremen ..
M29W320DT- - 70N6 ,32 Mbit 4Mb x8 or 2Mb x16, Boot Block 3V Supply Flash MemoryAbsolute Maximum Ratings 22DC and AC PARAMETERS . 23Table 9. Operating and AC Measuremen ..
M29W320DT70N1 ,32 Mbit 4Mb x8 or 2Mb x16, Boot Block 3V Supply Flash MemoryLogic Diagram . . 3Table 1. Signal Names . . 3Figure 3. TSOP Connections . . . ..
M29W320DT70N1T ,32 Mbit 4Mb x8 or 2Mb x16, Boot Block 3V Supply Flash MemoryFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Packages–V = 2.7V to 3.6V for Program, Erase and CC Rea ..
M50FLW040A ,4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash MemoryLogic Diagram (A/A Mux Interface) . . 7Table 1. Signal Names (FWH/LPC Interface) . 7Table ..
M50FLW040AK5G ,4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memoryapplications– 5 Signal Communication Interface supporting Read and Write Operations– 5 Additional G ..
M50FLW040B ,4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash MemoryFEATURES SUMMARY FLASH MEMORY Figure 1. Packages– Compatible with either the LPC interface or the ..
M50FLW080AK5 ,8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash MemoryLogic Diagram (A/A Mux Interface) . . 7Table 1. Signal Names (FWH/LPC Interface) . 7Table ..
M50FLW080AK5G ,8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash MemoryFEATURES SUMMARY . . . . . 1Figure 1. Packages . . . . . . 1SUMMARY DESCRIPTION ..
M50FLW080AN5 ,8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memoryapplications– 5 Signal Communication Interface supporting Read and Write Operations– 5 Additional G ..
M29W320DB-M29W320DT
32 MBIT (4MB X8 OR 2MB X16 BOOT BLOCK) 3V SUPPLY FLASH MEMORY
1/43November 2002
M29W320DT
M29W320DB32 Mbit (4Mb x8 or 2Mb x16, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY SUPPLY VOLTAGE
–VCC= 2.7V to 3.6V for Program, Erase and
Read
–VPP =12V for Fast Program (optional) ACCESS TIME: 70, 90ns PROGRAMMING TIME 10μs per Byte/Word typical 67 MEMORY BLOCKS 1 Boot Block (Top or Bottom Location) 2 Parameter and 64 Main Blocks PROGRAM/ERASE CONTROLLER Embedded Byte/Word Program algorithms ERASE SUSPEND and RESUME MODES Read and Program another Block during
Erase Suspend UNLOCK BYPASS PROGRAM COMMAND Faster Production/Batch Programming VPP/WP PIN for FAST PROGRAM and WRITE
PROTECT TEMPORARY BLOCK UNPROTECTION
MODE COMMON FLASH INTERFACE 64 bit Security Code LOW POWER CONSUMPTION Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 0020h Top Device Code M29W320DT: 22CAh Bottom Device Code M29W320DB: 22CBh
Figure 1. Packages
M29W320DT, M29W320DB
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 5. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 6. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VCC Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 2. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 3. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3/43
M29W320DT, M29W320DBChip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 4. Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 5. Commands, 8-bit mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . .18
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 7. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 8. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 11. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 12. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 13. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 14. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 14. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 15. Accelerated Program Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . . . . . . . .28
TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . . . . . . . .28
TFBGA63 – 63 ball array, 0.8 mm pitch, Package Outline, Bottom view . . . . . . . . . . . . . . . . . . . .29
TFBGA63 – 63 ball array, 0.8 mm pitch, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . .29
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
M29W320DT, M29W320DB
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42Table 26. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Table 17. Top Boot Block Addresses, M29W320DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 18. Bottom Boot Block Addresses, M29W320DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Table 19. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 20. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 21. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 22. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 23. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 24. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37Table 25. Programmer Technique Bus Operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . .37
Figure 16. Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 17. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 18. In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 19. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5/43
M29W320DT, M29W320DB
SUMMARY DESCRIPTIONThe M29W320D is a 32 Mbit (4Mb x8 or 2Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Figures 5 and 6 and Tables 17 and
18. The first or last 64 Kbytes have been divided
into four additional blocks. The 16 Kbyte Boot
Block can be used for small initialization code to
start the microprocessor, the two 8 Kbyte Param-
eter Blocks can be used for parameter storage and
the remaining 32 Kbyte is a small Main Block
where the application may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm) and
TFBGA63 (7x11mm, 0.8mm pitch) packages. The
memory is supplied with all the bits erased (set to
1).
Figure 2. Logic Diagram Table 1. Signal Names
M29W320DT, M29W320DB
Figure 3. TSOP Connections
7/43
M29W320DT, M29W320DB
Figure 4. TFBGA Connections (Top view through package)Note:1. Balls are shorted together via the substrate but not connected to the die.
M29W320DT, M29W320DB
Figure 5. Block Addresses (x8)Note: Also see Appendix A, Tables 17 and 18 for a full listing of the Block Addresses.
9/43
M29W320DT, M29W320DB
Figure 6. Block Addresses (x16)Note: Also see Appendix A, Tables 17 and 18 for a full listing of the Block Addresses.
M29W320DT, M29W320DB
SIGNAL DESCRIPTIONSSee Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the internal state ma-
chine.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
VIH. When BYTE is Low, VIL, these pins are not
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1).When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
VPP/Write Protect (VPP/WP). The VPP/Write
Protect pin provides two functions. The VPP func-
tion allows the memory to use an external high
voltage power supply to reduce the time required
for Unlock Bypass Program operations. The
Write Protect function provides a hardware meth-
od of protecting the 16 Kbyte Boot Block. The
VPP/Write Protect pin must not be left floating or
unconnected.
When VPP/Write Protect is Low, VIL, the memory
protects the 16 Kbyte Boot Block; Program and
Erase operations in this block are ignored while
VPP/Write Protect is Low.
When VPP/Write Protect is High, VIH, the memory
reverts to the previous protection status of the 16
Kbyte boot block. Program and Erase operations
can now modify the data in the 16 Kbyte Boot
Block unless the block is protected using Block
Protection.
When VPP/Write Protect is raised to VPP the mem-
ory automatically enters the Unlock Bypass mode.
When VPP/Write Protect returns to VIH or VIL nor-
mal operation resumes. During Unlock Bypass
Program operations the memory draws IPP from
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
VIH to VPP and from VPP to VIH must be slower
than tVHVPP, see Figure 15.
Never raise VPP/Write Protect to VPP from any
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
A 0.1μF capacitor should be connected between
the VPP/Write Protect pin and the VSS Ground pin
to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Unlock Bypass
Program, IPP.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if VPP/WP is at VIL, then the 16 KByte
outermost boot block will remain protect even if RP
is at VID.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/Busy
Output section, Table 15 and Figure 14, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, VOL. Ready/Busy is high-im-
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
11/43
M29W320DT, M29W320DBNote that if VPP/WP is at VIL, then the 16 KByte
outermost boot block will remain protect even if RP
is at VID.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 15 and Figure
14, Reset/Temporary Unprotect AC Characteris-
tics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
memory. When Byte/Word Organization Select is
Low, VIL, the memory is in x8 mode, when it is
High, VIH, the memory is in x16 mode.
VCC Supply Voltage (2.7V to 3.6V). VCC pro-
vides the power supply for all operations (Read,
Program and Erase).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1μF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase operations, ICC3.
VSS Ground. VSS is the reference for all voltage
measurements.
M29W320DT, M29W320DB
BUS OPERATIONSThere are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 2 and 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 11, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, VIH, during the whole Bus
Write operation. See Figures 12 and 13, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 11, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations un-
til the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus OperationsAdditional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require VID to be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2 and 3, Bus Operations.
lock Protect andC hip Unprotect. Each block
can be separately protected against accidental
Program or Erase. The whole chip can be unpro-
tected to allow the data inside the blocks to be
changed.
Block Protect and Chip Unprotect operations are
described in Appendix C.
13/43
M29W320DT, M29W320DB
Table 2. Bus Operations, BYTE = VILNote: X = VIL or VIH.
Table 3. Bus Operations, BYTE = VIHNote: X = VIL or VIH.
M29W320DT, M29W320DB
COMMAND INTERFACEAll Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes de-
pending on whether the memory is in 16-bit or 8-
bit mode. See either Table 4, or 5, depending on
the configuration that is being used, for a summary
of the commands.
Read/Reset Command. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless other-
wise stated. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select com-
mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until a Read/Reset
command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits
may be set to either VIL or VIH. The Manufacturer
Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either VIL or VIH. The
Device Code for the M29W320DT is 22CAh and
for the M29W320DB is 22CBh.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,= VIH, and A12-A20 specifying the address of
the block. The other address bits may be set to ei-
ther VIL or VIH. If the addressed block is protected
then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Read CFI Query Command. The Read CFI
Query Command is used to read data from the
Common Flash Interface (CFI) Memory Area. This
command is valid when the device is in the Read
Array mode, or when the device is in Autoselected
mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is-
sued subsequent Bus Read operations read from
the Common Flash Interface Memory Area.
The Read/Reset command must be issued to re-
turn the device to the previous mode (the Read Ar-
ray mode or Autoselected mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Autoselect-
ed mode.
See Appendix B, Tables 19, 20, 21, 22, 23 and 24
for details on the information contained in the
Common Flash Interface (CFI) memory area.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data in the internal
state machine and starts the Program/Erase Con-
troller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo-
ry. When the cycle time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
15/43
M29W320DT, M29W320DBpass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
The memory offers accelerated program opera-
tions through the VPP/Write Protect pin. When the
system asserts VPP on the VPP/Write Protect pin,
the memory automatically enters the Unlock By-
pass mode. The system may then write the two-
cycle Unlock Bypass program command se-
quence. The memory uses the higher voltage on
the VPP/Write Protect pin, to accelerate the Unlock
Bypass Program operation.
Never raise VPP/Write Protect to VPP from any
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
Unlock Bypass Program Command. The Un-
lock Bypass Program command can be used to
program one address in the memory array at a
time. The command requires two Bus Write oper-
ations, the final write operation latches the ad-
dress and data in the internal state machine and
starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. The
operation cannot be aborted, the Status Register
is read and protected blocks cannot be pro-
grammed. Errors must be reset using the Read/
Reset command, which leaves the device in Un-
lock Bypass Mode. See the Program command for
details on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100μs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands, including the Erase Suspend com-
mand. It is not possible to issue any command to
abort the operation. Typical chip erase times are
given in Table 6. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the sec-
tion on the Status Register for more details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50μs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50μs of the last block. The 50μs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register sec-
tion for details on how to identify if the Program/
Erase Controller has started the Block Erase oper-
ation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100μs, leaving the data un-
changed. No error condition is given when protect-
ed blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command. Typical block erase times are given in
Table 6. All Bus Read operations during the Block
Erase operation will output the Status Register on
the Data Inputs/Outputs. See the section on the
Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will suspend within
the Erase Suspend Latency Time (refer to Table 6
M29W320DT, M29W320DBfor value) of the Erase Suspend Command being
issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start im-
mediately when the Erase Resume Command is
issued. It is not possible to select any further
blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condition is given. Read-
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac-
cepted.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller after an Erase Suspend. The de-
vice must be in Read Array mode before the Re-
sume command will be accepted. An erase can be
suspended and resumed more than once.
lock P rotect andC hip Unprotec t Comm ands.Each block can be separately protected against
accidental Program or Erase. The whole chip can
be unprotected to allow the data inside the blocks
to be changed.
Block Protect and Chip Unprotect operations are
described in Appendix C.
17/43
M29W320DT, M29W320DB
Table 4. Commands, 16-bit mode, BYTE = VIHNote: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Read/Reset command isignored during algorithm execution.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional
Bus Write Operations until Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-mands on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Pro-gram/Erase Controller completes and the memory returns to Read Mode.
CFI Query. Command is valid when device is ready to read array data or when device is in autoselected mode.
M29W320DT, M29W320DB
Table 5. Commands, 8-bit mode, BYTE = VILNote: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Read/Reset command isignored during algorithm execution.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional
Bus Write Operations until Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-mands on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Pro-gram/Erase Controller completes and the memory returns to Read Mode.
CFI Query. Command is valid when device is ready to read array data or when device is in autoselected mode.
Table 6. Program, Erase Times and Program, Erase Endurance CyclesNote:1. TA = 25°C, VCC = 3.3V.
19/43
M29W320DT, M29W320DB
STATUS REGISTERBus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus-
pend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 7, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 7, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
If any attempt is made to erase a protected block,
the operation is aborted, no error is signalled and
DQ6 toggles for approximately 100μs. If any at-
tempt is made to program a protected block or a
suspended block, the operation is aborted, no er-
ror is signalled and DQ6 toggles for approximately
1μs.
Figure 8, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
M29W320DT, M29W320DB
Table 7. Status Register BitsNote: Unspecified data bits should be ignored.
Figure 7. Data Polling Flowchart Figure 8. Data Toggle Flowchart
21/43
M29W320DT, M29W320DB
MAXIMUM RATINGStressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum RatingsNote:1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions.
M29W320DT, M29W320DB
DC AND AC PARAMETERSThis section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 9, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 9. Operating and AC Measurement Conditions
Figure 9. AC Measurement I/O Waveform Figure 10. AC Measurement Load Circuit
Table 10. Device CapacitanceNote: Sampled only, not 100% tested.
