M29KW064E90N1 ,64MBIT (4MBX16, UNIFORM BLOCK) 3V SUPPLY LIGHTFLASH™ MEMORYLogic Diagram . . 3Table 1. Signal Names . . 3Figure 3. TFBGA Connections (Top view t ..
M29KW064E-90N1 ,64MBIT (4MBX16, UNIFORM BLOCK) 3V SUPPLY LIGHTFLASH™ MEMORYAbsolute Maximum Ratings . . . . . . . 14DC and AC PARAMETERS . 15Table 10. Operating an ..
M29KW064E-90N1T ,64 Mbit 4Mb x16, Uniform Block 3V Supply LightFlash⑩ MemoryFEATURES SUMMARY . . . . . 1Figure 1. Packages . . . . . . 1Table 1. Signal Names ..
M29W004BB-120N1 ,4 MBIT (512KB X8, BOOT BLOCK) LOW VOLTAGE SINGLE SUPPLY FLASH MEMORYLogic Diagram, and Table 1, Signalwhen the memory array can be read. Ready/BusyNames, for a brief o ..
M29W004BT70N1 ,4 MBIT (512KB X8, BOOT BLOCK) LOW VOLTAGE SINGLE SUPPLY FLASH MEMORYLogic Diagram, and Table 1, Signalwhen the memory array can be read. Ready/BusyNames, for a brief o ..
M29W008AB-120N6 ,8 MBIT (1MB X8, BOOT BLOCK) LOW VOLTAGE SINGLE SUPPLY FLASH MEMORYLogic Diagram■ ERASE SUSPEND and RESUME MODES– Read and Program another Block duringErase SuspendV■ ..
M50747-161SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50747-2B4SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50747-2B4SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50940-303SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50941-330SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50FLW040A ,4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash MemoryLogic Diagram (A/A Mux Interface) . . 7Table 1. Signal Names (FWH/LPC Interface) . 7Table ..
M29KW064E90N1-M29KW064E-90N1
64MBIT (4MBX16, UNIFORM BLOCK) 3V SUPPLY LIGHTFLASH™ MEMORY
1/31March 2004
M29KW064E64 Mbit (4Mb x16, Uniform Block)
3V Supply LightFlash™ Memory
FEATURES SUMMARY SUPPLY VOLTAGE
–VCC= 2.7V to 3.6V for Read
–VPP = 11.4V to 12.6V for Program and
Erase ACCESS TIME:
–90ns at VCC = 3.0V to 3.6V 100ns at VCC = 2.7V to 3.6V PROGRAMMING TIME 9µs per Word typical Multiple Word Programming Option (8s
typical Chip Program) ERASE TIME 41s typical factory Chip Erase UNIFORM BLOCKS 32 blocks of 2 Mbits PROGRAM/ERASE CONTROLLER Embedded Word Program algorithms 10,000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code : 88AFh
M29KW064E
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 2. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Program Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3/31
M29KW064ETable 4. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 5. Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . .10
Table 7. Multiple Word Program Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 5. Multiple Word Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
VPP Status Bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Status Register Bit DQ1 is reserved.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 6. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 7. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 10. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 11. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 12. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 10.Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 11.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 14. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 12.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 15. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 13.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 16. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Figure 14.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . .23
Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data .23
Figure 15.TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Bottom View Package Outline. . . . .24
Table 18. TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Package Mechanical Data. . . . . . . .24
Figure 16.TFBGA48 Daisy Chain - Package Connections (Top view through package) . . . . . . . .25
Figure 17.TFBGA48 Daisy Chain - PCB Connections (Top view through package). . . . . . . . . . . .26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
M29KW064ETable 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 20. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5/31
M29KW064E
SUMMARY DESCRIPTIONThe M29KW064E LightFlash™ is a 64 Mbit (4Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. Read operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. Program and Erase operations require an
additional VPP (11.4 to 12.6) power supply. On
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.
The memory is divided into 32 uniform blocks that
can be erased independently so it is possible to
preserve valid data while old data is erased (see
Figures 2, Block Addresses). Program and Erase
commands are written to the Command Interface
of the memory. An on-chip Program/Erase Con-
troller (P/E.C.) simplifies the process of program-
ming or erasing the memory by taking care of all of
the special operations that are required to update
the memory contents.
The M29KW064E LightFlash™ features a new
command, Multiple Word Program, used to pro-
gram large streams of data. It greatly reduces the
total programming time when a large number of
Words are written to the memory at any one time.
Using this command the entire memory can be
programmed in 8s, compared to 36s using the
standard Word Program.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm)
and TFBGA48 (6 x 9mm, 0.8mm pitch) packages.
The memory is supplied with all the bits erased
(set to ’1’).
Table 1. Signal Names
M29KW064E
7/31
M29KW064E Table 2. Block Addresses
M29KW064E
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs outputs the data stored at the select-
ed address during a Bus Read operation. During
Bus Write operations they represent the com-
mands sent to the Command Interface of the Pro-
gram/Erase Controller.
Data Inputs/Outputs (DQ8-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset (RP). The Reset pin can be used to apply
a Hardware Reset to the memory.
A Hardware Reset is achieved by holding Reset
Low, VIL, for at least tPLPX. After Reset goes High,
VIH, the memory will be ready for Bus Read and
Bus Write operations after tPHEL or tRHEL, which-
ever occurs last. See the Ready/Busy Output sec-
tion, Table 16 and Figure 13, Reset AC
Characteristics for more details.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode and Auto
Select mode. After a Hardware Reset, Bus Read
and Bus Write operations cannot begin until
Ready/Busy becomes high-impedance. See Table
16 and Figure 13, Reset AC Characteristics.
During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for Read operations.
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, ICC3.
VPP Program Supply Voltage. VPP is both a
power supply and Write Protect pin. The two func-
tions are selected by the voltage range applied to
the pin. The Supply Voltage VCC must be applied
before the Program Supply Voltage VPP.
If VPP is in the range 11.4V to 12.6V it acts as a
power supply pin for program and erase opera-
tions. VPP must be stable until the Program/Erase
algorithm is completed.
If VPP is kept in a low voltage range (0V to 3.6V)
VPP is seen as a Write Protect pin. In this case a
voltage lower than VHH gives an absolute protec-
tion against program or erase, while VPP in the
range of VHH enables these functions (see Table
12, DC Characteristics for the relevant values).
Note that VPP must not be left floating or uncon-
nected as the device may become unreliable.
Vss Ground. The VSS Ground is the reference
for all voltage measurements.
9/31
M29KW064E
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and
Electronic Signature. See Tables 3, Bus Opera-
tions, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ig-
nored by the memory and do not affect bus opera-
tions.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 10, Read Mode AC Waveforms,
and Table 13, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, VIH, during the whole Bus
Write operation. See Figures 11 and 12, Write AC
Waveforms, and Tables 14 and 15, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 12, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations un-
til the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3, Bus Operations.
Table 3. Bus Operations
Note:1. X = VIL or VIH. XX = VIL , VIH or VHH Not necessary for Auto Select or Read/Reset commands. When reading the Status Register during Program or Erase operations, VPP must be kept at VHH.
M29KW064E
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security. Refer to
Tables 4 and 5, for a summary of the commands.
Read/Reset Command.
The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM, unless otherwise stated. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
The Read/Reset Command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command is executed
regardless of the value of VPP (VIL, VIH or VHH).
Auto Select Command.
The Auto Select command is used to read the
Manufacturer Code and the Device Code. Three
consecutive Bus Write operations are required to
issue the Auto Select command. Once the Auto
Select command is issued the memory remains in
Auto Select mode until a Read/Reset command is
issued, all other commands are ignored. The Auto
Select command is executed regardless of the val-
ue of VPP (VIL, VIH or VHH).
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits
may be set to either VIL or VIH.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either VIL or VIH.
Word Program Command.
The Word Program command can be used to pro-
gram a Word to the memory array. VPP must be
set to VHH during Word Program. If VPP is set to ei-
ther VIL or VIH the command will be ignored, the
data will remain unchanged and the device will re-
vert to Read/Reset mode. The command requires
four Bus Write operations, the final write operation
latches the address and data in the internal state
machine and starts the Program/Erase Controller.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Multiple Word Program Command
The Multiple Word Program command can be
used to program large streams of data. It greatly
reduces the total programming time when a large
number of Words are written to the memory at any
one time. VPP must be set to VHH during Multiple
Word Program. If VPP is set to either VIL or VIH the
command will be ignored, the data will remain un-
changed and the device will revert to Read/Reset
mode.
It has four phases: the Setup Phase to initiate the
command, the Program Phase to program the
data to the memory, the Verify Phase to check that
the data has been correctly programmed and re-
program if necessary and the Exit Phase.
Setup Phase. The Multiple Word Program com-
mand requires three Bus Write operations to ini-
tiate the command (refer to Table 5, Multiple Word
Program Command and Figure 5, Multiple Word
Program Flowchart). The Status Register Toggle
bit (DQ6) should be checked to verify that the op-
eration has started and the Multiple Word Program
bit (DQ0) checked to verify that the P/E.C. is ready
for the first Word.
Program Phase. The Program Phase requires
n+1 cycles, where n is the number of Words, to ex-
ecute the programming phase (refer to Table 5,
Multiple Word Program Command and Figure 5,
Multiple Word Program Flowchart).
Three successive steps are required to issue and
execute the Program Phase of the command. The fourth Bus Write operation of the
command latches the Start Address and the
first Word to be programmed. The Status
Register Multiple Word Program bit (DQ0)
should be read to check that the P/E.C. is
ready for the next Word. Each subsequent Word to be programmed is
latched with a new Bus Write operation. The
address can remain the Start Address, be
incremented or be any address in the same
block, as the device automatically increments
the address with each sucssesive Bus Write
11/31
M29KW064E
cycle. If the command is used to program in
more than one block then the address must
remain in the starting block as any address
that is not in the same block as the Start
Address terminates the Program operation.
The Status Register Multiple Word Program
bit (DQ0) must be read between each Bus
Write cycle to check that the P/E.C. is ready
for the next Word. Finally, after all Words have been pro-
grammed, write one Bus Write operation to
any address outside the block containing the
Start Address, to terminate the programming
phase.
The memory is now set to enter the Verify Phase.
Verify Phase. The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data. If the check fails the P/E.C will
try to reprogram the correct data. The P/E.C will
remain busy until the correct data has been suc-
cessfully programmed. The Verify Phase is man-
datory. If the Verify Phase is not executed the
programmed data cannot be guaranteed.
Three successive steps are required to execute
the Verify Phase of the command. Use one Bus Write operation to latch the Start
Address and the first Word, to be verified. The
Status Register Multiple Word Program bit
(DQ0) should be read to check that the P/E.C.
is ready for the next Word. Each subsequent Word to be verified is
latched with a new Bus Write operation. If any
address that is not in the same block as the
Start Address is given, the Verify operation
terminates. The Status Register Multiple Word
Program (DQ0) must be read to check that the
P/E.C. is ready for the next Word. Finally, after all Words have been verified,
write one Bus Write operation to any address
outside the block containing the Start Address,
to terminate the Verify Phase.
Exit Phase . Read the Status Register to verify
that DQ6 has stopped toggling. If the Verify Phase
is successfully completed the memory returns to
the Read mode. If the P/E.C. fails to reprogram a
given location, the Verify Phase will terminate and
Error bit DQ5 will be set in the Status Register. If
the error is due to a VPP failure DQ4 will also be
set. If the operation fails a Read/Reset command
must be issued to return the device to Read mode.
It is not possible to issue any command to abort or
pause the operation. Typical program times are
given in Table 6. Bus Read operations during the
program operation will output the Status Register
on the Data Inputs/Outputs. See the section on the
Status Register for more details.
Note that the Multiple Word Program command
cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole memory from ’0’ to ’1’.
Block Erase Command.
The Block Erase command can be used to erase
a block. It sets all of the bits in the block to ’1’. All
previous data in the block is lost. VPP must be set
to VHH during Block Erase. If VPP is set to either
VIL or VIH the command will be ignored, the data
will remain unchanged and the device will revert to
Read/Reset mode.
Six Bus Write operations are required to select the
block. The Block Erase operation starts the Pro-
gram/Erase Controller after the last Bus Write op-
eration. The Status Register can be read after the
sixth Bus Write operation. See the Status Register
for details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
During the Block Erase operation the memory will
ignore all commands. Typical block erase times
are given in Table 6. All Bus Read operations dur-
ing the Block Erase operation will output the Sta-
tus Register on the Data Inputs/Outputs. See the
section on the Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Chip Erase Command.
The Chip Erase command can be used to erase
the entire memory. It sets all of the bits in the mem-
ory to ’1’. All previous data in the memory is lost.
VPP must be set to VHH during Chip Erase. If VPP
is set to either VIL or VIH the command will be ig-
nored, the data will remain unchanged and the de-
vice will revert to Read/Reset mode. Six Bus Write
operations are required to issue the Chip Erase
Command and start the Program/Erase Control-
ler.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
M29KW064E
Table 4. Standard Commands
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The
Command Interface only uses A0-A10 and DQ0-DQ7 to verify the commands; A11-A21, DQ8-DQ15 are Don’t Care.
Table 5. Multiple Word Program Command
Note: A Bus Read must be done between each Write cycle where the data is programmed or verified, to Read the Status Register and check
that the memory is ready to accept the next data. NOT PA1 is any address that is not in the same block as PA1. X Don’t Care, n =
number of Words to be programmed.
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
Note:1. TA = 25°C, VPP = 12V.
Table 7. Multiple Word Program Timings
Note:1. MWP = Multiple Word Program.
13/31
M29KW064E
Figure 5. Multiple Word Program Flowchart
Note:1. Refer to Table 7, Multiple Word Program Timings, for the values.
M29KW064E
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. The bits in the Status Register
are summarized in Table 8, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion. The Data Polling Bit is output on DQ7 when
the Status Register is read.
During a Word Program operation the Data Polling
Bit outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Word Program operation the memory returns
to Read mode and Bus Read operations from the
address just programmed output DQ7, not its com-
plement. The Data Polling Bit is not available dur-
ing a Multiple Word Program operation.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
Figure 6, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation. The Toggle
Bit is output on DQ6 when the Status Register is
read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
Figure 7, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
VPP Status Bit (DQ4). The VPP Status Bit can be
used to identify if any Program or Erase operation
has failed due to a VPP error. If VPP falls below VHH
during any Program or Erase operation, the oper-
ation aborts and DQ4 is set to ‘1’. If VPP remains at
VHH throughout the Program or Erase operation,
the operation completes and DQ4 is set to ‘0’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. The Erase
Timer Bit is output on DQ3 when the Status Reg-
ister is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Block and Chip Erase op-
erations. The Alternative Toggle Bit is output on
DQ2 when the Status Register is read.
During Erase operations the Toggle Bit changes
from ’0’ to ’1’ to ’0’, etc., with successive Bus Read
operations to any address. Once the operation
completes the memory returns to Read mode.
If an Erase operation fails and the Error Bit is set,
the Alternative Toggle Bit will continue to toggle
with successive Bus Read operations to any ad-
dress. The Alternative Toggle Bit does not change
if the addressed block has erased correctly.
Multiple Word Program Bit (DQ0). The Multiple
Word Program Bit can be used to indicate whether
the Program/Erase Controller is active or inactive
during Multiple Word Program. When the Pro-
gram/Erase Controller has written one Word and is
ready to accept the next Word, the bit is set to ‘0’.
Status Register Bit DQ1 is reserved.
15/31
M29KW064E
Table 8. Status Register Bits
Note:1. Unspecified data bits should be ignored. DQ2 toggles on any address during Block or Chip Erase and after an Erase error.
M29KW064E
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 9. Absolute Maximum Ratings
Note:1. Compliant with the ECOPACK® 7191395 specification for Lead-free soldering processes. Not exceeding 250°C for more than 30s, and peaking at 260°C. Minimum voltage may undershoot to –2V for less than 20ns during transitions. Maximum voltage may overshoot to VCC+2V for less than 20ns during transitions. Maximum voltage may overshoot to 14.0V for less than 20ns during transitions. VPP must not remain at VHH for more than a total
of 80hrs.
