M29F080A90N1T ,8 Mbit 1Mb x8, Uniform Block Single Supply Flash MemoryLogic Diagram, and Table 1, SignalSize Protection# Address RangeNames, for a brief overview of the ..
M29F080A90N6 ,8 MBIT (1MB X8, UNIFORM BLOCK) SINGLE SUPPLY FLASH MEMORY
M29F080D70N1 ,8 MBIT (1MB X8, UNIFORM BLOCK) 5V SUPPLY FLASH MEMORY
M29F080D-70N1 ,8 MBIT (1MB X8, UNIFORM BLOCK) 5V SUPPLY FLASH MEMORY
M29F080D-70N6 ,8 MBIT (1MB X8, UNIFORM BLOCK) 5V SUPPLY FLASH MEMORY
M29F080D70N6E , 8 Mbit (1Mb x8, Uniform Block) 5V Supply Flash Memory
M50734SP-10 , 8-BIT CMOS MICROCOMPUTER
M50734SP-10 , 8-BIT CMOS MICROCOMPUTER
M50747-161SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50747-2B4SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50747-2B4SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50940-303SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M29F080A90N1T
8 Mbit 1Mb x8, Uniform Block Single Supply Flash Memory
1/21April 2000
M29F080A Mbit (1Mb x8, Uniform Block) Single Supply Flash Memory SINGLE 5V±10% SUPPLY VOLTAGEfor
PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 70ns PROGRAMMING TIME
–8μsby Byte typical 16 UNIFORM64 Kbyte MEMORY BLOCKS PROGRAM/ERASE CONTROLLER Embedded Byte Program algorithm Embedded Multi-Block/Chip Erase algorithm Status Register Polling and Toggle Bits Ready/Busy OutputPin ERASE SUSPEND and RESUME MODES Read and Program another Block during
Erase Suspend TEMPORARY BLOCK UNPROTECTION
MODE LOW POWER CONSUMPTION Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLESper
BLOCK 20 YEARS DATA RETENTION Defectivity below1 ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: F1h
TSOP40(N)x 20mm
SO44(M)
Figure1. Logic DiagramAI00501C
A0-A19
DQ0-DQ7
VCC
M29F080AE
VSS
M29F080A2/21
Figure2. TSOP ConnectionsDQ1
DQ2A10
A14
A17
A18
DQ7
A13
A19
DQ5
DQ3
VSS
VCC
DQ4
DQ6
A12
A11
VCC
AI00520B
M29F080A10 21
A15
A16 G
VSS
DQ0
Figure3.SO ConnectionsA17
A18
A19
A16
DQ6DQ2
VSS
VCCVSS
DQ4
A13
VCC
A10
AI00521B
M29F080A22DQ0
DQ1
DQ7
A15
A14
DQ3
DQ5
A11 A12
Table1. Signal NamesA0-A19 Address Inputs
DQ0-DQ7 Data Inputs/Outputs Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output
VCC Supply Voltage
VSS Ground Not Connected Internally
SUMMARY DESCRIPTIONThe M29F080Aisan8 Mbit (1Mbx8) non-volatile
memory that canbe read, erased and repro-
grammed. These operations canbe performedus-
inga single5V supply.On power-upthe memory
defaultstoits Read mode whereit canbe readin
the same wayasa ROMor EPROM.
The memoryis divided into blocks that canbe
erased independentlysoitis possibleto preserve
valid data whileold datais erased. Blocks canbe
protectedin groupsto prevent accidental Program Erase commands from modifyingthe memory.
Program and Erase commandsare writtentothe
Command Interfaceofthe memory.An on-chip
Program/Erase Controller simplifiesthe processof
programmingor erasing the memoryby taking
careofallofthe special operations that arere-
quiredto updatethe memory contents. The endof programor erase operation canbe detected and
any error conditions identified. The commandset
requiredto controlthe memoryis consistent with
JEDEC standards.
Chip Enable, Output Enableand Write Enable sig-
nals control the bus operationof the memory.
They allow simple connectionto most micropro-
cessors, often without additional logic.
The memoryis offeredina TSOP40(10x 20mm)
and SO44 packages anditis supplied withallthe
bits erased (setto ’1’).
3/21
M29F080A
SIGNAL DESCRIPTIONSSee Figure1, Logic Diagram, and Table1, Signal
Names,fora brief overviewofthe signals connect-tothis device.
Address Inputs (A0-A19). The Address Inputs
selectthe cellsinthe memory arrayto access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sentto the
Command Interfaceofthe internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs outputthe data storedatthe selected
address duringa Bus Read operation. During Bus
Write operations they represent the commands
senttothe Command Interfaceofthe internal state
machine.
Chip Enable (E). The Chip Enable,E, activates
the memory, allowing Bus Readand Bus Writeop-
erationstobe performed. When Chip Enableis
High, VIH,all other pinsare ignored.
Output Enable (G). The Output Enable,G, con-
trolsthe Bus Read operationofthe memory.
Write Enable (W). The Write Enable,W, controls
the Bus Write operationof the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The Re-
set/Block Temporary Unprotectpincanbe usedto
applya Hardware Resettothe memoryorto tem-
porarily unprotectall blocks that have been pro-
tected.
Table2. Absolute Maximum Ratings(1)Note:1. Exceptforthe rating ”Operating Temperature Range”, stressesabove those listedinthe Table ”Absolute Maximum Ratings”may
cause permanent damagetothe device. Theseare stress ratingsonlyand operationofthe device attheseor anyother conditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposure toAbsolute Maximum Rating condi-
tionsfor extended periodsmay affect device reliability. Referalsotothe STMicroelectronics SUREProgram andotherrelevantqual-
ity documents. Minimum Voltage mayundershoot to–2V during transitionandforlessthan20ns during transitions.
Symbol Parameter Value UnitAmbient Operating Temperature (Temperature Range Option1) 0to70 °C
Ambient Operating Temperature (Temperature Range Option6) –40to85 °C
Ambient Operating Temperature (Temperature Range Option3) –40to125 °C
TBIAS Temperature Under Bias –50to125 °C
TSTG Storage Temperature –65to150 °C
VIO(2) Inputor Output Voltage –0.6to6 V
VCC Supply Voltage –0.6to6 V
VID Identification Voltage –0.6to 13.5 V
Table3. Uniform Block Addresses, M29F080A Size
(Kbytes) Address Range Protection
Group 64 F0000h-FFFFFh 64 E0000h-EFFFFh 64 D0000h-DFFFFh 64 C0000h-CFFFFh 64 B0000h-BFFFFh 64 A0000h-AFFFFh 64 90000h-9FFFFh 64 80000h-8FFFFh 64 70000h-7FFFFh 64 60000h-6FFFFh 64 50000h-5FFFFh 64 40000h-4FFFFh 64 30000h-3FFFFh 64 20000h-2FFFFh 64 10000h-1FFFFh 64 00000h-0FFFFh
M29F080A4/21 0.1μF capacitor shouldbe connected between
the VCC Supply Voltagepin andthe VSS Ground
pinto decouplethe current surges fromthe power
supply. The PCB track widths mustbe sufficientto
carry the currents required during program and
erase operations, ICC4.
VSS Ground. The VSS Groundisthe referencefor
all voltage measurements.
BUS OPERATIONSThere arefive standardbus operations that control
the device. Theseare Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table4, Bus Operations,fora summary. Typically
glitchesof less than 5nson Chip Enableor Write
Enableare ignoredbythe memory anddonotaf-
fect bus operations.
Bus Read. Bus Read operations read fromthe
memory cells,or specific registersin the Com-
mand Interface.A valid Bus Read operationin-
volves settingthe desired addressonthe Address
Inputs, applyinga Low signal,VIL,to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputswill outputthe
value, see Figure8, Read ModeAC Waveforms,
and Table11, ReadAC Characteristics,for details whenthe output becomes valid.
Bus Write. Bus Write operations writeto the
Command Interface.A valid Bus Write operation
beginsby settingthe desired addressonthe Ad-
dress Inputs. The Address Inputsare latchedby
the Command Interfaceonthe falling edgeof Chip
Enableor Write Enable, whichever occurs last.
The Data Inputs/Outputsare latchedbythe Com-
mand Interfaceonthe rising edgeof Chip Enable Write Enable, whichever occurs first. OutputEn-
able must remain High, VIH, duringthe whole Bus
Write operation. See Figures9 and10, WriteAC
Waveforms, and Tables12 and 13, Write AC
Characteristics,for detailsofthe timing require-
ments. Hardware Resetis achievedby holding Reset/
Block Temporary Unprotect Low, VIL,forat least
tPLPX. After Reset/Block Temporary Unprotect
goes High, VIH,the memorywillbe readyfor Bus
Read and Bus Write operations after tPHELor
tRHEL, whichever occurs last. Seethe Ready/Busy
Output section, Table14 and Figure 11, Reset/
Temporary UnprotectAC Characteristicsfor more
details.
Holding RPatVID will temporarily unprotect the
protected blocksin the memory. Program and
Erase operationsonall blockswillbe possible.
The transition fromVIHtoVID mustbe slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pinan open-drain output that canbe usedto identify
whenthe memory array canbe read. Ready/Busy high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
Aftera Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table14 and Figure
11, Reset/Temporary UnprotectAC Characteris-
tics.
During Programor Erase operations Ready/Busy Low, VOL. Ready/Busywill remain Low during
Read/Reset commandsor Hardware Resets until
the memoryis readyto enter Read mode.
Theuseofan open-drain output allowsthe Ready/
Busy pins from several memoriestobe connecteda single pull-up resistor.A Lowwill then indicate
that one,or more,ofthe memoriesis busy.
VCC Supply Voltage. The VCC Supply Voltage
suppliesthe powerforall operations (Read, Pro-
gram, Erase etc.).
The Command Interfaceis disabled whenthe VCC
Supply Voltageis less thanthe Lockout Voltage,
VLKO. This prevents Bus Write operations fromac-
cidentally damaging the data during power up,
power down and power surges.If the Program/
Erase Controlleris programmingor erasing during
this time thenthe operation aborts andthe memo- contents being alteredwillbe invalid.
5/21
M29F080A
Table4. Bus OperationsNote:X=VILorVIH.
Operation E G W Address Inputs Data
Inputs/OutputsBus Read VIL VIL VIH Cell Address Data Output
Bus Write VIL VIH VIL Command Address Data Input
Output Disable XVIH VIH XHi-Z
Standby VIH XX X Hi-Z
Read Manufacturer
Code VIL VIL VIH A0= VIL,A1= VIL,A9=VID,
OthersVILorVIH 20h
Read Device Code VIL VIL VIH A0= VIH,A1= VIL,A9=VID,
OthersVILorVIH F1h
Output Disable. The Data Inputs/Outputsarein
the high impedance state when Output Enableis
High, VIH.
Standby. When Chip Enableis High, VIH, the
Data Inputs/Outputs pins are placedinthe high-
impedance state and the Supply Currentisre-
ducedtothe Standby level.
When Chip EnableisatVIHthe Supply Currentis
reducedtothe TTL Standby Supply Current, ICC2. further reducethe Supply Currenttothe CMOS
Standby Supply Current, ICC3, Chip Enable should held within VCC± 0.2V. For Standby current
levels see Table10,DC Characteristics.
During programor erase operationsthe memory
will continueto use the Program/Erase Supply
Current, ICC4,for Programor Erase operationsun-
tilthe operation completes.
Automatic Standby.If CMOS levels (VCC± 0.2V)
are usedto drivethe bus andthe busis inactivefor
150nsor more the memory enters Automatic
Standby wherethe internal Supply Currentisre-
ducedtothe Standby Supply Current, ICC3. The
Data Inputs/Outputswillstill output dataifa Bus
Read operationisin progress.
Special Bus OperationsAdditional bus operations canbe performedto
readthe Electronic Signature and alsoto apply
and remove Block Protection. These bus opera-
tionsare intendedfor useby programming equip-
ment and are not usually usedin applications.
They requireVIDtobe appliedto some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that canbe readto identify the memory.
These codes canbe readby applyingthe signals
listedin Table4, Bus Operations.
Block Protection and
Blocks Unprotection. Blocks
can beprotectedin groups against accidental Pro-
gramor Erase. See Table3, Block Addresses,for
detailsof which blocks mustbe protected togethera group. Protected blocks canbe unprotected allow datatobe changed. Block Protection and
Block Unprotection operations must onlybe per-
formedon programming equipment.
For further information referto Application Note
AN1122, Applying Protection and Unprotectionto
M29 Series Flash.
M29F080A6/21
COMMAND INTERFACEAll Bus Write operationstothe memoryare inter-
pretedby the Command Interface. Commands
consistof oneor more sequential Bus Write oper-
ations. Failureto observea valid sequenceof Bus
Write operationswill resultinthe memory return-
ingto Read mode.Inthis case, afterat least 50ns, address transitionor Chip Enable going Lowis
required before reading correct data. The long
command sequences are imposedto maximize
data security.
The commandsare summarizedin Table5, Com-
mands. Referto Table5in conjunction withthe
text descriptions below.
Read/Reset Command. The Read/Reset com-
mand returnsthe memorytoits Read mode where behaves likea ROMor EPROM.It also resets
the errorsin the Status Register. Either oneor
three Bus Write operations canbe usedto issue
the Read/Reset command. the Read/Reset commandis issued duringa
Block Erase operationor followinga Programming Erase error thenthe memorywill takeupto 10μs abort. Duringthe abort periodno valid data can read fromthe memory. Issuinga Read/Reset
command duringa Block Erase operation will
leave invalid datainthe memory.
Auto Select Command. The Auto Select com-
mandis usedto readthe Manufacturer Code,the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations arere-
quiredto issuethe Auto Select command. Once
the Auto Select commandis issuedthe memory
remainsin Auto Select mode until another com-
mandis issued.
From the Auto Select mode the Manufacturer
Code canbe read usinga Bus Read operation
withA0=VIL andA1= VIL. The other address bits
maybesetto eitherVILor VIH. The Manufacturer
Codefor STMicroelectronicsis 20h.
The Device Code canbe read usinga Bus Read
operation withA0=VIH andA1= VIL. The other
address bits maybesetto eitherVILor VIH. The
Device Codeforthe M29F080Ais F1h.
The Block Protection Statusof each block canbe
read usinga Bus Read operation withA0= VIL,= VIH, and A16-A19 specifyingthe addressof
the block. The other address bits maybesettoei-
therVILor VIH.Ifthe addressed blockis protected
then 01his outputonthe Data Inputs/Outputs, oth-
erwise 00his output.
Program Command. The Program command
canbe usedto programa valueto one addressin
the memory arrayata time. The commandre-
quires four Bus Write operations,the finalwriteop-
eration latchesthe addressand datainthe internal
state machine and startsthe Program/Erase Con-
troller.the address fallsina protected block then the
Program commandis ignored,the data remains
unchanged. The Status Registeris never read and error conditionis given.
Duringthe program operationthe memorywillig-
noreall commands.Itisnot possibleto issue any
commandto abortor pausethe operation. Typical
program timesare givenin Table6. Bus Readop-
erations duringthe program operationwill output
the Status Registeronthe Data Inputs/Outputs.
Seethe sectiononthe Status Registerfor more
details.
After the program operation has completed the
memorywill returntothe Read mode, unlessan
error has occurred. Whenan error occurs the
memorywill continueto outputthe Status Regis-
ter.A Read/Reset command mustbe issuedtore-
setthe error condition and returnto Read mode.
Note thatthe Program command cannot changea
bitsetat’0’ backto’1’. Oneofthe Erase Com-
mands mustbe usedtosetallthebitsina blockorthe whole memory from’0’to’1’.
7/21
M29F080A
Table5. CommandsNote:X Don’t Care,PA Program Address,PD Program Data,BAAny addressinthe Block.
All valuesinthetablearein hexadecimal.
The Command Interfaceonlyuses addressbits A0-A10to verifythe commands,the upper addressbitsare Don’t Care.
Read/Reset.Aftera Read/Reset command,readthe memoryas normaluntil another commandis issued.
Auto Select.AfteranAuto Select command,read ManufacturerID, DeviceIDor Block Protection Status.
Program, Chip Erase, Block Erase.After these commandsreadthe Status Registeruntilthe Program/Erase Controller completesandthe
memory returnsto Read Mode.Add additional Blocks during Block Erase Commandwith additionalBus Write Operationsuntilthe Timeout
Bitisset.
Erase Suspend. Afterthe Erase Suspend command readnon-erasing memory blocksas normal, issueAuto Selectand Program commands non-erasing blocksas normal.
Erase Resume.Afterthe Erase Resume commandthe suspended Erase operation resumes,readthe Status Registeruntilthe Program/
Erase Controller completesandthe memory returnsto Read Mode.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr DataRead/Reset F0 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Chip Erase Command. The Chip Erase com-
mand canbe usedto erasethe entire chip.Six Bus
Write operations are requiredto issue the Chip
Erase Command and start the Program/Erase
Controller. any blocksare protected then theseare ignored
andallthe other blocks are erased.Ifallofthe
blocksare protectedthe Chip Erase operationap-
pears tostartbutwill terminate within about 100μs,
leavingthe data unchanged.No error conditionis
given when protected blocksare ignored.
Duringthe erase operationthe memorywill ignore
all commands.Itisnot possibleto issue any com-
mandto abortthe operation. Typical chip erase
timesare givenin Table6.All Bus Read opera-
tions duringthe Chip Erase operationwill output
the Status Registeronthe Data Inputs/Outputs.
Seethe sectiononthe Status Registerfor more
details.
Afterthe Chip Erase operation has completedthe
memorywill returntothe Read Mode, unlessan
error has occurred. Whenan error occurs the
memorywill continueto outputthe Status Regis-
ter.A Read/Reset command mustbe issuedtore-
setthe error condition and returnto Read Mode.
The Chip Erase Command setsallofthebitsinun-
protected blocksofthe memoryto’1’.All previous
datais lost.
M29F080A8/21
Block Erase Command. The Block Erase com-
mand canbe usedto erasealistof oneor more
blocks.Six Bus Write operations are requiredto
select the first blockin the list. Each additional
blockinthelist canbe selectedby repeatingthe
sixth Bus Write operation usingthe addressofthe
additional block. The Block Erase operation starts
the Program/Erase Controller about 50μs afterthe
last Bus Write operation. Oncethe Program/Erase
Controller startsitis not possibleto select any
more blocks. Each additional block must therefore selected within 50μsofthelast block. The 50μs
timer restarts whenan additional blockis selected.
The Status Register canbe read after the sixth
Bus Write operation. Seethe Status Registerfor
detailson howto identifyif the Program/Erase
Controller has startedthe Block Erase operation. any selected blocksare protected then theseare
ignored andall the other selected blocks are
erased.Ifallofthe selected blocksare protected
the Block Erase operation appearsto startbutwill
terminate within about 100μs, leavingthe dataun-
changed.No error conditionis given when protect- blocksare ignored.
Duringthe Block Erase operationthe memorywill
ignoreall commands exceptthe Erase Suspend
and Read/Reset commands. Typical block erase
times are givenin Table6.All Bus Read opera-
tions duringthe Block Erase operationwill output
the Status Registeron the Data Inputs/Outputs.
Seethe sectiononthe Status Registerfor more
details.
Afterthe Block Erase operation has completedthe
memorywill returntothe Read Mode, unlessan
error has occurred. Whenan error occurs the
memorywill continueto outputthe Status Regis-
ter.A Read/Reset command mustbe issuedtore-
setthe error condition and returnto Read mode.
The Block Erase Command setsallofthe bitsin
the unprotected selected blocksto’1’.All previous
datainthe selected blocksis lost.
Erase Suspend Command. The Erase Suspend
Command maybe usedto temporarily suspenda
Block Erase operation and returnthe memoryto
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controllerwill suspend within
15μsof the Erase Suspend Command beingis-
sued. Once the Program/Erase Controller has
stoppedthe memorywillbesetto Read mode and
the Erasewillbe suspended.Ifthe Erase Suspend
commandis issued during the period whenthe
memoryis waitingforan additional block (before
the Program/Erase Controller starts) then the
Eraseis suspended immediately andwill startim-
mediately whenthe Erase Resume Commandis
issued.Itwillnotbe possibleto select any further
blocksfor erasure afterthe Erase Resume.
During Erase Suspenditis possibleto Read and
Program cellsin blocks thatarenot being erased;
both Read and Program operations behaveas
normalon these blocks. Reading from blocks that
are being erasedwill outputthe Status Register.It also possibleto enterthe Auto Select mode:the
memorywill behaveasinthe Auto Select modeon
all blocks untila Read/Reset command returnsthe
memoryto Erase Suspend mode.
Erase Resume Command. The Erase Resume
command mustbe usedto restartthe Program/
Erase Controller from Erase Suspend.An erase
canbe suspended and resumed more than once.
Table6. Program, Erase Times and Program, Erase Endurance Cycles(TA=0to70°C, –40to85°Cor –40to 125°C)
Note:1.TA =25°C,VCC =5V.
Parameter Min Typ(1) Typical after
100k W/E Cycles(1) Max UnitChip Erase(Allbitsinthe memorysetto‘0’) 3 3 sec
Chip Erase 8 8 30 sec
Block Erase(64 Kbytes) 0.6 0.6 4 sec
Program 8 8 150 μs
Chip Program 9 9 35 sec
Program/Erase Cycles(per Block) 100,000 cycles
9/21
M29F080A
STATUS REGISTERBus Read operations from any address always
read the Status Register during Program and
Erase operations.Itis also read during Erase Sus-
pend whenan address within ablock being erased accessed.
Thebitsinthe Status Registerare summarizedin
Table7, Status Register Bits.
Data PollingBit (DQ7). The Data PollingBit can usedto identify whether the Program/Erase
Controller has successfully completedits opera-
tionorifit has respondedtoan Erase Suspend.
The Data PollingBitis outputon DQ7 whenthe
Status Registeris read.
During Program operationsthe Data PollingBit
outputs the complementof thebit being pro-
grammedto DQ7. After successful completionof
the Program operation the memory returnsto
Read mode and Bus Read operationsfromthead-
dress just programmed output DQ7,notits com-
plement.
During Erase operationsthe Data PollingBit out-
puts’0’, the complementof the erased stateof
DQ7. After successful completionofthe Eraseop-
erationthe memory returnsto Read mode. Erase Suspend modethe Data PollingBitwill
outputa’1’ duringa Bus Read operation withina
block being erased. The Data PollingBit will
change froma’0’toa’1’ whenthe Program/Erase
Controller has suspendedthe Erase operation.
Figure4, Data Polling Flowchart, givesan exam-
pleof howtousethe Data PollingBit.A ValidAd-
dressis the address being programmedoran
address withinthe block being erased.
ToggleBit (DQ6). The ToggleBit canbe usedto
identify whetherthe Program/Erase Controller has
successfully completedits operationorifithasre-
spondedtoan Erase Suspend. The ToggleBitis
outputon DQ6 whenthe Status Registeris read.
During Program and Erase operationsthe Toggle
Bit changes from’0’to’1’to’0’, etc., with succes-
sive Bus Read operationsat any address. After
successful completionofthe operationthe memo- returnsto Read mode.
During Erase Suspend modethe ToggleBitwill
output when addressingacell withina block being
erased. The ToggleBitwill stop toggling whenthe
Program/Erase Controller has suspended the
Erase operation.
Figure5, Data Toggle Flowchart, givesan exam-
pleof howto usethe Data ToggleBit.
ErrorBit (DQ5). The ErrorBit canbe usedto
identify errors detectedby the Program/Erase
Controller. The ErrorBitissetto’1’ whena Pro-
gram, Block Eraseor Chip Erase operation failsto
writethe correct datatothe memory.Ifthe Error
Bitisseta Read/Reset command mustbe issued
before other commandsare issued. The Errorbit outputon DQ5 whenthe Status Registeris read.
Note thatthe Program command cannot changea
bitsetat’0’ backto’1’ and attemptingtodoso may maynotset DQ5at’1’.In both cases,a succes-
sive Bus Read operationwill showthebitisstill’0’.
Oneofthe Erase commands mustbe usedtoset
allthe bitsina blockorinthe whole memory from
’0’to’1’.
Table7. Status Register BitsNote: Unspecifieddatabits shouldbe ignored.
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RBProgram Any Address DQ7 Toggle 0 – – 0
Program During Erase
Suspend Any Address DQ7 Toggle 0 – – 0
Program Error Any Address DQ7 Toggle 1 – – 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0
Block Erase before
timeout
Erasing Block 0 Toggle 0 0 Toggle 0
Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Block Erase
Erasing Block 0 Toggle 0 1 Toggle 0
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erase Suspend
Erasing Block 1 No Toggle 0 – Toggle 1
Non-Erasing Block Data readas normal 1
Erase Error
Good Block Address 0 Toggle 1 1 No Toggle 0
Faulty Block Address 0 Toggle 1 1 Toggle 0
M29F080A10/21
Figure4. Data Polling FlowchartREADDQ5& DQ7 VALID ADDRESS
START
READ DQ7 VALID ADDRESS
FAIL PASS
AI03598
DQ7 = DATA
YES
YES
DQ5
DQ7 =
DATA
YES
Figure5. Data Toggle FlowchartREADDQ6
START
READ DQ6
TWICE
FAIL PASS
AI01370B
DQ6 = TOGGLE
YES
YES
DQ5 =1
YES
DQ6 = TOGGLE
READ
DQ5 &DQ6
Erase TimerBit (DQ3). The Erase TimerBit can usedto identify the startof Program/Erase
Controller operation duringa Block Erase com-
mand.
Oncethe Program/Erase Controller starts erasing
the Erase TimerBitissetto’1’. Beforethe Pro-
gram/Erase Controller startsthe Erase TimerBitis
setto’0’ and additional blockstobe erased may writtentothe Command Interface. The Erase
TimerBitis outputon DQ3 whenthe Status Reg-
isteris read.
Alternative ToggleBit (DQ2). The Alternative
ToggleBit canbe usedto monitorthe Program/
Erase controller during Erase operations. TheAl-
ternative ToggleBitis outputon DQ2 whenthe
Status Registeris read.
During Chip Erase and Block Erase operationsthe
ToggleBit changes from’0’to’1’to’0’, etc., with
successive Bus Read operations from addresses
withinthe blocks being erased. Oncethe operation
completesthe memory returnsto Read mode.
During Erase Suspendthe Alternative ToggleBit
changes from’0’to’1’to’0’, etc. with successive
Bus Read operations from addresses withinthe
blocks being erased. Bus Read operationstoad-
dresses within blocksnot being erasedwill output
the memorycell dataasifin Read mode.
Afteran Erase operation that causesthe ErrorBitbesetthe Alternative ToggleBit canbe usedto
identify which blockor blocks have causedtheer-
ror. The Alternative ToggleBit changes from’0’to
’1’to’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that havenot
erased correctly. The Alternative ToggleBit does
not changeifthe addressed block has erased cor-
rectly.
11/21
M29F080A
Figure6.AC Testing Input Output WaveformAI01275B
High Speed
1.5V
2.4V
Standard
0.45V
2.0V
0.8V
Figure7.AC Testing Load CircuitAI03027
1.3V
OUT= 30pF or100pF includesJIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Table9. Capacitance(TA =25°C,f=1 MHz)
Note: Sampledonly,not 100% tested.
Symbol Parameter Test Condition Min Max UnitCIN Input Capacitance VIN =0V 6pF
COUT Output Capacitance VOUT =0V 12 pF
Table8.AC Measurement Conditions
Parameter
M29F080A 90/120 Test Conditions High Speed Standard
Load Capacitance (CL) 30pF 100pF
Input RiseandFall Times ≤ 10ns ≤ 10ns
Input Pulse Voltages 0to3V 0.45to 2.4V
Inputand Output Timing Ref.Voltages 1.5V 0.8Vand 2.0V
