M29F002T-120K1TR ,2 Mbit 256Kb x8, Boot Block Single Supply Flash MemoryLogic Diagram20 YEARS DATARETENTION– Defectivity below 1ppm/yearELECTRONIC SIGNATUREV– Manufacturer ..
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M29F002T-120K1TR
2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory
AI02078C
A0-A17
DQ0-DQ7CC
M29F002T
M29F002B
M29F002NTE
VSS
(*) RPNC
Figure1. Logic Diagram
M29F002T, M29F002NT
M29F002B Mbit (256Kb x8, Boot Block) Single Supply Flash Memory± 10% SUPPLY VOLTAGEfor PROGRAM,
ERASE and READ OPERATIONS
FASTACCESS TIME: 70ns
FAST PROGRAMMING TIME: 10μs typical
PROGRAM/ERASE CONTROLLER (P/E.C.) Program Byte-by-Byte Status Register bits
MEMORYBLOCKS Boot Block (Topor Bottom location) Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI-BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION Stand-byand Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK YEARSDATARETENTION Defectivity below 1ppm/year
ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code, M29F002T: B0h Device Code, M29F002NT: B0h Device Code, M29F002B: 34h
DESCRIPTIONThe M29F002isa non-volatile memory that may erased electricallyat the blockor chiplevel and
programmed in-system ona Byte-by-Byte basis
usingonly asingle5VVCC supply.For Programand
Erase operationsthe necessary high voltages are
generated internally. The device can alsobe pro-
grammedin standard programmers.
The array matrix organisation allows each blockto erased and reprogrammed without affecting
otherblocks. Blocks canbe protectedagainst pro-
graming and erase on programming equipment,
and temporarily unprotectedto make changesin
the application. Each block can be programmed
and erased over 100,000 cycles.
July 1998 1/29
PLCC32 (K)
PDIP32 (P)
TSOP32(N)x 20mm
Note:* RPNC functionisnot availableforthe M29F002NT
AI02079C
A17
A13
A10
DQ5
DQ0
DQ1DQ2 DQ3DQ4
A16
DQ7
A12
A14
RPNCV
M29F002T
M29F002B
A15
A11
DQ6
Figure 2B. LCC Pin ConnectionsDQ0
A13
A10
DQ7
A14
A11
DQ5DQ1
DQ2
DQ3VSS
DQ4
DQ6
A17A16
A12
(*) RPNC VCC
A15
AI02080C
M29F002T
M29F002B
M29F002NT
Figure 2A. DIP Pin ConnectionsDQ0 A3
A13
A10
DQ7
A14
A11 G
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A17
A16
A12
RPNC
VCC
A15
AI02361B
M29F002T
M29F002B 17
VSS
Figure 2C. TSOP Pin Connections
Note: Pin1isnot connected fortheM29F002NT
A0-A17 Address Inputs
DQ0-DQ7 Data Input/Outputs, Command Inputs Chip Enable Output Enable WriteEnable
RPNC(*) Reset/ Block TemporaryUnprotect
VCC Supply Voltage
VSS Ground
Table1. Signal Names
DESCRIPTION(cont’d)Instructionsfor Read/Reset, Auto Select for read-
ing the Electronic Signatureor Block Protection
status,Programming, Block and Chip Erase,Erase
Suspend and Resume are writtento the devicein
cyclesofcommandstoa CommandInterfaceusing
standardmicroprocessor writetimings. The device
isofferedin PLCC32, PDIP32 and TSOP32(8x20
mm) packages.
2/29
M29F002T, M29F002NT, M29F002B
Symbol Parameter Value Unit Ambient Operating Temperature(3) –40to 125 °C
TBIAS Temperature Under Bias –50to 125 °C
TSTG Storage Temperature –65to 150 °C
VIO(2) Inputor Output Voltages –0.6to7 V
VCC Supply Voltage –0.6to7 V
V(A9,E, G,RPNC)(2) A9,E,G, RPNC Voltage –0.6to 13.5 V
Notes:1. Exceptfor therating ”OperatingTemperature Range”, stresses above those listedin theTable ”Absolute Maximum Ratings”
may cause permanentdamageto thedevice. Theseare stress ratings only and operationofthe deviceat theseorany other
conditions above those indicatedinthe Operatingsectionsofthis specificationis notimplied. Exposureto Absolute Maximum
Rating conditionsfor extendedperiods may affectdevice reliability.Refer alsotothe STMicroelectronics SURE Programand other
relevant qualitydocuments. Minimum Voltagemay undershootto–2V duringtransitionandfor less than20ns. Dependson range.
Table2. Absolute Maximum Ratings(1)
OrganisationThe M29F002is organisedas 256Kx8. Memory
controlis providedby Chip EnableE, Output En-
ableG and Write EnableW inputs. Reset/Block Temporary Unprotection RPNC
(NOT availableon M29F002NT) tri-level input pro-
videsa hardwareresetwhen pulledLow, andwhen
held High (at VID) temporarily unprotects blocks
previously protected allowing themto be progra-
med and erased. Erase and Program operations
are controlledbyan internal Program/Erase Con-
troller(P/E.C.).StatusRegisterdataoutputon DQ7
providesa Data Polling signal, and DQ6 and DQ2
provide Toggle signalsto indicate the stateof the
P/E.C operations.
Memory BlocksThe devices feature asymmetrically blocked archi-
tecture providing system memory integration. The
M29F002 hasan arrayof7 blocks, one Boot Block16 KBytes, two Parameter Blocksof8 KBytes,
one Main Blockof 32KBytesandthree Main Blocks64 KBytes.
The memory mapis shownin Figure3. Each block
can be erased separately, any combinationof
blockscanbe specifiedfor multi-blockeraseor the
entire chip maybe erased. The Erase operations
aremanagedautomaticallybythe P/E.C.The block
eraseoperation can besuspendedin orderto read
fromor programto any block not being ersased,
and then resumed.Block protection provides addi-
tional data security. Each block canbe separately
protectedor unprotectedagainstProgramor Erase programming equipment. All previously pro-
tectedblockscanbe temporarilyunprotectedin the
application.
Bus OperationsThe following operations canbe performed using
the appropriatebus cycles:Read(Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby,Reset, Block Pro-
tection, Unprotection, Protection Verify,
Unprotection Verify and Block Temporary Unpro-
tection.See Tables4 and5.
Command InterfaceInstructions,madeupof commands writtenin cy-
cles, canbe givento the Program/EraseController
througha Command Interface (C.I.). For added
data protection,programor erase execution starts
after4 or6 cycles.The first, second, fourth and fifth
cycles are usedto input Coded cyclesto the C.I.
This Coded sequenceis the same for all Pro-
gram/Erase Controller instructions. The ’Com-
mand’itself andits confirmation, when applicable,
are givenon the third, fourthor sixth cycles. Any
incorrect commandor any improper commandse-
quencewill reset the deviceto Read Array mode.
3/29
M29F002T, M29F002NT, M29F002B
Address Range A17 A16 A15 A14 A1300000h-0FFFFh 0 0 X X X
10000h-1FFFFh 0 1 X X X
20000h-2FFFFh 1 0 X X X
30000h-37FFFh 1 1 0 X X
38000h-39FFFh 1110 0
3A000h-3BFFFh 1110 1
3C000h-3FFFFh 1111 X
Table 3A. M29F002T, M29F002NT Block Address Table
Address Range A17 A16 A15 A14 A1300000h-03FFFh 0000 X
04000h-05FFFh 0001 0
06000h-07FFFh 0001 1
08000h-0FFFFh 0 0 1 X X
10000h-1FFFFh 0 1 X X X
20000h-2FFFFh 1 0 X X X
30000h-3FFFFh 1 1 X X X
Table 3B. M29F002B Block Address TableAI02081C
16KBOOT BLOCK
3FFFFh
3C000h
3BFFFh
3A000h
39FFFh
00000h PARAMETER BLOCK PARAMETER BLOCK
32K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
M29F002T, M29F002NT
38000h
37FFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
0FFFFh
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
00000h PARAMETER BLOCK PARAMETER BLOCK
32K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
M29F002B
10000h
0FFFFh
08000h
07FFFh
06000h
05FFFh
04000h
03FFFh
16K BOOT BLOCK
Figure3. Memory Map and Block Address Table4/29
M29F002T, M29F002NT, M29F002B
InstructionsSeven instructions are definedto perform Read
Array, Auto Select(to readthe ElectronicSignature Block ProtectionStatus), Program, BlockErase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handlesall tim-
ing and verificationof the Program and Erase
operations.The Status Register Data Polling, Tog-
gle, Error bits may be readat any time, during
programmingor erase,to monitor the progressof
the operation.
Instructions are composedof upto six cycles. The
first two cycles inputa Coded sequenceto the
CommandInterfacewhich iscommontoall instruc-
tions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
outputthe addressed data,ElectronicSignatureor
Block Protection Status for Read operations.In
orderto giveadditional data protection,the instruc-
tionsfor Program and Blockor Chip Erase require
furthercommandinputs.ForaPrograminstruction,
the fourth command cycle inputs the address and
datato be programmed. Foran Erase instruction
(Blockor Chip), the fourth and fifth cycles inputa
further Coded sequence before the Erase confirm
commandon the sixth cycle. Erasureofa memory
blockmaybe suspended,in orderto readdata from
another blockorto program datain another block,
and then resumed.
When poweris first appliedorif VCC falls below
VLKO, the command interfaceis resetto Read
Array.
SIGNAL DESCRIPTIONSSee Figure1 and Table1.
Address Inputs (A0-A17). The addressinputsfor
thememory array are latchedduringa writeopera-
tionon the falling edgeof Chip EnableEor Write
EnableW. WhenA9is raisedto VID, eithera Read
ElectronicSignatureManufacturerorDeviceCode,
Block Protection Statusora WriteBlock Protection Block Unprotectionis enableddependingon the
combinationof levelson A0, A1, A6, A12and A15.
Data Input/Outputs(DQ0-DQ7). The inputis databe programmedin the memory arrayora com-
mandtobe writtento the C.I. Both are latchedon
the rising edgeof Chip EnableEor Write Enable The outputis data from the Memory Array, the
Electronic Signature Manufactureror Device
codes, the Block Protection Statusor the Status
register Data Pollingbit DQ7, the ToggleBits DQ6
and DQ2, the Errorbit DQ5or the Erase Timerbit
DQ3. Outputs are valid when Chip EnableE and
Output EnableG are active. The outputis high
impedance when the chipis deselectedor the
outputs are disabled and when RPNCisata Low
level.
Chip Enable (E). The Chip Enable input activates
the memory control logic, input buffers, decoders
andsenseamplifiers.E Highdeselectsthe memory
andreducesthe powerconsumptiontothe standby
level.E can alsobe usedto control writingto the
command register andto the memory array, while
Wremainsata low level.TheChip Enablemustbe
forcedto VID during the Block Unprotection opera-
tion.
Output Enable (G). The Output Enable gates the
outputs through the data buffers duringa read
operation. WhenGis High the outputs are High
impedance.G must be forcedto VID level during
Block Protection and Unprotection operations.
Write Enable(W). This input controls writingto the
Command Registerand Addressand Datalatches.
Reset/Block Temporary Unprotect/No Connect
Input (RPNC). The RPNC (not available for the
M29F002NT) input provides hardware reset and
protected block(s) temporary unprotection func-
tions.In reador write mode, the RPNC pin canbe
left open (Not Connected)or heldat VIH. Resetof
the memoryis acheivedby pulling RPNCtoVIL for
atleast 500ns.When the reset pulseis given,if the
memoryisin Reador Standby modes,it will be
availablefor newoperationsin 50nsafter the rising
edgeof RPNC.If the memoryisin Erase, Erase
Suspendor Program modes the reset will take
10μs.Ahardwarereset duringan Eraseor Program
operation will corrupt the data being programmed the sector(s) being erased.
Temporary block unprotectionis madeby holding
RPNCat VID.In this conditionpreviouslyprotected
blocks canbe programmedor erased. The transi-
tionof RPNC from VIHto VID must slower than
500ns. When RPNCis returnedfrom VIDto VIHall
blocks temporarily unprotected will be again pro-
tected.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
VSS Ground. VSSis the referenceforall voltage
measurements.
DEVICE OPERATIONSSee Tables4,5 and6.
Read. Read operations are usedto output the
contentsof the Memory Array, the Electronic Sig-
nature,the Status Registeror the Block Protection
Status. Both Chip EnableE and Output EnableG
must be lowin orderto read the outputof the
memory.
5/29
M29F002T, M29F002NT, M29F002B
Operation E G W RPNC(6) A0 A1 A6 A9 A12 A15 DQ0-DQ7Read Byte VIL VIL VIH VIH/NC(5) A0 A1 A6 A9 A12 A15 Data Output
Write Byte VIL VIH VIL VIH/NC(5) A0 A1 A6 A9 A12 A15 Data Input
Output Disable VIL VIH VIH VIH/NC(5) XX XXXX Hi-Z
Standby VIH XX VIH/NC(5) XX XXXX Hi-Z
Reset(6) XX X VIL XX XXXX Hi-Z
Block
Protection(2,4) VIL VID VIL Pulse VIH/NC(5) XX X VID XX X
Blocks
Unprotection(4) VID VID VIL Pulse VIH/NC(5) XX X VID VIH VIH X
Block
Protection
Verify(2,4) VIL VIL VIH VIH/NC(5) VIL VIH VIL VID A12 A15 Block Protect
Status(3)
Block
Unprotection
Verify(2,4) VIL VIL VIH VIH/NC(5) VIL VIH VIH VID A12 A15 Block Protect
Status(3)
Block
Temporary
Unprotection(6) XX X VID XX XXXX X
Notes:1.X =VILorVIH Block Address must begivenon A13-A17bits. See Table6. Operationperformedon programming equipment. RPNCcanbe heldatVIHorleft open (Not Connected).Not Availableon M29F002NT.
Table4. User Bus Operations(1)
Code Device E G W A0 A1 Other
Addresses DQ0- DQ7Manufact. Code VIL VIL VIH VIL VIL Don’t Care 20h
Device Code
M29F002T
M29F002NT VIL VIL VIH VIH VIL Don’t Care B0h
M29F002B VIL VIL VIH VIH VIL Don’t Care 34h
Table5. Read Electronic Signature (following AS instructionor with A9= VID)
Code E G W A0 A1 A13- A17 Other
Addresses DQ0- DQ7Protected Block VIL VIL VIH VIL VIH Block Address Don’t Care 01h
Unprotected Block VIL VIL VIH VIL VIH Block Address Don’t Care 00h
Table6. Read Block Protectionwith AS Instruction6/29
M29F002T, M29F002NT, M29F002B
Write. Write operationsareusedto giveInstruction
Commandsto the memoryorto latch inputdatato
beprogrammed.A write operationis initiatedwhen
Chip EnableEis Low and Write EnableWis Low
with Output EnableG High.Addressesare latched
onthefallingedgeofWorE whicheveroccurs last.
CommandsandInputData are latchedon therising
edgeofWorE whicheveroccurs first.
Output Disable. The dataoutputsare highimped-
ance when the Output EnableGis High with Write
EnableW High.
Standby. The memoryisin standby when Chip
EnableEis Highand the P/E.C.is idle. The power
consumptionis reducedto the standby level and
the outputs are high impedance, independentof
the Output EnableGor Write EnableW inputs.
Automatic Standby. After 150nsof bus inactivity
and when CMOS levels are driving theaddresses,
the chip automatically entersa pseudo-standby
mode where consumptionisreducedto the CMOS
standby value, while outputs still drive the bus.
Electronic Signature. Two codes identifying the
manufacturerand the device canbe read from the
memory. These codes allow programming equip-
mentor applicationsto automatically match their
interfaceto the characteristicsof the M29F002.
The Electronic Signatureis outputbya Read op-
eration when the voltageappliedtoA9isat VID and
addressinputA1is Low.Themanufacturercodeis
output when the Address input A0is Low and the
devicecode when thisinputis High. OtherAddress
inputs are ignored.
The Electronic Signature can alsobe read, without
raisingA9to VID,by giving the memory the Instruc-
tion AS.
Block Protection. Each block can be separately
protected against Programor Eraseon program-
ming equipment. Block protection provides addi-
tional data security,asit disablesall programor
erase operations. This modeis activated when
bothA9 andG are raisedto VID andan addressin
theblockis appliedon A13-A17. The BlockProtec-
tion algorithmis shownin Figure 14. Block protec-
tionis initiatedon the edgeofW fallingto VIL. Then
aftera delayof 100μs, the edgeofW risingto VIH
ends the protection operations. Block protection
verifyis achievedby bringingG,E, A0 and A6to
VIL and A1to VIH, whileWisat VIH and A9at VID.
Undertheseconditions, reading thedataoutputwill
yield 01hif the block defined by the inputs on
A13-A17is protected. Any attemptto programor
erasea protected block will be ignored by the
device.
Block Temporary Unprotection. This featureis
availableon M29F002T and M29F002B only. Any
previously protected block canbe temporarily un-
protectedin orderto change stored data. The
temporaryunprotectionmode isactivatedby bring-
ing RPNCto VID. During the temporary unprotec-
tion mode the previously protected blocks are
unprotected.A block canbe selectedand data can modifiedby executing the Eraseor Program
instructionwith the RPNC signal held atVID. When
RPNCis returnedto VIH, all the previously pro-
tected blocks are again protected.
Block Unprotection. All protected blocks canbe
unprotectedon programming equipmentto allow
updatingof bit contents.All blocks must first be
protectedbefore the unprotectionoperation.Block
unprotectionis activated when A9,G andE areat
VID and A12, A15at VIH. The Block Unprotection
algorithmis shownin Figure 15. Unprotectionis
initiatedby theedgeofW fallingto VIL. Aftera delay 10ms, the unprotection operationis ended by
risingWto VIH. Unprotection verifyis achievedby
bringingG andEto VIL while A0isat VIL, A6 and areat VIH and A9 remainsat VID.In these
conditions, reading the output data will yield 00hif
the block definedby the inputs A13-A17 has been
succesfullyunprotected.Eachblockmustbe sepa-
rately verified by givingits addressin orderto
ensure thatit has been unprotected.
INSTRUCTIONS AND COMMANDSThe Command Interface latches commands writ-
tento the memory. Instructions are madeup from
oneor more commandsto perform Read Memory
Array, Read Electronic Signature, ReadBlock Pro-
tection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
madeof addressand data sequences.
Hex Code Command00h Invalid/Reserved
10h Chip Erase Confirm
20h Reserved
30h Block Erase Resume/Confirm
80h Set-up Erase
90h Read Electronic Signature/
Block Protection Status
A0h Program
B0h Erase Suspend
F0h Read Array/Reset
Table7. Commands7/29
M29F002T, M29F002NT, M29F002B
Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc. (2,4) Read/Reset
Memory Array
Addr. (3,7) X Read Memory Array untila new write cycleis initiated.
Data F0h
Addr. (3,7) 555h AAAh 555h Read Memory Array untila new write
cycleis initiated.
Data AAh 55h F0h(4) Auto Select 3+
Addr. (3,7) 555h AAAh 555h Read Electronic Signatureor Block
Protection Status untila new write cycle initiated. See Note5 and6.
Data AAh 55h 90h Program 4
Addr. (3,7) 555h AAAh 555h Program
Address Read Data Pollingor Toggle
Bit until Program completes.
Data AAh 55h A0h Program
Data BlockErase 6
Addr. (3,7) 555h AAAh 555h 555h AAAh Block
Address
Additional
Block(8)
Data AAh 55h 80h AAh 55h 30h 30h Chip Erase 6
Addr. (3,7) 555h AAAh 555h 555h AAAh 555h Note9
Data AAh 55h 80h AAh 55h 10h(10) Erase
Suspend 1
Addr. (3,7) X Read until Toggle stops, then readallthe data needed from
any Block(s) not being erased then Resume Erase.
Data B0h Erase
Resume 1
Addr. (3,7) X Read Data Pollingor Toggle Bits until Erase completesor
Eraseis suspended another time
Data 30h
Notes:1. Commandsnot interpretedin thistablewill defaultto read array mode. Awaitof tPLYHis necessaryaftera Read/Resetcommandifthe memory wasinan Eraseor Program mode
before startingany new operation (see Table14 and Figure9).X= Don’t Care. Thefirst cyclesof theRDorAS instructionsare followedby read operations.Any numberof read cyclescan occur after
the command cycles. Signature Address bitsA0,A1atVIL willoutputManufacturer code (20h). Addressbits A0atVIH andA1atVIL willoutput
Device code. Block Protection Address:A0at VIL,A1atVIHand A13-A17withinthe Blockwill outputthe BlockProtectionstatus. For Coded cycles address inputs A12-A17are don’t care. Optional, additional Blocks addresses mustbe entered withinthe erasetimeout delay afterlast writeentry,
timeout status canbe verified throughDQ3 value (see EraseTimerBit DQ3description).
Whenfull commandis entered,read Data Pollingor Togglebit until Eraseis completedor suspended. Read Data Polling, TogglebitsorRB until Erase completes.
10.During Erase Suspend, Readand Data Program functionsare allowedin blocks notbeingerased.
Table8. Instructions(1)The instructions requirefrom1to6 cycles, the first first threeof which are always write operations
usedto initiate theinstruction.Theyarefollowedby
either further write cyclesto confirm the first com-
mandor executethe commandimmediately.Com-
mand sequencing must be followed exactly. Any
invalid combinationof commands will reset the
deviceto Read Array. The increased numberof
cycles has been chosento assure maximum data
security. Instructions are initialised by two initial
Coded cycles which unlock the Command Inter-
face.In addition,for Erase, instruction confirmation again precededby the two Coded cycles.
Status Register BitsP/E.C. statusis indicatedduring executionby Data
Polling on DQ7, detectionofT oggleon DQ6 and
DQ2,or Erroron DQ5 and Erase Timer DQ3 bits.
Any read attempt during Programor Erase com-
mandexecution will automatically outputthesefive
Status Register bits. TheP/E.C. automatically sets
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
(DQ0, DQ1 and DQ4) are reservedfor future use
and shouldbe masked. See Tables9 and 10.
8/29
M29F002T, M29F002NT, M29F002B
Name Logic Level Definition Note DataPolling
’1’ Erase Completeor erase
blockin Erase Suspend
Indicatesthe P/E.C. status, check during
Programor Erase, andon completion
before checking bits DQ5for Programor
Erase Success.
’0’ Erase On-going
Program Completeor data non erase block during
Erase Suspend Program On-going ToggleBit
’-1-0-1-0-1-0-1-’ Eraseor Program On-going Successive reads outputcomplementary
dataon DQ6 while Programming orErase
operationsare on-going. DQ6 remainsat
constant level when P/E.C. operations are
completedor Erase Suspendis
acknowledged. Program Complete
’-1-1-1-1-1-1-1-’
Erase Completeor Erase
Suspendon currently
addressed block ErrorBit ’1’ Programor Erase Error This bitissetto’1’inthe caseof
Programmingor Erase failure.’0’ Programor Erase On-going Reserved Erase
TimeBit
’1’ Erase Timeout Period Expired
P/E.C. Erase operationhas started. Only
possible command entryis Erase Suspend
(ES).
’0’ Erase Timeout Period
On-going additionalblocktobe erasedin parallel
canbe enteredtothe P/E.C. ToggleBit
’-1-0-1-0-1-0-1-’
Chip Erase, Eraseor Erase
Suspendon the currently
addressed block.
Erase Error duetothe
currently addressed block
(when DQ5= ’1’). Indicatesthe erase status and allowsto
identifythe erased block
Program on-going, Erase
on-goingon another blockor
Erase Complete Erase Suspend readon
non Erase Suspend block Reserved Reserved
Notes:Logic level ’1’is High,’0’is Low. -0-1-0-0-0-1-1-1-0- representbit valuein successive Read operations.
Table9. Status Register Bits
Data Polling Bit (DQ7). When Programming op-
erations arein progress, thisbit outputs the com-
plementof the bit being programmed on DQ7.
During Erase operation,it outputsa ’0’. After com-
pletionof the operation, DQ7 will outputthebit last
programmedora’1’ after erasing. Data Pollingis
valid and only effective during P/E.C. operation,
thatis after the fourthW pulsefor programmingor
after the sixthW pulsefor erase.It must be per-
formedat the address being programmedoratan
address within the block being erased.Ifall the
blocks selectedforerasureare protected,DQ7 will setto’0’ forabout 100μs, and then returnto the
previous addressedmemory data value.
9/29
M29F002T, M29F002NT, M29F002B
See Figure11 for the Data Polling flowchart and
Figure10for the Data Pollingwaveforms.DQ7 will
also flag the Erase Suspend modeby switching
from’0’to’1’at the startof the Erase Suspend.In
orderto monitor DQ7in the Erase Suspend mode address withina block being erased must be
provided.Fora Read Operationin Erase Suspend
mode, DQ7 will output’1’if the readis attempted
ona blockbeingerasedand thedatavalueonother
blocks. During Program operationin Erase Sus-
pend Mode, DQ7 will have the same behaviouras the normal program execution outsideof the
suspendmode.
Toggle Bit (DQ6). WhenProgrammingor Erasing
operationsarein progress,successiveattemptsto
readDQ6will outputcomplementarydata. DQ6will
toggle following togglingof eitherG,orE whenG low. The operationis completed when two suc-
cessivereadsyield the same output data.Thenext
readwill outputthe bitlastprogrammedora ’1’after
erasing. The toggle bit DQ6is valid only during
P/E.C. operations, thatis after the fourthW pulse
for programmingor after the sixth W pulse for
Erase.If the blocks selected for erasure are pro-
tected, DQ6 will toggle for about 100μs and then
returnbackto Read. DQ6willbe setto ’1’ifa Read
operationisattemptedon anEraseSuspendblock.
When eraseis suspended DQ6 will toggle during
programming operationsina blockdifferentto the
blockin Erase Suspend.EitherEorG toggling will
cause DQ6to toggle. See Figure12for ToggleBit
flowchart and Figure13 for ToggleBit waveforms.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, canbe usedto determine the device status
duringthe Erase operations.It can alsobe usedto
identify the block being erased. During Eraseor
Erase Suspenda read froma block being erased
will cause DQ2to toggle.A read froma block not
being erased will set DQ2to’1’ during erase and DQ2 during Erase Suspend. During Chip Erase read operation will cause DQ2to toggleasall
blocks are being erased. DQ2 will be setto ’1’
during program operation and when eraseis com-
plete. After erase completion andif the errorbit
DQ5is setto ’1’, DQ2 will toggleif the faulty block addressed.
Error Bit (DQ5). Thisbitis setto’1’by the P/E.C.
when thereisa failureof programming, block
erase,or chip erase that resultsin invalid datain
thememoryblock.In caseofan errorin blockerase program,the blockin which the error occuredor which the programmed data belongs, mustbe
discarded. The DQ5 failure condition will also ap-
pearifa usertriesto programa’1’toa locationthat previously programmedto ’0’. OtherBlocks may
stillbe used.The errorbit resetsaftera Read/Reset
(RD)instruction.In caseof successof Programor
Erase, the errorbit willbe setto’0’.
Erase Timer Bit (DQ3). Thisbitis setto’0’by the
P/E.C. when the last block Erase command has
been enteredto the Command Interface anditis
awaiting the Erase start. When the erase timeout
periodis finished,after 50μsto 120μs, DQ3 returns ’1’.
Coded CyclesThe two Coded cycles unlock the Command Inter-
face. They are followedbyan input commandora
confirmation command. The Coded cycles consist writing the data AAhat address 555h duringthe
first cycle. During the second cycle the Coded
cycles consistof writing the data 55hat address
AAAh. The addresslinesA0to A11are valid,other
address lines are ’don’t care’. The Coded cycles
happenon first and secondcyclesof the command
writeor on thefourth and fifth cycles.
InstructionsSee Table8.
Read/Reset (RD) Instruction. The Read/Reset
instruction consistsof one write cycle giving the
command F0h.It canbe optionallyprecededby the
twoCoded cycles. Subsequentreadoperationswill
read the memory array addressed and output the
data read.A wait stateof 10μsis necessary after
Read/Reset priorto any valid readif the memory
wasin an Erase mode when the RD instructionis
given.
Mode DQ7 DQ6 DQ2Program DQ7 Toggle 1
Erase 0 Toggle Note1
Erase Suspend Read
(in Erase Suspend
block) 1 Toggle
Erase Suspend Read
(outside Erase Suspend
block)
DQ7 DQ6 DQ2
Erase Suspend Program DQ7 Toggle N/A
Note:1. Toggleifthe addressis withina block being erased.
’1’ifthe addressis withina blocknot being erased.
Table 10. Pollingand Toggle Bits10/29
M29F002T, M29F002NT, M29F002B
AI01275B
High Speed
1.5V
2.4V
Standard
0.45V
2.0V
0.8V
Figure4. AC TestingInput Output WaveformAI01276B
1.3V
OUTL= 30pF forHigh Speed= 100pFfor Standard includes JIGcapacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Figure5. AC Testing Load Circuit
Symbol Parameter Test Condition Min Max UnitCIN Input Capacitance VIN =0V 6 pF
COUT Output Capacitance VOUT =0V 12 pF
Note:1. Sampled only,not 100% tested.
Table 12. Capacitance(1) (TA =25 °C,f=1 MHz)
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followedby one write
cycle giving the command90hto address555hfor
command set-up. Asubsequentreadwill outputthe
manufacturer code and the device codeor the
block protection status dependingon the levelsof and A1. The manufacturer code, 20h,is output
when the addresses lines A0 and A1 are Low, the
devicecodeis outputwhen A0isHigh withA1 Low.
The AS instruction also allows accessto the block
protectionstatus.AftergivingtheASinstruction,A0 setto VIL with A1at VIH, while A13-A17 define
the addressof the blocktobe verified.A readin
these conditions will outputa 01hif the blockis
protectedanda 00hif the blockis not protected.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0his
writtento address 555hon the third cycle after two
Coded cycles.A fourth write operation latches the
Addresson the falling edgeofWorE and the Data be written on the rising edge and starts the
P/E.C. Read operationsoutputthe StatusRegister
bits after the programming has started. Memory
programmingis made onlyby writing’0’in placeof
’1’. Status bits DQ6 and DQ7determineif program-
mingis on-goingand DQ5allowsverificationof any
possible error. Programmingatan address notin
blocks being erasedis also possible during erase
suspend.In this case, DQ2 will toggleat the ad-
dress being programmed.
High Speed StandardInput Rise and Fall Times ≤ 10ns ≤ 10ns
Input Pulse Voltages 0to3V 0.45V to2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and2V
Table 11. AC Measurement Conditions11/29
M29F002T, M29F002NT, M29F002B
Symbol Parameter Test Condition Min Max UnitILI(2) Input LeakageCurrent 0V≤VIN≤ VCC ±1 μA
ILO Output Leakage Current 0V≤ VOUT≤ VCC ±1 μA
ILR1 RPNC Leakage Current High RPNC= VCC ±1 μA
ILR2 RPNC Leakage Current Low RPNC= VSS –0.2 –10 μA
ICC1 Supply Current (Read) TTLByte E= VIL,G= VIH,f= 6MHz 20 mA
ICC2 Supply Current (Standby) TTL E=VIH 1mA
ICC3 Supply Current (Standby) CMOS E= VCC± 0.2V 100 μA
ICC4(1) Supply Current (Programor Erase) Byte program, Blockor
Chip Erase inprogress 20 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 2 VCC+ 0.5 V
VOL Output Low Voltage IOL= 5.8mA 0.45 V
VOH Output High Voltage TTL IOH= –2.5mA 2.4 V
Output High Voltage CMOS IOH= –100μAVCC –0.4V V
VID A9,E,G, RPNC High Voltage 11.5 12.5 V
IID A9,E,G, RPNC High Current A9,E,Gor RPNC=VID 100 μA
VLKO Supply Voltage(Erase and
Program lock-out) 3.2 4.2 V
Note:1. Sampled only,not 100% tested. ExceptRPNC.
Table 13. DC Characteristics(TA=0to 70°Cor –40to 85°C; VCC =5V± 10%)
Block Erase (BE) Instruction. This instruction
usesa minimumof six write cycles. The Erase
Set-upcommand80his writtento address555hon
third cycle after the two Coded cycles. The Block
EraseConfirmcommand 30his similarly writtenon
the sixth cycle after another two Coded cycles.
During the inputof the second command an ad-
dress within the blockto be erasedis given and
latched into the memory. Additional block Erase
Confirm commands and block addresses can be
written subsequentlyto erase other blocksin par-
allel, without further Coded cycles. The erase will
start after the erase timeout period (see Erase
TimerBit DQ3 description). Thus, additionalErase
Confirm commandsfor other blocks mustbe given
within this delay. Theinputofa new EraseConfirm
commandwillrestartthetimeout period. Thestatus the internal timer canbe monitored through the
levelof DQ3,if DQ3is’0’ the Block Erase Com-
mand has been given and the timeoutis running,if
DQ3is ’1’, the timeout has expired and the P/E.C. erasing the Block(s).If the second command
givenis notaneraseconfirmorif theCodedcycles
are wrong, the instruction aborts, and thedeviceis
resetto ReadArray.Itis not necessaryto program
the block with 00has the P/E.C. will do this auto-
maticallybeforeto erasingto FFh.Readoperations
after the sixth rising edgeofWorE output the
status register status bits.
Duringthe executionof theeraseby the P/E.C.,the
memory accepts only the Erase Suspend ES and
Read/Reset RD instructions. Data Pollingbit DQ7
returns’0’ while the erasureisin progress and’1’
whenit has completed. The Togglebit DQ2 and
DQ6 toggle during the erase operation. They stop
when eraseis completed. After completion the
StatusRegisterbit DQ5returns’1’ ifthere has been erase failure.In sucha situation,theT ogglebit
DQ2 canbe usedto determine which blockis not
correctly erased.In the caseof erase failure,a
Read/ResetRDinstructionis necessaryin orderto
reset the P/E.C.
12/29
M29F002T, M29F002NT, M29F002B
Symbol Alt Parameter Test Condition
M29F002T/ M29F002NT/ M29F002B
Unit
-70 -90 -120
VCC =5V±
10% VCC =5V±
10% VCC =5V±
10%
Standard
Interface
Standard
Interface
Standard
Interface
Min Max Min Max Min MaxtAVAV tRC Address Validto
Next Address Valid E=VIL,G=VIL 70 90 120 ns
tAVQV tACC Address Validto
Output Valid E=VIL,G=VIL 70 90 120 ns
tELQX(1) tLZ Chip Enable Lowto
Output Transition G=VIL 00 0 ns
tELQV(2) tCE Chip Enable Lowto
Output Valid G=VIL 70 90 120 ns
tGLQX(1) tOLZ Output Enable Low Output Transition E=VIL 00 0 ns
tGLQV(2) tOE Output Enable Low Output Valid E=VIL 30 35 50 ns
tEHQX tOH Chip Enable Highto
Output Transition G=VIL 00 0 ns
tEHQZ(1) tHZ Chip Enable Highto
Output Hi-Z G=VIL 20 20 30 ns
tGHQX tOH Output Enable High Output Transition E=VIL 00 0 ns
tGHQZ(1) tDF Output Enable High Output Hi-Z E=VIL 20 20 30 ns
tAXQX tOH Address Transition Output Transition E=VIL,G=VIL 00 0 ns
tPLEL(1,3) tREADY RPNC Lowto Read
Mode 10 10 10 μs
tPHEL tRSP RPNC Highto Chip
Enable Low 50 50 50 ns
tPLPX tRP RPNC Pulse Width 500 500 500 ns
Notes:1. Sampled only,not 100% tested.G maybe delayedbyupto tELQV-tGLQV afterthefallingedge ofE withoutincreasing tELQV.Tobe considered onlyifthe Reset pulseis given whilethe memoryisin Erase mode.
Table 14. ReadAC Characteristics(TA=0to 70°Cor –40to 85°C)
13/29
M29F002T, M29F002NT, M29F002B
AI02082
tAVAV
tAVQV
tAXQX
tELQX
tEHQX
tGLQV
tGLQX
tGHQX
VALID
A0-A17 E G DQ0-DQ7
tELQV
VALID
ADDRESS
VALID
AND
CHIP
ENABLE
OUTPUT
ENABLE
DATA
VALID
tEHQZ
tGHQZ
Figure6. Read Mode AC Waveformsite
abl
14/29
M29F002T, M29F002NT, M29F002B
Symbol Alt Parameter
M29F002T/ M29F002NT/ M29F002B
Unit
-70 -90 -120
VCC =5V±
10% VCC =5V±
10% VCC =5V±
10%
Standard
Interface
Standard
Interface
Standard
Interface
Min Max Min Max Min MaxtAVAV tWC Address Validto Next Address
Valid 70 90 120 ns
tELWL tCS Chip Enable Lowto Write Enable
Low 000 ns
tWLWH tWP Write Enable Lowto Write Enable
High 35 45 50 ns
tDVWH tDS Input Validto WriteEnable High 30 45 50 ns
tWHDX tDH Write Enable Highto Input
Transition 000 ns
tWHEH tCH Write Enable Highto Chip Enable
High 000 ns
tWHWL tWPH Write Enable Highto Write Enable
Low 20 20 20 ns
tAVWL tAS Address Validto Write Enable Low 5 5 5 ns
tWLAX tAH Write Enable Lowto Address
Transition 45 45 50 ns
tGHWL Output Enable Highto Write
Enable Low 000 ns
tVCHEL tVCS VCCHighto Chip Enable Low 50 50 50 μs
tWHGL tOEH Write Enable Highto Output
Enable Low 000 ns
tPHPHH (1,2) tVIDR RPNC Rise TimetoVID 500 500 500 ns
tPLPX tRP RPNC Pulse Width 500 500 500 ns
Notes:1. Sample only, not100% tested. This timingisfor Temporary Block Unprotectionoperation.
Table 15. Write AC Characteristics,Write Enable Controlled(TA=0to 70°Cor –40to 85°C)
ChipErase (CE) Instruction. Thisinstructionuses
six write cycles. The Erase Set-up command 80h writtento address 555hon the third cycle after
the two Coded cycles. The Chip Erase Confirm
command 10his similarly writtenon the sixth cycle
after another two Coded cycles.If the second
command givenis notan erase confirmorif the
Codedcyclesare wrong, theinstruction abortsand
thedeviceisresetto Read Array.Itis notnecessary
toprogram thearray with00h first astheP/E.C. will
automaticallydo this before erasingittoFFh. Read
operations after the sixth rising edgeofWorE
output the Status Register bits. During the execu-
tionof theeraseby the P/E.C.,DataPollingbit DQ7
returns ’0’, then’1’on completion. The Toggle bits
DQ2 and DQ6 toggle during erase operation and
stop wheneraseis completed.Aftercompletionthe
StatusRegisterbit DQ5returns’1’ ifthere has been Erase Failure.
15/29
M29F002T, M29F002NT, M29F002B
