M29DW323DT-70ZE6E ,32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block 3V Supply Flash MemoryM29DW323DTM29DW323DB32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block)3V Supply Flash Memory
M29DW323DT70ZE6F ,32 Mbit 4Mb x8 or 2Mb x16 / Dual Bank 8:24 / Boot Block 3V Supply Flash MemoryAbsolute Maximum Ratings 22DC and AC PARAMETERS . 23Table 10. Operating and AC Measureme ..
M29DW324DB70N6 ,32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 16:16, Boot Block 3V Supply Flash Memory
M29DW324DB-70N6 ,32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 16:16, Boot Block 3V Supply Flash Memory
M29DW324DB-70N6 ,32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 16:16, Boot Block 3V Supply Flash Memory
M29DW324DB70N6E ,32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 16:16, Boot Block 3V Supply Flash Memory
M50427FP , CD PLAYER DIGITAL SIGNAL PROCESSOR
M50427FP , CD PLAYER DIGITAL SIGNAL PROCESSOR
M50436-689SP , SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
M50734SP-10 , 8-BIT CMOS MICROCOMPUTER
M50734SP-10 , 8-BIT CMOS MICROCOMPUTER
M50747-161SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M29DW323DB70N6-M29DW323DB-70N6-M29DW323DB70N6E-M29DW323DB-70N6E-M29DW323DB70ZE6-M29DW323DB-70ZE6-M29DW323DB-90N6-M29DW323DT-70N6-M29DW323DT70N6E-M29DW323DT-70ZE6-M29DW323DT70ZE6E-M29DW323DT-70ZE6E
32 MBIT (4MB X8 OR 2MB X16, DUAL BANK 8:24, BOOT BLOCK) 3V SUPPLY FLASH MEMORY
1/51December 2004
M29DW323DT
M29DW323DB32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY SUPPLY VOLTAGE
–VCC = 2.7V to 3.6V for Program, Erase
and Read
–VPP =12V for Fast Program (optional) ACCESS TIME: 70ns PROGRAMMING TIME 10µs per Byte/Word typical Double Word/ Quadruple Byte Program MEMORY BLOCKS Dual Bank Memory Array: 8Mbit+24Mbit Parameter Blocks (Top or Bottom
Location) DUAL OPERATIONS Read in one bank while Program or Erase
in other ERASE SUSPEND and RESUME MODES Read and Program another Block during
Erase Suspend UNLOCK BYPASS PROGRAM COMMAND Faster Production/Batch Programming VPP/WP PIN for FAST PROGRAM and
WRITE PROTECT TEMPORARY BLOCK UNPROTECTION
MODE COMMON FLASH INTERFACE 64 bit Security Code EXTENDED MEMORY BLOCK Extra block used as security block or to
store additional information LOW POWER CONSUMPTION Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 0020h Top Device Code M29DW323DT: 225Eh Bottom Device Code M29DW323DB:
225Fh
M29DW323DT, M29DW323DB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 4. TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 5. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 6. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VCC Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 3. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 4. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Auto Select Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3/51
M29DW323DT, M29DW323DB
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Fast Program Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Unlock Bypass Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Enter Extended Block Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Exit Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Block Protect and Chip Unprotect Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 5. Commands, 16-bit mode, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 6. Commands, 8-bit mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 7. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . .18
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 8. Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 9. Dual Operations Allowed In the Other Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 10. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Table 12. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 10.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 13. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 11.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 15. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 12.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 16. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 13.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
M29DW323DT, M29DW323DBTable 17. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 14.Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled . . . . . . . . . . . .29
Figure 15.Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled . . . . . . . . . .29
Table 18. Toggle and Alternative Toggle Bits AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 16.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 19. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 17.Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Figure 18.TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline. .31
Table 20. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data . . . . .31
Figure 19.TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline. . . . . .32
Table 21. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data. . . . . . . . .32
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
APPENDIX A.BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Table 23. Top Boot Block Addresses, M29DW323DT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 24. Bottom Boot Block Addresses, M29DW323DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40Table 25. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 26. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 27. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 28. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 29. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 30. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
APPENDIX C.EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43Table 31. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
APPENDIX D.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44Table 32. Programmer Technique Bus Operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 20.Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 21.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 22.In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 23.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49Table 33. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5/51
M29DW323DT, M29DW323DB
SUMMARY DESCRIPTIONThe M29DW323D is a 32 Mbit (4Mb x8 or 2Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode.
The device features an asymmetrical block archi-
tecture. The M29DW323D has an array of 8 pa-
rameter and 63 main blocks and is divided into two
Banks, A and B, providing Dual Bank operations.
While programming or erasing in Bank A, read op-
erations are possible in Bank B and vice versa.
Only one bank at a time is allowed to be in pro-
gram or erase mode. The bank architecture is
summarized in Table 2. M29DW323DT locates the
Parameter Blocks at the top of the memory ad-
dress space while the M29DW323DB locates the
Parameter Blocks starting from the bottom.
M29DW323D has an extra 32 KWord (x16 mode)
or 64 KByte (x8 mode) block, the Extended Block,
that can be accessed using a dedicated com-
mand. The Extended Block can be protected and
so is useful for storing security information. How-
ever the protection is irreversible, once protected
the protection cannot be undone.
Each block can be erased independently so it is
possible to preserve valid data while old data is
erased. The blocks can be protected to prevent
accidental Program or Erase commands from
modifying the memory. Program and Erase com-
mands are written to the Command Interface of
the memory. An on-chip Program/Erase Controller
simplifies the process of programming or erasing
the memory by taking care of all of the special op-
erations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions identi-
fied. The command set required to control the
memory is consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP48 (12x20mm), and
TFBGA48 (6x8mm, 0.8mm pitch) packages. The
memory is supplied with all the bits erased (set to
’1’).
Table 1. Signal Names
M29DW323DT, M29DW323DB
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M29DW323DT, M29DW323DB
M29DW323DT, M29DW323DB
9/51
M29DW323DT, M29DW323DB
M29DW323DT, M29DW323DB
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
1., Signal Names, for a brief overview of the sig-
nals connected to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
VIH. When BYTE is Low, VIL, these pins are not
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
VPP/Write Protect (VPP/WP). The VPP/Write
Protect pin provides two functions. The VPP func-
tion allows the memory to use an external high
voltage power supply to reduce the time required
for Program operations. This is achieved by by-
passing the unlock cycles and/or using the Dou-
ble Word or Quadruple Byte Program commands.
The Write Protect function provides a hardware
method of protecting the two outermost boot
blocks.
When VPP/Write Protect is Low, VIL, the memory
protects the two outermost boot blocks; Program
and Erase operations in these blocks are ignored
while VPP/Write Protect is Low, even when RP is
at VID.
When VPP/Write Protect is High, VIH, the memory
reverts to the previous protection status of the two
outermost boot blocks. Program and Erase oper-
ations can now modify the data in these blocks un-
less the blocks are protected using Block
Protection.
When VPP/Write Protect is raised to VPP the mem-
ory automatically enters the Unlock Bypass mode.
When VPP/Write Protect returns to VIH or VIL nor-
mal operation resumes. During Unlock Bypass
Program operations the memory draws IPP from
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
VIH to VPP and from VPP to VIH must be slower
than tVHVPP, see Figure 17.
Never raise VPP/Write Protect to VPP from any
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
The VPP/Write Protect pin must not be left floating
or unconnected or the device may become unreli-
able. A 0.1µF capacitor should be connected be-
tween the VPP/Write Protect pin and the VSS
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
Unlock Bypass Program, IPP.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if VPP/WP is at VIL, then the two outer-
most boot blocks will remain protected even if RP
is at VID.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/Busy
Output section, Table 19. and Figure 16., Reset/
Block Temporary Unprotect AC Waveforms, for
more details.
Holding RP at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
11/51
M29DW323DT, M29DW323DB
operation. During Program or Erase operations
Ready/Busy is Low, VOL. Ready/Busy is high-im-
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 19. and Figure
16., Reset/Block Temporary Unprotect AC Wave-
forms.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
memory. When Byte/Word Organization Select is
Low, VIL, the memory is in x8 mode, when it is
High, VIH, the memory is in x16 mode.
VCC Supply Voltage (2.7V to 3.6V). VCC pro-
vides the power supply for all operations (Read,
Program and Erase).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase operations, ICC3.
VSS Ground. VSS is the reference for all voltage
measurements. The device features two VSS pins
which must be both connected to the system
ground.
M29DW323DT, M29DW323DB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby.
The Dual Bank architecture of the M29DW323 al-
lows read/write operations in Bank A, while read
operations are being executed in Bank B or vice
versa. Write operations are only allowed in one
bank at a time.
See Tables 3 and 4, Bus Operations, for a summa-
ry. Typically glitches of less than 5ns on Chip En-
able or Write Enable are ignored by the memory
and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 11., Read Mode AC Waveforms,
and Table 15., Read AC Characteristics, for de-
tails of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, VIH, during the whole Bus
Write operation. See Figures 12 and 13, Write AC
Waveforms, and Tables 16 and 17, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 14., DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations un-
til the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require VID to be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3 and 4, Bus Operations.
Block Protect and Chip Unprotect. Groups of
blocks can be protected against accidental Pro-
gram or Erase. The Protection Groups are shown
in APPENDIX A., Tables 23 and 24, Block Ad-
dresses. The whole chip can be unprotected to al-
low the data inside the blocks to be changed.
The VPP/Write Protect pin can be used to protect
the two outermost boot blocks. When VPP/Write
Protect is at VIL the two outermost boot blocks are
protected and remain protected regardless of the
Block Protection Status or the Reset/Block Tem-
porary Unprotect pin status.
Block Protect and Chip Unprotect operations are
described in APPENDIX D.
13/51
M29DW323DT, M29DW323DB
Table 3. Bus Operations, BYTE = VIL
Note: X = VIL or VIH.
Table 4. Bus Operations, BYTE = VIH
Note: X = VIL or VIH.
M29DW323DT, M29DW323DB
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes de-
pending on whether the memory is in 16-bit or 8-
bit mode. See either Table 5, or 6, depending on
the configuration that is being used, for a summary
of the commands.
Read/Reset Command
The Read/Reset command returns the memory to
its Read mode. It also resets the errors in the Sta-
tus Register. Either one or three Bus Write opera-
tions can be used to issue the Read/Reset
command.
The Read/Reset command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. If the Read/Reset command is issued
during the time-out of a Block erase operation then
the memory will take up to 10µs to abort. During
the abort period no valid data can be read from the
memory. The Read/Reset command will not abort
an Erase operation when issued while in Erase
Suspend.
Auto Select Command
The Auto Select command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status and the Extended Memory Block
Verify Code. It can be addressed to either Bank.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. The fi-
nal Write cycle must be addressed to one of the
Banks. Once the Auto Select command is issued
Bus Read operations to the Bank where the com-
mand was issued output the Auto Select data. Bus
Read operations to the other Bank will output the
contents of the memory array. The memory re-
mains in Auto Select mode until a Read/Reset or
CFI Query command is issued.
In Auto Select mode the Manufacturer Code can
be read using a Bus Read operation with A0 = VIL
and A1 = VIL and A19-A20 = Bank Address. The
other address bits may be set to either VIL or VIH.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL and A19-A20
= Bank Address. The other address bits may be
set to either VIL or VIH.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,= VIH, A19-A20 = Bank Address and A12-A18
specifying the address of the block inside the
Bank. The other address bits may be set to either
VIL or VIH. If the addressed block is protected then
01h is output on Data Inputs/Outputs DQ0-DQ7,
otherwise 00h is output.
Read CFI Query Command
The Read CFI Query Command is used to read
data from the Common Flash Interface (CFI)
Memory Area. This command is valid when the de-
vice is in the Read Array mode, or when the device
is in Auto Select mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is-
sued subsequent Bus Read operations read from
the Common Flash Interface Memory Area.
The Read/Reset command must be issued to re-
turn the device to the previous mode (the Read Ar-
ray mode or Auto Select mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Auto Select
mode.
See APPENDIX B., Tables 25, 26, 27, 28, 29 and
30 for details on the information contained in the
Common Flash Interface (CFI) memory area.
Program Command
The Program command can be used to program a
value to one address in the memory array at a
time. The command requires four Bus Write oper-
ations, the final write operation latches the ad-
dress and data, and starts the Program/Erase
Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. After
programming has started, Bus Read operations in
the Bank being programmed output the Status
Register content, while Bus Read operations to
the other Bank output the contents of the memory
array. See the section on the Status Register for
more details. Typical program times are given in
Table 7.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg-
ister. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
15/51
M29DW323DT, M29DW323DB
Fast Program Commands
There are two Fast Program commands available
to improve the programming throughput, by writing
several adjacent words or bytes in parallel. The
Quadruple Byte Program command is available for
x8 operations, while the Double Word Program
command is available for x16 operations.
Quadruple Byte Program Command. The Qua-
druple Byte Program command is used to write a
page of four adjacent Bytes in parallel. The four
bytes must differ only for addresses A0, DQ15A-1.
Five bus write cycles are necessary to issue the
Quadruple Byte Program command. The first bus cycle sets up the Quadruple Byte
Program Command. The second bus cycle latches the Address and
the Data of the first byte to be written. The third bus cycle latches the Address and
the Data of the second byte to be written. The fourth bus cycle latches the Address and
the Data of the third byte to be written. The fifth bus cycle latches the Address and the
Data of the fourth byte to be written and starts
the Program/Erase Controller.
Double Word Program Command. The Double
Word Program command is used to write a page
of two adjacent words in parallel. The two words
must differ only for the address A0.
Three bus write cycles are necessary to issue the
Double Word Program command. The first bus cycle sets up the Double Word
Program Command. The second bus cycle latches the Address and
the Data of the first word to be written. The third bus cycle latches the Address and
the Data of the second word to be written and
starts the Program/Erase Controller.
Only one bank can be programmed at any one
time. The other bank must be in Read mode or
Erase Suspend.
Programming should not be attempted when VPP
is not at VPPH.
After programming has started, Bus Read opera-
tions in the Bank being programmed output the
Status Register content, while Bus Read opera-
tions to the other Bank output the contents of the
memory array.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg-
ister. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
Note that the Fast Program commands cannot
change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Typical Program times are given in Table
7., Program, Erase Times and Program, Erase
Endurance Cycles.
Unlock Bypass Command
The Unlock Bypass command is used in conjunc-
tion with the Unlock Bypass Program command to
program the memory faster than with the standard
program commands. When the cycle time to the
device is long, considerable time saving can be
made by using these commands. Three Bus Write
operations are required to issue the Unlock By-
pass command.
Once the Unlock Bypass command has been is-
sued the bank enters Unlock Bypass mode. When
in Unlock Bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands
are valid. The Unlock Bypass Program command
can be issued to program addresses within the
bank, and the Unlock Bypass Reset command to
return the bank to Read mode. In Unlock Bypass
mode the memory can be read as if in Read mode.
When VPP is applied to the VPP/Write Protect pin
the memory automatically enters the Unlock By-
pass mode and the Unlock Bypass Program com-
mand can be issued immediately.
Unlock Bypass Program Command
The Unlock Bypass Program command can be
used to program one address in the memory array
at a time. The command requires two Bus Write
operations, the final write operation latches the ad-
dress and data, and starts the Program/Erase
Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. The
operation cannot be aborted, a Bus Read opera-
tion to the Bank where the command was issued
outputs the Status Register. See the Program
command for details on the behavior.
Unlock Bypass Reset Command
The Unlock Bypass Reset command can be used
to return to Read/Reset mode from Unlock Bypass
Mode. Two Bus Write operations are required to
issue the Unlock Bypass Reset command. Read/
Reset command does not exit from Unlock Bypass
Mode.
Chip Erase Command
The Chip Erase command can be used to erase
the entire chip. Six Bus Write operations are re-
quired to issue the Chip Erase Command and start
the Program/Erase Controller.
M29DW323DT, M29DW323DB
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands, including the Erase Suspend com-
mand. It is not possible to issue any command to
abort the operation. Typical chip erase times are
given in Table 7. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the sec-
tion on the Status Register for more details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command
The Block Erase command can be used to erase
a list of one or more blocks in a Bank. It sets all of
the bits in the unprotected selected blocks to ’1’.
All previous data in the selected blocks is lost.
Six Bus Write operations are required to select the
first block in the list. Each additional block in the
list can be selected by repeating the sixth Bus
Write operation using the address of the additional
block. All blocks must belong to the same Bank; if
a block belonging to the other Bank is given it will
not be erased. The Block Erase operation starts
the Program/Erase Controller after a time-out pe-
riod of 50µs after the last Bus Write operation.
Once the Program/Erase Controller starts it is not
possible to select any more blocks. Each addition-
al block must therefore be selected within 50µs of
the last block. The 50µs timer restarts when an ad-
ditional block is selected. After the sixth Bus Write
operation a Bus Read operation within the same
Bank will output the Status Register. See the Sta-
tus Register section for details on how to identify if
the Program/Erase Controller has started the
Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-
changed. No error condition is given when protect-
ed blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command and the Read/Reset command which is
only accepted during the 50µs time-out period.
Typical block erase times are given in Table 7.
After the Erase operation has started all Bus Read
operations to the Bank being erased will output the
Status Register on the Data Inputs/Outputs. See
the section on the Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg-
ister. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
Erase Suspend Command
The Erase Suspend Command may be used to
temporarily suspend a Block Erase operation and
return the memory to Read mode. The command
requires one Bus Write operation.
The Program/Erase Controller will suspend within
the Erase Suspend Latency time of the Erase Sus-
pend Command being issued. Once the Program/
Erase Controller has stopped the memory will be
set to Read mode and the Erase will be suspend-
ed. If the Erase Suspend command is issued dur-
ing the period when the memory is waiting for an
additional block (before the Program/Erase Con-
troller starts) then the Erase is suspended immedi-
ately and will start immediately when the Erase
Resume Command is issued. It is not possible to
select any further blocks to erase after the Erase
Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condition is given. Read-
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac-
cepted.
During Erase Suspend a Bus Read operation to
the Extended Block will output the Extended Block
data.
Erase Resume Command
The Erase Resume command must be used to re-
start the Program/Erase Controller after an Erase
Suspend. The device must be in Read Array mode
before the Resume command will be accepted. An
erase can be suspended and resumed more than
once.
17/51
M29DW323DT, M29DW323DB
Enter Extended Block Command
The M29DW323D has an extra 64KByte block
(Extended Block) that can only be accessed using
the Enter Extended Block command. Three Bus
write cycles are required to issue the Extended
Block command. Once the command has been is-
sued the device enters Extended Block mode
where all Bus Read or Program operations to the
Boot Block addresses access the Extended Block.
The Extended Block (with the same address as
the boot block) cannot be erased, and can be
treated as one-time programmable (OTP) memo-
ry. In Extended Block mode the Boot Blocks are
not accessible. In Extended Block mode dual op-
erations are possible, with the Extended Block
mapped in Bank A. When in Extended Block
mode, Erase Commands in Bank A are not al-
lowed.
To exit from the Extended Block mode the Exit Ex-
tended Block command must be issued.
The Extended Block can be protected, however
once protected the protection cannot be undone.
Exit Extended Block Command
The Exit Extended Block command is used to exit
from the Extended Block mode and return the de-
vice to Read mode. Four Bus Write operations are
required to issue the command.
Block Protect and Chip Unprotect Commands
Groups of blocks can be protected against acci-
dental Program or Erase. The Protection Groups
are shown in APPENDIX A., Tables 23 and 24,
Block Addresses. The whole chip can be unpro-
tected to allow the data inside the blocks to be
changed.
Block Protect and Chip Unprotect operations are
described in APPENDIX D.
Table 5. Commands, 16-bit mode, BYTE = VIH
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the table are in
hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
M29DW323DT, M29DW323DB
Table 6. Commands, 8-bit mode, BYTE = VIL
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Table 7. Program, Erase Times and Program, Erase Endurance Cycles
Note:1. Typical values measured at room temperature and nominal voltages. Sampled, but not 100% tested. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. Maximum value measured at worst case conditions for both temperature and VCC.
19/51
M29DW323DT, M29DW323DB
STATUS REGISTER
The M29DW323D has a Status Register that pro-
vides information on the current or previous Pro-
gram or Erase operations executed in each bank.
The various bits convey information and errors on
the operation. Bus Read operations from any ad-
dress within the Bank, always read the Status
Register during Program and Erase operations. It
is also read during Erase Suspend when an ad-
dress within a block being erased is accessed.
The bits in the Status Register are summarized in
Table 8., Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 7., Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 8., Toggle Flowchart, gives an example of
how to use the Data Toggle Bit. Figures 14 and 15
describe Toggle Bit timing waveform.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
Figures 14 and 15 describe Alternative Toggle Bit
timing waveform.
M29DW323DT, M29DW323DB
Table 8. Status Register Bits
Note: Unspecified data bits should be ignored.
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M29DW323DT, M29DW323DB
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE
The Multiple Bank Architecture of the
M29DW323DT and M29DW323DB gives greater
flexibility for software developers to split the code
and data spaces within the memory array. The
Dual Operations feature simplifies the software
management of the device by allowing code to be
executed from one bank while the other bank is
being programmed or erased.
The Dual Operations feature means that while pro-
gramming or erasing in one bank, read operations
are possible in the other bank with zero latency.
Only one bank at a time is allowed to be in pro-
gram or erase mode.
If a read operation is required in a bank, which is
programming or erasing, the program or erase op-
eration can be suspended.
Also if the suspended operation was erase then a
program command can be issued to another
block, so the device can have one block in Erase
Suspend mode, one programming and other
banks in read mode.
By using a combination of these features, read op-
erations are possible at any moment.
Table 9. and Table 10. show the dual operations
possible in other banks and in the same bank.
Note that only the commonly used commands are
represented in these tables.
Table 9. Dual Operations Allowed In the Other Bank
Note:1. If one bank is involved in a program or erase operation, then the other bank is available for dual operations. Only after an Erase operation in that bank. Only after an Erase Suspend command in that bank.
M29DW323DT, M29DW323DB
Table 10. Dual Operations Allowed In Same Bank
Note:1. Not allowed in the Block or Word that is being erased or programmed. Only after an Erase operation in that bank. Only after an Erase Suspend command in that bank. Read Status Register is not a command. The Status Register can be read during a block program or erase operation. The Status Register can be read by addressing the block being erase suspended.
23/51
M29DW323DT, M29DW323DB
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 11. Absolute Maximum Ratings
Note:1. Compliant with the ECOPACK® 7191395 specification for Lead-free soldering processes. Not exceeding 250°C for more than 30s, and peaking at 260°C. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions. VPP must not remain at 12V for more than a total of 80hrs.
M29DW323DT, M29DW323DB
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 12., Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when rely-
ing on the quoted parameters.
Table 12. Operating and AC Measurement Conditions
Table 13. Device Capacitance
Note: Sampled only, not 100% tested.
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M29DW323DT, M29DW323DB
Table 14. DC Characteristics
Note:1. Sampled only, not 100% tested. In Dual operations the Supply Current will be the sum of ICC1(read) and ICC3 (program/erase).
M29DW323DT, M29DW323DB
