M29DW128F70ZA6F ,128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V Supply, Flash MemoryM29DW128F128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block)3V Supply, Flash MemoryPRELI ..
M29DW128G60ZA6E , 128 Mbit (8 Mb x 16, multiple bank, page, dual boot) 3 V supply Flash memory
M29DW128G60ZA6E , 128 Mbit (8 Mb x 16, multiple bank, page, dual boot) 3 V supply Flash memory
M29DW323DB70N6 ,32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block 3V Supply Flash MemoryAbsolute Maximum Ratings . . . . . . . 23DC and AC PARAMETERS . 24Table 12. Operating an ..
M29DW323DB70N6 ,32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block 3V Supply Flash MemoryFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Packages–V = 2.7V to 3.6V for Program, Erase CC and Rea ..
M29DW323DB-70N6 ,32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block 3V Supply Flash MemoryLogic Diagram . . 5Table 1. Signal Names . . 5Figure 3. TSOP Connections . . . ..
M50427FP , CD PLAYER DIGITAL SIGNAL PROCESSOR
M50427FP , CD PLAYER DIGITAL SIGNAL PROCESSOR
M50436-689SP , SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
M50734SP-10 , 8-BIT CMOS MICROCOMPUTER
M50734SP-10 , 8-BIT CMOS MICROCOMPUTER
M50747-161SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M29DW128F-M29DW128F70NF6-M29DW128F-70NF6-M29DW128F70NF6E-M29DW128F70ZA6-M29DW128F70ZA6F
128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V Supply, Flash Memory
PRELIMINARY DATARev 1.0
August 2005 1/93
M29DW128F128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block)
3V Supply , Flash Memory
Features summary Supply Voltage
–VCC = 2.7V to 3.6V for Program, Erase and
Read
–VCCQ= 1.65V to 3.6V for Input/Output
–VPP =12V for Fast Program (optional) ASYNCHRONOUS RANDOM/PAGE READ Page Width: 8 Words Page Access: 25, 30ns Random Access: 60, 70ns PROGRAMMING TIME 10µs per Byte/Word typical 4 Words / 8 Bytes Program 32-Word Write Buffer ERASE VERIFY MEMORY BLOCKS Quadruple Bank Memory Array:
16Mbit+48Mbit+48Mbit+16Mbit Parameter Blocks (at Top and Bottom) DUAL OPERATIONS While Program or Erase in one bank, Read
in any of the other banks PROGRAM/ ERASE SUSPEND and RESUME
MODES Read from any Block during Program
Suspend Read and Program another Block during
Erase Suspend UNLOCK BYPASS PROGRAM Faster Production/Batch Programming COMMON FLASH INTERFACE 64 bit Security Code 100,000 PROGRAM/ERASE CYCLES per
BLOCK LOW POWER CONSUMPTION Standby and Automatic Standby
M29DW128F2/93
Contents Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.1 Address Inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4 Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8 VPP/ Write Protect (VPP/ WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9 Reset/Block T emporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.10 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.11 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.12 V CCQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.13 VCC Supply Voltage (2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.14 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.1 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.2 Verify Extended Block Protection Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.3 Verify Block Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.4 Hardware Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.5 Temporary Unprotect of High Voltage Protected Blocks . . . . . . . . . . . . . . . . 19
Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M29DW128F
3/93
4.1 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 Temporary Block Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Software Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Standard Protection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Block Lock/Unlock Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.2 Non-Volatile Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Password Protection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.1 Block Lock/Unlock Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.2 Non-Volatile Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.3 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.4 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.5 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.6 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.7 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.8 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1.9 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1.10 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1.11 Verify command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2 Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.1 Write to Buffer and Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2.2 Write to Buffer and Program Confirm command . . . . . . . . . . . . . . . . . . . . . . 34
6.2.3 Write to Buffer and Program Abort and Reset command . . . . . . . . . . . . . . . 34
6.2.4 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2.5 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2.6 Double Byte Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2.7 Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.8 Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.9 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.10 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2.11 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
M29DW128F4/93
6.3 Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.1 Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.2 Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.3 Set Extended Block Protection Bit command . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.4 Verify Extended Block Protection Bit command . . . . . . . . . . . . . . . . . . . . . . 38
6.3.5 Password Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.6 Password Verify command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.7 Password Protection Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.8 Set Password Protection Mode command . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.9 Verify Password Protection Mode command . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.10 Set Standard Protection Mode command . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.11 Verify Standard Protection Mode command . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.12 Set Non-Volatile Modify Protection Bit command . . . . . . . . . . . . . . . . . . . . . 40
6.3.13 Verify Non-Volatile Modify Protection Bit command . . . . . . . . . . . . . . . . . . . 41
6.3.14 Clear Non-Volatile Modify Protection Bits command . . . . . . . . . . . . . . . . . . . 41
6.3.15 Set Lock Bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.16 Clear Lock Bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.17 Verify Lock Bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.18 Set Lock-Down Bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.19 Verify Lock-Down Bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.3 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.4 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.6 Write to Buffer and Program Abort Bit (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . 46
Dual Operations and Multiple Bank architecture . . . . . . . . . . . . . . . . . . . 49 Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
M29DW128F
5/93 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Appendix A Block addresses and Read/Modify Protection groups. . . . . . . . . . 67
Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
C.1 Factory Locked Section of the Extended Block . . . . . . . . . . . . . . . . . . . . . . . 82
C.2 Customer Lockable Section of the Extended Block . . . . . . . . . . . . . . . . . . . . 82
Appendix D High Voltage Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
D.1 Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
D.2 In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Appendix E Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
M29DW128F6/93
List of tables
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Bus Operations, 8-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Read Electronic Signature, 8-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Block Protection, 8-bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Bus Operations, 16-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Read Electronic Signature, 16-bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Block Protection, 16-bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Block Protection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Standard Commands, 8-bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 12. Standard Commands, 16-bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13. Fast Program Commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 14. Fast Program Commands, 16-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 15. Block Protection Commands, 8-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 16. Block Protection Commands, 16-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 17. Protection Command Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 18. Program, Erase Times and Program, Erase Endurance Cycles. . . . . . . . . . . . . . . . . . . . . 44
Table 19. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 20. Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 21. Dual Operations Allowed In Same Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 22. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 23. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 24. Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 25. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 26. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 27. Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 28. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 29. Toggle and Alternative Toggle Bits AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 30. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 31. TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, Package Mechanical Data. . . 64
Table 32. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, Package Mechanical Data . . . . . . 65
Table 33. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 34. Block Addresses and Protection Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 35. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 36. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 37. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 38. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 39. Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 40. Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 41. Extended Block Address and Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 42. Programmer Technique Bus Operations, 8-bit or 16-bit Mode . . . . . . . . . . . . . . . . . . . . . . 85
Table 43. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
M29DW128F
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List of figures
Figure 1. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. TBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Block Protection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 7. Software Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 9. Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 10. AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 12. Random Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 13. Page Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 14. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 15. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 16. Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled. . . . . . . . . . . . . . 61
Figure 17. Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled . . . . . . . . . . . . 61
Figure 18. Reset/Block Temporary Unprotect AC Waveforms (No Program/Erase Ongoing). . . . . . . 62
Figure 19. Reset/Block Temporary Unprotect During Program/Erase Operation AC Waveforms. . . . 62
Figure 20. Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 21. TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, Package Outline . . . . . . . . . . 64
Figure 22. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, Package Outline. . . . . . . . . . . . . . 65
Figure 23. Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 24. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 25. In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 26. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 27. Write to Buffer and Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . 90
1 Summary description M29DW128F
8/93
1 Summary description
The M29DW128F is a 128 Mbit (16Mb x8 or 8Mb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single low voltage (2.7
to 3.6V) supply. VCCQ is an additional voltage supply that allows to drive the I/O pins down to
1.65V. At Power-up the memory defaults to its Read mode.
The M29DW128F features an asymmetrical block architecture, with 16 parameter and 254
main blocks, divided into four Banks, A, B, C and D, providing multiple Bank operations. While
programming or erasing in one bank, read operations are possible in any other bank. The bank
architecture is summarized in Table 2. Eight of the Parameter Blocks are at the top of the
memory address space, and eight are at the bottom.
Program and Erase commands are written to the Command Interface of the memory. An on-
chip Program/Erase Controller simplifies the process of programming or erasing the memory by
taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions identified.
The command set required to control the memory is consistent with JEDEC standards. The
Chip Enable, Output Enable and Write Enable signals control the bus operations of the
memory. They allow simple connection to most microprocessors, often without additional logic.
The device supports Asynchronous Random Read and Page Read from all blocks of the
memory array.
The M29DW128F has one extra 256 Byte block (Extended Block) that can be accessed using a
dedicated command. The Extended Block can be protected and so is useful for storing security
information. However the protection is irreversible, once protected the protection cannot be
undone.
Each block can be erased independently, so it is possible to preserve valid data while old data
is erased.
The device features four different levels of hardware and software block protection to avoid
unwanted program or erase (modify). The software block protection features are available in 16
bit memory organization only: Hardware Protection:
–The VPP/WP provides a hardware protection of the four outermost parameter blocks
(two at the top and two at the bottom of the address space).
–The RP pin temporarily unprotects all the blocks previously protected using a High
Voltage Block Protection technique (see Appendix D: High Voltage Block Protection). Software Protection Standard Protection Password Protection
The memory is offered in TSOP56 (14 x 20mm) and TBGA64 (10 x 13mm, 1mm pitch)
packages. The 8-bit Bus mode is only available when the M29DW128F is delivered in TSOP56
package. In order to meet environmental requirements, ST offers the M29DW128F in
ECOP ACK® packages. ECOP ACK packages are Lead-free. The category of second Level
Interconnect is marked on the package and on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOP ACK specifications are available at:
. The memory is supplied with all the bits erased (set to ’1’).
M29DW128F 1 Summary description
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Table 1. Signal Names
Figure 1. Logic Diagram The x8 organization is only available in TSOP56 Package while the x16 organization is available for both
packages.
1 Summary description M29DW128F
10/93
Table 2. Bank Architecture
Figure 2. TSOP Connections
M29DW128F 1 Summary description
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Figure 3. TBGA Connections (Top view through package)
1 Summary description M29DW128F
12/93
Figure 4. Block Addresses (x8) Also see Appendix A and Table 34 for a full listing of the Block Addresses.
M29DW128F 1 Summary description
13/93
Figure 5. Block Addresses (x16) Also see Appendix A, Table 34 for a full listing of the Block Addresses.
2 Signal descriptions M29DW128F
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2 Signal descriptions
See Figure 1: Logic Diagram, and Table 1: Signal Names, for a brief overview of the signals
connected to this device.
2.1 Address Inputs (A0-A22)
The Address Inputs select the cells in the memory array to access during Bus Read operations.
During Bus Write operations they control the commands sent to the Command Interface of the
Program/Erase Controller.
2.2 Data Inputs/Outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation.
During Bus Write operations they represent the commands sent to the Command Interface of
the internal state machine.
2.3 Data Inputs/Outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high
impedance. During Bus Write operations the Command Register does not use these bits.
When reading the Status Register these bits should be ignored.
2.4 Data Input/Output or Address Input (DQ15A–1)
When the device is in x16 Bus mode, this pin behaves as a Data Input/Output pin (as DQ8-
DQ14). When the device is in x8 Bus mode, this pin behaves as an address pin; DQ15A–1 Low
will select the LSB of the addressed Word, DQ15A–1 High will select the MSB. Throughout the
text consider references to the Data Input/Output to include this pin when the device operates
in x16 bus mode and references to the Address Inputs to include this pin when the device
operates in x8 bus mode except when stated explicitly otherwise.
2.5 Chip Enable (E)
The Chip Enable pin, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, VIH, all other pins are ignored.
2.6 Output Enable (G)
The Output Enable pin, G, controls the Bus Read operation of the memory.
M29DW128F 2 Signal descriptions
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2.7 Write Enable (W)
The Write Enable pin, W, controls the Bus Write operation of the memory’s Command Interface.
2.8 V PP/ Write Protect (VPP /WP)
The VPP /Write Protect pin provides two functions. The VPP function allows the memory to use
an external high voltage power supply to reduce the time required for Program operations. This
is achieved by bypassing the unlock cycles and/or using the multiple Word (2 or 4 at-a-time) or
multiple Byte Program (2, 4 or 8 at-a-time) commands.
The Write Protect function provides a hardware method of protecting the four outermost boot
blocks (two at the top, and two at the bottom of the address space). When VPP /Write Protect is
Low, VIL , the memory protects the four outermost boot blocks; Program and Erase operations in
these blocks are ignored while VPP /Write Protect is Low, even when RP is at VID.
When VPP /Write Protect is High, VIH , the memory reverts to the previous protection status of
the four outermost boot blocks. Program and Erase operations can now modify the data in
these blocks unless the blocks are protected using Block Protection.
Applying VPPH to the VPP /WP pin will temporarily unprotect any block previously protected
(including the four outermost parameter blocks) using a High Voltage Block Protection
technique (In-System or Programmer technique). See Table 9: Hardware Protection for details.
When VPP /Write Protect is raised to VPP the memory automatically enters the Unlock Bypass
mode. When VPP /Write Protect returns to VIH or VIL normal operation resumes. During Unlock
Bypass Program operations the memory draws IPP from the pin to supply the programming
circuits. See the description of the Unlock Bypass command in the Command Interface section.
The transitions from VIH to VPP and from VPP to VIH must be slower than t VHVPP , see Figure20.
Never raise VPP /Write Protect to VPP from any mode except Read mode, otherwise the
memory may be left in an indeterminate state.
The VPP /Write Protect pin must not be left floating or unconnected or the device may become
unreliable. A 0.1µF capacitor should be connected between the VPP /Write Protect pin and the SS Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Unlock Bypass Program, IPP.
2.9 Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all the blocks previously protected using a High Voltage
Block Protection technique (In-System or Programmer technique).
Note that if VPP /WP is at VIL , then the four outermost parameter blocks will remain protected
even if RP is at VID.
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL , for at
least t PLPX . After Reset/Block Temporary Unprotect goes High, VIH , the memory will be ready
for Bus Read and Bus Write operations after t PHEL or t RHEL , whichever occurs last. See the
Ready/Busy Output section, Table 30: Reset/Block Temporary Unprotect AC Characteristics
and Figure 18 and Figure 19 for more details.
2 Signal descriptions M29DW128F
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Holding RP at VID will temporarily unprotect all the blocks previously protected using a High
Voltage Block Protection technique. Program and erase operations on all blocks will be
possible. The transition from VIH to VID must be slower than tPHPHH.
2.10 Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or erase operation. During Program or erase operations Ready/Busy is
Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase
Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high-impedance. See Table 30: Reset/Block Temporary Unprotect AC Characteristics
and Figure 18 and Figure 19.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.11 Byte/Word Organization Select (BYTE)
It is used to switch between the x8 and x16 Bus modes of the memory when the M29DW128F
is delivered in TSOP56 package. When Byte/Word Organization Select is Low, VIL, the memory
is in x8 mode, when it is High, VIH, the memory is in x16 mode.
2.12 V CCQ Supply VoltageCCQ provides the power supply to the I/O and control pins and enables all Outputs to be
powered independently from VCC. VCCQ can be tied to VCC or can use a separate supply.
2.13 VCC Supply Voltage (2.7V to 3.6V)
VCC provides the power supply for all operations (Read, Program and Erase).
The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout
Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during
power up, power down and power surges. If the Program/Erase Controller is programming or
erasing during this time then the operation aborts and the memory contents being altered will
be invalid.
A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS
Ground pin to decouple the current surges from the power supply. The PCB track widths must
be sufficient to carry the currents required during Program and erase operations, ICC2.
2.14 VSS GroundSS is the reference for all voltage measurements. The device features two VSS pins both of
which must be connected to the system ground.
M29DW128F 3 Bus operations
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3 Bus operations
There are five standard bus operations that control the device. These are Bus Read (Random
and Page modes), Bus Write, Output Disable, Standby and Automatic Standby.
Dual operations are possible in the M29DW128F, thanks to its multiple bank architecture. While
programming or erasing in one banks, read operations are possible in any of the other banks.
Write operations are only allowed in one bank at a time.
See Table 3 and Table 6, Bus Operations, for a summary. Typically glitches of less than 5ns on
Chip Enable, Write Enable, and Reset/Block Temporary Unprotect pins are ignored by the
memory and do not affect bus operations.
3.1 Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. To speed up the read operation the memory array can be read in Page mode where
data is internally read and stored in a page buffer. The Page has a size of 8 Words and is
addressed by the address inputs A0-A2.
A valid Bus Read operation involves setting the desired address on the Address Inputs,
applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High,
VIH. The Data Inputs/Outputs will output the value, see Figure 12: Random Read AC
Waveforms, Figure 13: Page Read AC Waveforms, and Table 26: Read AC Characteristics, for
details of when the output becomes valid.
3.2 Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip
Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during
the whole Bus Write operation. See Figure 14 and Figure 15, Write AC Waveforms, and
Table 27 and Table 28, Write AC Characteristics, for details of the timing requirements.
3.3 Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4 Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs
pins are placed in the high-impedance state. To reduce the Supply Current to the Standby
Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current
level see Table 25: DC Characteristics. During program or erase operations the memory will
continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until
the operation completes.
3 Bus operations M29DW128F
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3.5 Automatic Standby
If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or more
the memory enters Automatic Standby where the internal Supply Current is reduced to the
Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read
operation is in progress.
3.6 Special Bus Operations
Additional bus operations can be performed to read the Electronic Signature, verify the
Protection Status of the Extended Memory Block (second section), and apply and remove
Block Protection. These bus operations are intended for use by programming equipment and
are not usually used in applications. They require VID to be applied to some pins.
3.6.1 Read Electronic Signature
The memory has two codes, the Manufacturer code and the Device code used to identify the
memory. These codes can accessed by performing read operations with control signals and
addresses set as shown in Table 4 and Table6.
These codes can also be accessed by issuing an Auto Select command (see Auto Select
command in Section 6: Command Interface).
3.6.2 Verify Extended Block Protection Indicator
The Extended Block is divided in two sections of which one is Factory Locked and the second
one is either Customer Lockable or Customer Locked.
The Protection Status of the second section of the Extended Block (Customer Lockable or
Customer Locked) can be accessed by reading the Extended Block Protection Indicator. This is
performed by applying the signals as shown in Table 5 and Table 8. The Protection Status of
the Extended Block is then output on bits DQ7 and DQ6 of the Data Input/Outputs. (see Table3
and Table 6, Bus Operations).
The Protection Status of the Extended Block can also be accessed by issuing an Auto Select
command (see Auto Select command in Section 6: Command Interface).
3.6.3 Verify Block Protection Status
The Protection Status of a Block can be directly accessed by performing a read operation with
control signals and addresses set as shown in Table 5 and Table8.
If the Block is protected, then 01h (in x8 mode) is output on Data Input/Outputs DQ0-DQ7,
otherwise 00h is output.
3.6.4 Hardware Block Protect
The VPP/WP pin can be used to protect the four outermost parameter blocks. When VPP/WP is
at VIL the four outermost parameter blocks are protected and remain protected regardless of
the Block Protection Status or the Reset/Block Temporary Unprotect pin state.
M29DW128F 3 Bus operations
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3.6.5 Temporary Unprotect of High Voltage Protected Blocks
The RP pin can be used to temporarily unprotect all the blocks previously protected using the
In-System or the Programmer protection technique (High Voltage techniques).
Refer to Reset/Block Temporary Unprotect (RP) in Section 2: Signal descriptions.
Table 3. Bus Operations, 8-bit Mode
Table 4. Read Electronic Signature, 8-bit Mode X = VIL or VIH. X = VIL or VIH.
3 Bus operations M29DW128F
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Table 5. Block Protection, 8-bit Mode
Table 6. Bus Operations, 16-bit Mode
Table 7. Read Electronic Signature, 16-bit Mode X = VIL or VIH. BKA Bank Address, BA any Address in the Block. This indicates the protection status of the second section of the Extended Block; the first section of the Extended Block
being always Factory Locked. The RP pin unprotects all the blocks that have been previously protected using a High Voltage protection Technique. X = VIL or VIH. X = VIL or VIH.
M29DW128F 3 Bus operations
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Table 8. Block Protection, 16-bit Mode X = VIL or VIH. BKA Bank Address, BA Any Address in the Block. This indicates the protection status of the second section of the Extended Block; the first section of the Extended Block
being always Factory Locked. The RP pin unprotects all the blocks that have been previously protected using a High Voltage protection Technique.
4 Hardware Protection M29DW128F
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4 Hardware Protection
The M29DW128F features hardware protection/unprotection. Refer to Table 9 for details on
hardware block protection/unprotection using VPP/WP and RP pins.
4.1 Write Protect
The VPP/WP pin protects the four outermost parameter blocks (refer to Section 2: Signal
descriptions for a detailed description of the signals).
4.2 Temporary Block Unprotect
When held at VID, the Reset/Block Temporary Unprotect pin, RP , will temporarily unprotect all
the blocks previously protected using a High Voltage Block Protection technique.
Table 9. Hardware Protection The temporary unprotection is valid only for the blocks that have been protected using the High Voltage
Protection Technique (see Appendix D: High Voltage Block Protection). The blocks protected using a software
protection method (Standard, Password) do not follow this rules.
M29DW128F 5 Software Protection
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5 Software Protection
The M29DW128F has two different Software Protection modes: the Standard Protection mode
and the Password Protection mode.
On first use all parts default to the Standard Protection mode and the customer is free to
activate the Standard or the Password Protection mode.
The desired protection mode is activated by setting one of two one-time programmable bits, the
Standard Protection Mode Lock bit or the Password Protection Mode Lock bit. Programming
the Standard and the Password Protection Mode Lock bit to ‘1’ will permanently activate the
Standard Protection mode and the Password Protection mode, respectively. These two bits are
one-time programmable and non-volatile, once the Protection mode has been programmed, it
cannot be changed and the device will permanently operate in the selected Protection mode. It
is recommended to activate the desired Software Protection mode when first programming the
device.
The device is shipped with all blocks unprotected. The Block Protection Status can be read by
issuing the Auto Select command (see Table 10: Block Protection Status).
The Standard and Password Protection modes offer two levels of protection, a Block Lock/
Unlock protection and a Non-Volatile protection.
For the four outermost parameter blocks, an even higher level of block protection can be
achieved by locking the blocks using the Non-Volatile Protection and then by holding the VPP/
WP pin Low.
5.1 Standard Protection Mode
5.1.1 Block Lock/Unlock Protection
It is a flexible mechanism to protect/unprotect a block or a group of blocks from program or
erase operations.
A volatile Lock bit is assigned to each block or group of blocks. When the lock bit is set to ‘1’ the
associated block or group of blocks is protected from program/erase operations, when the Lock
bit is set to ‘0’ the associated block or group of blocks is unprotected and can be programmed
or erased.
The Lock bits can be set (‘1’) and cleared (‘0’) individually as often as required by issuing a Set
Lock Bit command and Clear Lock bit command, respectively.
After a Power-up or Hardware Reset, all the Lock bits are cleared to ‘0’ (block unlocked).
5.1.2 Non-V olatile Protection
A Non-Volatile Modify Protection bit is assigned to each block or group of blocks.
When a Non-Volatile Modify Protection bit is set to ‘1’ the associated block or group of blocks is
protected, preventing any program or erase operations in this block or group of blocks.
The Non-Volatile Modify Protection bits are set individually by issuing a Set Non-Volatile Modify
Protection Bit command. They are non-volatile and will remain set through a hardware reset or
a power-down/power-up sequence.
5 Software Protection M29DW128F
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The Non-Volatile Modify Protection bits cannot be cleared individually, they can only be cleared
all at the same time by issuing a Clear Non-Volatile Modify Protection Bits command.
However if any one of the Non-Volatile Modify Protection bits has to be cleared, care should be
taken to preprogram to ‘1’ all the Non-Volatile Modify Protection Bits prior to issuing the Clear
Non-Volatile Modify Protection bits in order to prevent the over-erasure of previously cleared
Non Volatile Modify Protection bits. It is crucial to prevent over-erasure because the process
may lead to permanent damage to the Non-Volatile Modify Protection Bits and the device does
not have any built-in means of preventing over-erasure.
The device features a volatile Lock-Down bit which can be used to prevent changing the state
of the Non-Volatile Modify Protection bits. When set to ‘1’, the Non-Volatile Modify Protection
bits can no longer be modified; when set to ‘0’, the Non-Volatile Modify Protection bits can be
set and reset using the Set Non-Volatile Modify Protection Bit command and the Clear Non-
Volatile Modify Protection Bits command, respectively.
The Lock-Down bit is set by issuing the Set Lock-Down Bit Command. It is not cleared using a
command, but through a hardware reset or a power-down/power-up sequence.
The parts are shipped with the Non-Volatile Modify Protection bits set to ‘0’.
Locked blocks and Non-Volatile Locked blocks can co-exist in the same memory array.
Refer to Table 10: Block Protection Status and Figure 7: Software Protection Scheme for details
on the block protection mechanism.
5.2 Password Protection Mode
The Password Protection mode provides a more advanced level of software protection than the
Standard Protection mode.
Prior to entering the Password Protection mode, it is necessary to set a password and to verify
it (see Password Program command and Password Verify command). The Password Protection
mode is then activated by programming the Password Protection Mode Lock bit to ‘1’. The
Reset/Block Temporary Unprotect pin, RP , can be at VID or at VIH.
This operation is not reversible and once the bit is programmed the device will permanently
remain in the Password Protection mode.
The Password Protection mode uses the same protection mechanisms as the Standard
Protection mode (Block Lock/Unlock, Non-Volatile Protection).
5.2.1 Block Lock/Unlock Protection
The Block Lock/Unlock Protection operates exactly in the same way as in the Standard
Protection mode.
5.2.2 Non-V olatile Protection
The Non-Volatile Protection is more advanced in the Password Protection mode.
In this mode, the Lock-Down bit cannot be cleared through a hardware reset or a power-down/
power-up sequence.
The Lock-Down bit is cleared by issuing the Password Protection Unlock command along with
the correct password.
M29DW128F 5 Software Protection
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Once the correct Password has been provided, the Lock-Down bit is cleared and the Non-
Volatile Modify Protection bits can be set or reset using the appropriate commands (the Set
Non-Volatile Modify Protection Bit command or the Clear Non-Volatile Modify Protection Bits
command, respectively).
If the Password provided is not correct, the Lock-Down bit remains locked and the state of the
Non-Volatile Modify Protection bits cannot be modified.
The Password is a 64-bit code located in the memory space. It must be programmed by the
user prior to selecting the Password Protection mode. The Password is programmed by issuing
a Password Program command and checked by issuing a Password Verify command. The
Password should be unique for each part.
Once the device is in Password Protection mode, the Password can no longer be read or
retrieved. Moreover, all commands to the address where the password is stored, are disabled.
Refer to Table 10: Block Protection Status and Figure 7: Software Protection Scheme for details
on the block protection scheme.
Table 10. Block Protection Status
Figure 6. Block Protection State Diagram The Lock bit can always be modified by issuing a Clear Lock Bit command or by taking the device through a Power-up or
Hardware Reset.
5 Software Protection M29DW128F
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Figure 7. Software Protection Scheme
M29DW128F 6 Command Interface
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6 Command Interface
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of
Bus Write operations will result in the memory returning to Read mode. The long command
sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-bit or
8-bit mode.
6.1 Standard commands
See either Table 12, or Table 11, depending on the configuration that is being used, for a
summary of the Standard commands.
6.1.1 Read/Reset command
The Read/Reset command returns the memory to Read mode. It also resets the errors in the
Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset
command.
The Read/Reset command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to Read mode. If the Read/Reset command is
issued during the time-out of a Block erase operation, the memory will take up to 10µs to abort.
During the abort period no valid data can be read from the memory.
The Read/Reset command will not abort an Erase operation when issued while in Erase
Suspend.
6.1.2 Auto Select command
The Auto Select command is used to read the Manufacturer Code, the Device Code, the
Protection Status of each block (Block Protection Status) and the Extended Block Protection
Indicator. It can be addressed to either Bank.
Three consecutive Bus Write operations are required to issue the Auto Select command. Once
the Auto Select command is issued Bus Read operations to specific addresses output the
Manufacturer Code, the Device Code, the Extended Block Protection Indicator and a Block
Protection Status (see Table 11 and Table 12 in conjunction with Table 4, Table 5, Table 7 and
Table 8). The memory remains in Auto Select mode until a Read/Reset or CFI Query command
is issued.
6.1.3 Read CFI Query command
The Read CFI Query Command is used to put the addressed bank in Read CFI Query mode.
Once in Read CFI Query mode Bus Read operations to the same bank will output data from the
Common Flash Interface (CFI) Memory Area. If the read operations are to a different bank from
the one specified in the command then the read operations will output the contents of the
memory array and not the CFI data.
One Bus Write cycle is required to issue the Read CFI Query Command. Care must be taken to
issue the command to one of the banks (A22-A19) along with the address shown in Table 3 and
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Table 6. Once the command is issued subsequent Bus Read operations in the same bank
(A22-A19) to the addresses shown in Appendix B: Common Flash Interface (CFI) (A7-A0), will
read from the Common Flash Interface Memory Area.
This command is valid only when the device is in the Read Array or Auto Select mode. To enter
Read CFI query mode from Auto Select mode, the Read CFI Query command must be issued
to the same bank address as the Auto Select command, otherwise the device will not enter
Read CFI Query mode.
The Read/Reset command must be issued to return the device to the previous mode (the Read
Array mode or Auto Select mode). A second Read/Reset command is required to put the
device in Read Array mode from Auto Select mode.
See Appendix B, Table 35, Table 36, Table 37, Table 38, Table 39 and Table 40 for details on
the information contained in the Common Flash Interface (CFI) memory area.
6.1.4 Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are
required to issue the Chip Erase Command and start the Program/Erase Controller.
If any blocks are protected, then these are ignored and all the other blocks are erased. If all of
the blocks are protected the Chip Erase operation appears to start but will terminate within
about 100µs, leaving the data unchanged. No error condition is given when protected blocks
are ignored.
During the erase operation the memory will ignore all commands, including the Erase Suspend
command. It is not possible to issue any command to abort the operation. Typical chip erase
times are given in Table 18. All Bus Read operations during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs. See the section on the Status Register for
more details.
After the Chip Erase operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs the memory will continue to output the Status
Register. A Read/Reset command must be issued to reset the error condition and return to
Read mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
6.1.5 Block Erase command
The Block Erase command can be used to erase a list of one or more blocks in one or more
Banks. It sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the
selected blocks is lost.
Six Bus Write operations are required to select the first block in the list. Each additional block in
the list can be selected by repeating the sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts the Program/Erase Controller after a time-
out period of 50µs after the last Bus Write operation. Once the Program/Erase Controller starts
it is not possible to select any more blocks. Each additional block must therefore be selected
within 50µs of the last block. The 50µs timer restarts when an additional block is selected. After
the sixth Bus Write operation a Bus Read operation within the same Bank will output the Status
Register. See the Status Register section for details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
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If any selected blocks are protected then these are ignored and all the other selected blocks are
erased. If all of the selected blocks are protected the Block Erase operation appears to start but
will terminate within about 100µs, leaving the data unchanged. No error condition is given when
protected blocks are ignored.
During the Block Erase operation the memory will ignore all commands except the Erase
Suspend command and the Read/Reset command which is only accepted during the 50µs
time-out period. T ypical block erase times are given in Table 18.
After the Erase operation has started all Bus Read operations to the Banks being erased will
output the Status Register on the Data Inputs/Outputs. See the section on the Status Register
for more details.
After the Block Erase operation has completed the memory will return to the Read mode,
unless an error has occurred.
When an error occurs, Bus Read operations to the Banks where the command was issued will
continue to output the Status Register. A Read/Reset command must be issued to reset the
error condition and return to Read mode.
6.1.6 Erase Suspend command
The Erase Suspend command may be used to temporarily suspend a Block or multiple Block
Erase operation. One Bus Write operation specifying the Bank Address of one of the Blocks
being erased is required to issue the command. Issuing the Erase Suspend command returns
the whole device to Read mode.
The Program/Erase Controller will suspend within the Erase Suspend Latency time (see
Table 18 for value) of the Erase Suspend Command being issued. Once the Program/Erase
Controller has stopped the memory will be set to Read mode and the Erase will be suspended.
If the Erase Suspend command is issued during the period when the memory is waiting for an
additional block (before the Program/Erase Controller starts) then the Erase is suspended
immediately and will start immediately when the Erase Resume Command is issued. It is not
possible to select any further blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. If any attempt is
made to program in a protected block or in the suspended block then the Program command is
ignored and the data remains unchanged. The Status Register is not read and no error
condition is given. Reading from blocks that are being erased will output the Status Register.
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an Erase Suspend. The Read/Reset command must be issued to return the device to
Read Array mode before the Resume command will be accepted.
During Erase Suspend a Bus Read operation to the Extended Block will output the Extended
Block data. Once in the Extended Block mode, the Exit Extended Block command must be
issued before the erase operation can be resumed.
6.1.7 Erase Resume command
The Erase Resume command is used to restart the Program/Erase Controller after an Erase
Suspend. The command must include the Bank Address of the Erase-Suspended Bank,
otherwise the Program/Erase Controller is not restarted.
The device must be in Read Array mode before the Resume command will be accepted. An
Erase can be suspended and resumed more than once.
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6.1.8 Program Suspend command
The Program Suspend command allows the system to interrupt a program operation so that
data can be read from any block. When the Program Suspend command is issued during a
program operation, the device suspends the program operation within the Program Suspend
Latency time (see Table 18 for value) and updates the Status Register bits. The Bank
Addresses of the Block being programmed must be specified in the Program Suspend
command.
After the program operation has been suspended, the system can read array data from any
address. However, data read from Program-Suspended addresses is not valid.
The Program Suspend command may also be issued during a program operation while an
erase is suspended. In this case, data may be read from any addresses not in Erase Suspend
or Program Suspend. If a read is needed from the Extended Block area (One-time Program
area), the user must use the proper command sequences to enter and exit this region.
The system may also issue the Auto Select command sequence when the device is in the
Program Suspend mode. The system can read as many Auto Select codes as required. When
the device exits the Auto Select mode, the device reverts to the Program Suspend mode, and is
ready for another valid operation. See Auto Select command sequence for more information.
6.1.9 Program Resume command
After the Program Resume command is issued, the device reverts to programming. The
controller can determine the status of the program operation using the DQ7 or DQ6 status bits,
just as in the standard program operation. See Write Operation Status for more information.
The system must write the Program Resume command, specifying the Bank addresses of the
Program-Suspended Block, to exit the Program Suspend mode and to continue the
programming operation.
Further issuing of the Resume command is ignored. Another Program Suspend command can
be written after the device has resumed programming.
6.1.10 Program command
The Program command can be used to program a value to one address in the memory array at
a time. The command requires four Bus Write operations, the final Write operation latches the
address and data in the internal state machine and starts the Program/Erase Controller.
Programming can be suspended and then resumed by issuing a Program Suspend command
and a Program Resume command, respectively (see Program Suspend command and
Program Resume command paragraphs).
If the address falls in a protected block then the Program command is ignored, the data remains
unchanged. The Status Register is never read and no error condition is given.
After programming has started, Bus Read operations in the Bank being programmed output the
Status Register content, while Bus Read operations to the other Bank output the contents of
the memory array. See the section on the Status Register for more details. Typical program
times are given in Table18.
After the program operation has completed the memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus Read operations to the Bank where the
command was issued will continue to output the Status Register. A Read/Reset command must
be issued to reset the error condition and return to Read mode.
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One of the Erase Commands must be used to set all the bits in a block or in the whole memory
from ’0’ to ’1’.
6.1.11 Verify command
The Verify command is used to check if a block is blank or in other words, if it has been
successfully erased and all its bits set to ’1’. It reads the value of the Error Bit DQ5. If the Error
Bit is set to ’1’, it indicates that the operation failed.
Three cycles are required to issue a Verify command: The command starts with two unlock cycles.
2. The third Bus Write cycle sets up the Verify command code along with the address of the
block to be checked.
Table 11. Standard Commands, 8-bit Mode Grey cells represent Read cycles. The other cells are Write cycles. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the
table are in hexadecimal. The Auto Select addresses and data are given in Table 4: Read Electronic Signature, 8-bit Mode, and Table 5: Block
Protection, 8-bit Mode, except for A9 that is ‘Don’t Care’.
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Table 12. Standard Commands, 16-bit Mode
6.2 Fast Program commands
The M29DW128F offers a set of Fast Program commands to improve the programming
throughput: Write to Buffer and Program Double and Quadruple Word, Program Double, Quadruple and Octuple Byte Program Unlock Bypass.
See either Table 14, or Table 13, depending on the configuration that is being used, for a
summary of the Fast Program commands.
When VPPH is applied to the VPP/Write Protect pin the memory automatically enters the Fast
Program mode. The user can then choose to issue any of the Fast Program commands. Care
must be taken because applying a VPPH to the VPP/WP pin will temporarily unprotect any
protected block.
Only one bank can be programmed at any one time. The other bank must be in Read mode or
Erase Suspend. Grey cells represent Read cycles. The other cells are Write cycles. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the
table are in hexadecimal. The Auto Select addresses and data are given in Table 7: Read Electronic Signature, 16-bit Mode, and Table 8: Block
Protection, 16-bit Mode, except for A9 that is ‘Don’t Care’.
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After programming has started, Bus Read operations in the Bank being programmed output the
Status Register content, while Bus Read operations to the other Bank output the contents of
the memory array. Fast program commands can be suspended and then resumed by issuing a
Program Suspend command and a Program Resume command, respectively (see Program
Suspend command and Program Resume command paragraphs.)
After the fast program operation has completed, the memory will return to the Read mode,
unless an error has occurred. When an error occurs Bus Read operations to the Bank where
the command was issued will continue to output the Status Register. A Read/Reset command
must be issued to reset the error condition and return to Read mode. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
Typical Program times are given in Table 18: Program, Erase Times and Program, Erase
Endurance Cycles.
6.2.1 Write to Buffer and Program command
The Write to Buffer and Program Command makes use of the device’s 64-Byte Write Buffer to
speed up programming. 32 Words/64 Bytes can be loaded into the Write Buffer. Each Write
Buffer has the same A5-A22 addresses.The Write to Buffer and Program command
dramatically reduces system programming time compared to the standard non-buffered
Program command.
When issuing a Write to Buffer and Program command, the VPP/WP pin can be either held
High, VIH or raised to VPPH.
See Table 18 for details on typical Write to Buffer and Program times in both cases.
Five successive steps are required to issue the Write to Buffer and Program command: The Write to Buffer and Program command starts with two unlock cycles.
2. The third Bus Write cycle sets up the Write to Buffer and Program command. The setup
code can be addressed to any location within the targeted block.
3. The fourth Bus Write cycle sets up the number of Words to be programmed. Value n is
written to the same block address, where n+1 is the number of Words to be programmed.
n+1 must not exceed the size of the Write Buffer or the operation will abort.
4. The fifth cycle loads the first address and data to be programmed.
5. Use n Bus Write cycles to load the address and data for each Word into the Write Buffer.
Addresses must lie within the range from the start address+1 to the start address + n-1.
Optimum performance is obtained when the start address corresponds to a 64 Byte
boundary. If the start address is not aligned to a 64 Byte boundary, the total programming
time is doubled.
All the addresses used in the Write to Buffer and Program operation must lie within the same
page.
To program the content of the Write Buffer, this command must be followed by a Write to Buffer
and Program Confirm command.
If an address is written several times during a Write to Buffer and Program operation, the
address/data counter will be decremented at each data load operation and the data will be
programmed to the last word loaded into the Buffer.
Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will
abort the Write to Buffer and Program.
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The Status Register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status during
a Write to Buffer and Program operation.
If is not possible to detect Program operation fails when changing programmed data from ‘0’ to
‘1’, that is when reprogramming data in a portion of memory already programmed. The
resulting data will be the logical OR between the previous value and the current value.
A Write to Buffer and Program Abort and Reset command must be issued to abort the Write to
Buffer and Program operation and reset the device in Read mode.
During Write to Buffer and Program operations, the bank being programmed will accept
Program/Erase Suspend commands.
See Appendix E, Figure 27: Write to Buffer and Program Flowchart and Pseudo Code, for a
suggested flowchart on using the Write to Buffer and Program command.
6.2.2 Write to Buffer and Program Confirm command
The Write to Buffer and Program Confirm command is used to confirm a Write to Buffer and
Program command and to program the n+1 Words loaded in the Write Buffer by this command.
6.2.3 Write to Buffer and Program Abort and Reset command
The Write to Buffer and Program Abort and Reset command is used to abort Write to Buffer
and Program command.
6.2.4 Double Word Program command
This is used to write two adjacent Words in x16 mode, simultaneously. The addresses of the
two Words must differ only in A0.
Three bus write cycles are necessary to issue the command: The first bus cycle sets up the command.
2. The second bus cycle latches the Address and the Data of the first Word to be written.
3. The third bus cycle latches the Address and the Data of the second Word to be written and
starts the Program/Erase Controller.
6.2.5 Quadruple Word Program command
This is used to write a page of four adjacent Words, in x16 mode, simultaneously. The
addresses of the four Words must differ only in A1 and A0.
Five bus write cycles are necessary to issue the command: The first bus cycle sets up the command.
2. The second bus cycle latches the Address and the Data of the first Word to be written.
3. The third bus cycle latches the Address and the Data of the second Word to be written.
4. The fourth bus cycle latches the Address and the Data of the third Word to be written.
5. The fifth bus cycle latches the Address and the Data of the fourth Word to be written and
starts the Program/Erase Controller.
6.2.6 Double Byte Program Command
This is used to write two adjacent Bytes in x8 mode, simultaneously. The addresses of the two
Bytes must differ only in DQ15A-1.
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Three bus write cycles are necessary to issue the command: The first bus cycle sets up the command.
2. The second bus cycle latches the Address and the Data of the first Byte to be written.
3. The third bus cycle latches the Address and the Data of the second Byte to be written and
starts the Program/Erase Controller.
6.2.7 Quadruple Byte Program command
This is used to write four adjacent Bytes in x8 mode, simultaneously. The addresses of the four
Bytes must differ only in A0, DQ15A-1.
Five bus write cycles are necessary to issue the command. The first bus cycle sets up the command.
2. The second bus cycle latches the Address and the Data of the first Byte to be written.
3. The third bus cycle latches the Address and the Data of the second Byte to be written.
4. The fourth bus cycle latches the Address and the Data of the third Byte to be written.
5. The fifth bus cycle latches the Address and the Data of the fourth Byte to be written and
starts the Program/Erase Controller.
6.2.8 Octuple Byte Program command
This is used to write eight adjacent Bytes, in x8 mode, simultaneously. The addresses of the
eight Bytes must differ only in A1, A0 and DQ15A-1.
Nine bus write cycles are necessary to issue the command: The first bus cycle sets up the command.
2. The second bus cycle latches the Address and the Data of the first Byte to be written.
3. The third bus cycle latches the Address and the Data of the second Byte to be written.
4. The fourth bus cycle latches the Address and the Data of the third Byte to be written.
5. The fifth bus cycle latches the Address and the Data of the fourth Byte to be written.
6. The sixth bus cycle latches the Address and the Data of the fifth Byte to be written.
7. The seventh bus cycle latches the Address and the Data of the sixth Byte to be written.
8. The eighth bus cycle latches the Address and the Data of the seventh Byte to be written.
9. The ninth bus cycle latches the Address and the Data of the eighth Byte to be written and
starts the Program/Erase Controller.
6.2.9 Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory faster than with the standard program commands. When the
cycle time to the device is long, considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the bank enters Unlock Bypass mode.
When in Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset
commands are valid. The Unlock Bypass Program command can then be issued to program
addresses within the bank, or the Unlock Bypass Reset command can be issued to return the
bank to Read mode. In Unlock Bypass mode the memory can be read as if in Read mode.
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6.2.10 Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in the memory
array at a time. The command requires two Bus Write operations, the final write operation
latches the address and data and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass Program command behaves identically to the
Program operation using the Program command. The operation cannot be aborted, a Bus
Read operation to the Bank where the command was issued outputs the Status Register. See
the Program command for details on the behavior.
6.2.11 Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock
Bypass mode. Two Bus Write operations are required to issue the Unlock Bypass Reset
command. Read/Reset command does not exit from Unlock Bypass mode.
Table 13. Fast Program Commands, 8-bit mode X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address, WBL Write Buffer Location. All
values in the table are in hexadecimal. The maximum number of cycles in the command sequence is 37. N+1 is the number of Words to be programmed during the Write to Buffer
and Program operation. Each buffer has the same A5-A22 addresses. A0-A4 are used to select a Word within the N+1 Word page. The 6th cycle has to be issued N time. WBL scans the Word inside the page. BA must be identical to the address loaded during the Write to buffer and Program 3rd and 4th cycles.
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Table 14. Fast Program Commands, 16-bit Mode
6.3 Block Protection commands
Blocks or groups of blocks can be protected against accidental program, erase or read
operations. The Protection Groups are shown in Appendix A, Table 34: Block Addresses and
Protection Groups. The device block protection scheme is shown in Figure 7: Software
Protection Scheme and Figure 6: Block Protection State Diagram. See either Table 15, or
Table 16, depending on the configuration that is being used, for a summary of the Block
Protection commands.
Only the commands related to the Extended Block Protection are available in both 8 bit and 16
bit memory configuration. The other block protection commands are available in 16-bit
configuration only.
6.3.1 Enter Extended Block command
The M29DW128F has one extra 256-Byte block (Extended Block) that can only be accessed
using the Enter Extended Block command.
Three Bus Write cycles are required to issue the Extended Block command. Once the
command has been issued the device enters the Extended Block mode where all Bus Read or
Program operations are conducted on the Extended Block. Once the device is in the Extended
Block mode, the Extended Block is addressed by using the addresses occupied by the boot
blocks in the other operating modes (see Table 34: Block Addresses and Protection Groups).
The device remains in Extended Block mode until the Exit Extended Block command is issued
or power is removed from the device. After power-up or a hardware reset, the device reverts to X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address, WBL Write
Buffer Location. All values in the table are in hexadecimal. The maximum number of cycles in the command sequence is 37. N+1 is the number of Words to be programmed during
the Write to Buffer and Program operation. Each buffer has the same A5-A22 addresses. A0-A4 are used to select a Word within the N+1 Word page. The 6th cycle has to be issued N time. WBL scans the Word inside the page. BA must be identical to the address loaded during the Write to buffer and Program 3rd and 4th cycles.
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the Read mode where commands issued to the Boot Block Address space will address the
Boot Blocks.
Note that when the device is in the Extended Block mode, the VPP/WP pin cannot be used for
fast programming and the Unlock Bypass mode is not available.
The Extended Block cannot be erased, and can be treated as one-time programmable (OTP)
memory. In Extended Block mode only array cell locations (Bank A) with the same addresses
as the Extended Block are not accessible. In Extended Block mode dual operations are allowed
and the Extended Block physically belongs to Bank A.
In Extended Block mode, Erase, Chip Erase, Erase Suspend and Erase resume commands are
not allowed.
To exit from the Extended Block mode the Exit Extended Block command must be issued.
The Extended Block can be protected by setting the Extended Block Protection Bit to ‘1’;
however once protected the protection cannot be undone.
6.3.2 Exit Extended Block command
The Exit Extended Block command is used to exit from the Extended Block mode and return
the device to Read mode. Four Bus Write operations are required to issue the command.
6.3.3 Set Extended Block Protection Bit command
The Set Extended Block Protection Bit command programs the Extended Block Protection bit to
‘1’ thus preventing the second section of the Extended Block from being programmed.
A Read/Reset command must be issued to abort a Set Extended Block Protection Bit
command.
Six successive steps are required to issue the Set Extended Block Protection Bit command. The command starts with two unlock cycles.
2. The third Bus Write cycle sets up the Set Extended Block Protection Bit command.
3. The fourth Bus Write Cycle programs the Extended Block Protection bit to ‘1’.
4. The last two cycles verify the value programmed at the Extended Block Protection bit
address: if bit DQ0 of Data Inputs/Outputs is set to ’1’, it indicates that the Extended Block
Protection bit has been successfully programmed. If DQ0 is ‘0’, the Set Extended Block
Protection Bit command must be issued and verified again.
6.3.4 Verify Extended Block Protection Bit command
The Verify Extended Block Protection Bit command reads the status of the Extended Block
Protection bit on bit DQ0 of the Data Inputs/Outputs. If DQ0 is ‘1’, the second section of the
Extended Block is protected from program operations.
6.3.5 Password Program command
The Password Program Command is used to program the 64-bit Password used in Password
Protection mode.
Four cycles are required to program the Password: The first two cycles are unlock cycles.
2. The third cycle issues the Password Program command.
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3. The fourth cycle inputs the 16-bit data required to program the Password.
To program the 64-bit Password, the complete command sequence must be entered four times
at four consecutive addresses selected by A1 to A0.
Read operations can be used to read the Status Register during a Password Program
operation. All other operations are forbidden.
The Password can be checked by issuing a Password Verify command.
Once Password Program operation has completed, a Read/ Reset command must be issued to
return the device to Read mode. The Password Protection mode can then be selected.
By default, all Password bits are set to ‘1’.
6.3.6 Password Verify command
The Password Verify Command is used to verify the Password used in Password Protection
mode. T o verify the 64-bit Password, the complete command sequence must be entered four
times at four consecutive addresses selected by A1 to A0. If the Password Mode Locking Bit is
programmed and the user attempts to verify the Password, the device will output all F’s onto the
I/O data bus. The Password is output regardless of the bank address.
The user must issue a Read/reset command to return the device to Read mode.
Dual operations are not allowed during a Password Verify operation.
6.3.7 Password Protection Unlock command
The Password Protection Unlock command is used to clear the Lock-Down bit in order to
unprotect all Non-Volatile Modify Protection bits when the device is in Password Protection
mode. The Password Protection Unlock command must be issued along with the correct
Password.
The complete command sequence must be entered for each 16 bits of the Password.
There must be a 2µs delay between successive Password Protection Unlock commands in
order to prevent hackers from cracking the Password by trying all possible 64-bit combinations.
If this delay is not respected, the latest command will be ignored.
6.3.8 Set Password Protection Mode command
The Set Password Protection Mode command puts the device in Password Protection mode by
programming the Password Protection Mode Lock bit to ‘1’. This command can be issued either
with the Reset/Block Temporary Unprotect pin, RP, at VID or at VIH.
Six cycles are required to issue a Set Password Protection Mode command: The first two cycles are unlock cycles.
2. The third cycle issues the command.
3. The fourth and fifth cycles select the address (see Table 17: Protection Command
Addresses).
4. The last cycle verifies if the operation has been successful. If DQ0 is set to ’1’, the device
has successfully entered the Password Protection mode. If DQ0 is ‘0’, the operation has
failed and the command must be re-issued.
There must be a 100µs delay between the fourth and fifth cycles.
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Once the Password Protection mode is activated the device will permanently remain in this
mode.
6.3.9 Verify Password Protection Mode command
The Verify Password Protection Mode command reads the status of the Password Protection
Mode Lock Bit. If it is ‘1’, the device is in Password Protection mode.
6.3.10 Set Standard Protection Mode command
The Set Standard Protection Mode command puts the device in Standard Protection mode by
programming the Standard Protection Mode Lock bit to ‘1’.
Six cycles are required to issue the Standard Protection Mode command: The first two cycles are unlock cycles.
2. The third cycle issues the program command.
3. The fourth and fifth cycles select the address (see Table 17: Protection Command
Addresses).
4. The last cycle verifies if the operation has been successful. If DQ0 is set to ’1’, the
Standard Protection Mode has been successfully activated. If DQ0 is ‘0’, the operation has
failed and the command must be re-issued.
There must be a 100µs delay between the fourth and fifth cycles.
Once the Standard Protection mode is activated the device will permanently remain in this
mode.
6.3.11 Verify Standard Protection Mode command
The Verify Standard Protection Mode command reads the status of the Standard Protection
Mode Lock Bit. If it is ‘1’, the device is in Standard Protection mode.
6.3.12 Set Non-Volatile Modify Protection Bit command
A block or group of blocks can be protected from program or erase by issuing a Set Non-Volatile
Modify Protection Bit command along with the block address. This command sets the Non-
Volatile Modify Protection bit to ‘1’ for a given block or group of blocks.
Six cycles are required to issue the command: The first two cycles are unlock cycles.
2. The third cycle issues the program command.
3. The fourth and fifth cycles select the address (see Table 17: Protection Command
Addresses).
4. The last cycle verifies if the operation has been successful. If DQ0 is set to ’1’, the Non-
Volatile Modify Protection bit has been successfully programmed. If DQ0 is ‘0’, the
operation has failed and the command must be re-issued.
There must be a 100µs delay between the fourth and fifth cycles.
The Non-Volatile Modify Protection bits are erased simultaneously by issuing a Clear Non-
Volatile Modify Protection Bits command except if the Lock-Down bit is set to ‘1’.
The Non-Volatile Modify Protection bits can be set a maximum of 100 times.
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6.3.13 Verify Non-Volatile Modify Protection Bit command
The status of a Non-Volatile Modify Protection bit for a given block or group of blocks can be
read by issuing a Verify Non-Volatile Modify Protection Bit command along with the block
address.
6.3.14 Clear Non-Volatile Modify Protection Bits command
This command is used to clear all Non-Volatile Modify Protection bits. No specific block address
is required. If the Lock-Down bit is set to ‘1’, the command will fail.
Six cycles are required to issue a Clear Non-Volatile Modify Protection Bits command: The first two cycles are unlock cycles.
2. The third cycle issues the command.
3. The last three cycles verify if the operation has been successful. If DQ0 is set to ’0’, all
Non-Volatile Modify Protection bits have been successfully cleared. If DQ0 is ‘1’, the
operation has failed and the command must be re-issued.
There must be a 12ms delay between the fourth and fifth cycles.
6.3.15 Set Lock Bit command
The Set Lock Bit command individually sets the Lock bit to ‘1’ for a given block or group of
blocks.
If the Non-Volatile Lock bit for the same block or group of blocks is set, the block is locked
regardless of the value of the Lock bit. (see Table 10: Block Protection Status).
6.3.16 Clear Lock Bit command
The Clear Lock Bit command individually clears (sets to ‘0’) the Lock Bit for a given block or
group of blocks.
If the Non-Volatile Lock bit for the same block or group of blocks is set, the block or group of
blocks remains locked (see Table 10: Block Protection Status).
6.3.17 Verify Lock Bit command
The status of a Lock bit for a given block can be read by issuing a Verify Lock Bit command
along with the block address.
6.3.18 Set Lock-Down Bit command
This command is used to set the Lock-Down bit to ‘1’ thus protecting the Non-Volatile Modify
Protection bits from program and erase.
There is no Unprotect Lock-Down Bit command.
6.3.19 Verify Lock-Down Bit command
This command is used to read the status of the Lock-Down bit. The status is output on bit DQ1.
If DQ1 is ‘1’, all the Non-Volatile Modify Protection bits are protected from program or erase
operations.
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Table 15. Block Protection Commands, 8-bit Mode
Table 16. Block Protection Commands, 16-bit Mode OW Extended Block Protection Bit Address (A7-A0=’00011010’), X Don’t Care. All values in the table are in hexadecimal. Grey cells represent Read cycles. The other cells are Write cycles. A 100µs timeout is required between cycles 4 and 5.
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Address, PL Password Protection Mode Lock Bit Address, PW Password Data, PWA Password Address, RPW Password
Data Being Verified, NVMP Non-Volatile Modify Protection Bit Address, OW Extended Block Protection Bit Address, X Don’t
Care. All values in the table are in hexadecimal. Addresses are described in Table 17: Protection Command Addresses. During Unlock and Command cycles, if the lower address bits are 555h or 2AAh then the address bits higher than A11
(except where BA is required) and data bits higher than DQ7 are Don't Care. A Reset Command must be issued to return to the Read mode. The 4th Bus Write cycle programs a protection bit (Extended Block Protection bit, Password Protection Mode Lock bit,
Standard Protection Mode Lock bit, and a block NVMP bit). The 5th and 6th cycles verify that the bit has been successively
programmed when DQ0=1. If DQ0=0 in the 6th cycle, the program command must be issued again and verified again. A
100µs delay is required between the 4th and the 5th cycle. Data is latched on the rising edge of W. The entire command sequence must be entered for each portion of the password. The command sequence returns FFh if the Password Protection Mode locking bit is set.
10. The password is written over four consecutive cycles, at addresses [0-3]
11. A 2µs timeout is required between any two portions of the password.
12. A 10ms delay is required between the 4th and the 5th cycle.
13. A 12ms timeout is required between cycles 4 and 5.
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Table 17. Protection Command Addresses
Table 18. Program, Erase Times and Program, Erase Endurance Cycles
14. Cycle 4 erases all Non-Volatile Modify Protection bits. Cycles 5 and 6 verify that the bits have been successfully cleared
when DQ0=0. If DQ0=1 in the 6th cycle, the erase command must be issued again and verified again. Before issuing the
erase command, all Non-Volatile Modify Protection bits should be programmed to prevent over erasure.
15. DQ1=1 if the Non-Volatile Modify Protection bit is locked, DQ1 = 0 if it is unlocked. Typical values measured at room temperature and nominal voltages. Sampled, but not 100% tested. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. Maximum value measured at worst case conditions for both temperature and VCC.
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7 Status Register
The M29DW128F has one Status Register. The Status Register provides information on the
current or previous Program or Erase operations executed in each bank. The various bits
convey information and errors on the operation. Bus Read operations from any address within
the Bank, always read the Status Register during Program and Erase operations. It is also read
during Erase Suspend when an address within a block being erased is accessed.
The bits in the Status Register are summarized in Table 19: Status Register Bits.
7.1 Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling Bit is output on DQ7 when the Status Register is read.
During Program operations the Data Polling Bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory returns
to Read mode and Bus Read operations from the address just programmed output DQ7, not its
complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read mode.
In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within
a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/
Erase Controller has suspended the Erase operation.
Figure 8: Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid
Address is the address being programmed or an address within the block being erased.
7.2 Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully
completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on
DQ6 when the Status Register is read.
During a Program/Erase operation the T oggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the operation
the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block
being erased. The T oggle Bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.
Figure 9: Toggle Flowchart, gives an example of how to use the Data Toggle Bit. Figure 16 and
Figure 17 describe Toggle Bit timing waveform.
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7.3 Error Bit (DQ5)
The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error
Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct
data to the memory. If the Error Bit is set a Read/Reset command must be issued before other
commands are issued. The Error bit is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do
so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of
the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’
to ’1’.
7.4 Erase Timer Bit (DQ3)
The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation
during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase
Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’
and additional blocks to be erased may be written to the Command Interface. The Erase Timer
Bit is output on DQ3 when the Status Register is read.
7.5 Alternative Toggle Bit (DQ2)
The Alternative Toggle Bit can be used to monitor the Program/Erase controller during Erase
operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read.
During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc.,
with successive Bus Read operations from addresses within the blocks being erased. A
protected block is treated the same as a block not being erased. Once the operation completes
the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory array data as if
in Read mode.
After an Erase operation that causes the Error Bit to be set, the Alternative Toggle Bit can be
used to identify which block or blocks have caused the error. The Alternative T oggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within
blocks that have not erased correctly. The Alternative T oggle Bit does not change if the
addressed block has erased correctly.
Figure 16 and Figure 17 describe Alternative Toggle Bit timing waveform.
7.6 Write to Buffer and Program Abort Bit (DQ1)
The Write to Buffer and Program Abort bit, DQ1, is set to ‘1’ when a Write to Buffer and
Program operation aborts. The Write to Buffer and Program Abort and Reset command must
be issued to return the device to Read mode (see Write to Buffer and Program in COMMANDS
section).
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Table 19. Status Register Bits Unspecified data bits should be ignored. Figure 16 and Figure 17 describe Toggle and Alternative Toggle Bits timing waveforms.
Figure 8. Data Polling Flowchart
