M28W800BT100N6T ,8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYTABLE OF CONTENTSSUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... ..
M28W800CB90N6 ,8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYM28W800CTM28W800CB8 Mbit (512Kb x16, Boot Block)3V Supply Flash Memory
M28W800CT70N6 ,8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYTABLE OF CONTENTSSUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... ..
M28W800CT70ZB6T ,8 Mbit 512Kb x16, Boot Block 3V Supply Flash Memoryfeatures an asymmetrical blocked ar- DD DDQ PPchitecture. The M28W800C has an array of 23blocks: 8 ..
M28W800CT90N6 ,8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYLogic Diagram1.65V. An optional 12V V power supply is pro-PPvided to speed up customer programming. ..
M28W800CT-90N6 ,8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Packages–V = 2.7V to 3.6V Core Power SupplyDD–V = 1.65V ..
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M28W800BT100N6T
8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORY
1/42May 2002
M28W800BT
M28W800BB Mbit (512Kb x16, Boot Block) Supply Flash Memory
FEATURES SUMMARY SUPPLY VOLTAGE
–VDD= 2.7Vto 3.6V Core Power Supply
–VDDQ= 1.65Vto 3.6Vfor Input/Output
–VPP= 12V for fast Program (optional) ACCESS TIME: 70, 85, 90,100ns PROGRAMMING TIME 10μs typical Double Word Programming Option COMMON FLASH INTERFACE 64bit Security Code MEMORY BLOCKS Parameter Blocks (Topor Bottom location) Main Blocks BLOCK PROTECTIONon TWO PARAMETER
BLOCKS
–WPfor Block Protection AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M28W800BT: 8892h Bottom Device Code, M28W800BB: 8893h
M28W800BT, M28W800BB2/42
TABLE OF CONTENTS
SUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... .....5Figure 2.LogicDiagram.. ...... ....... ...... ....... ...... ....... ...... ...... .....5
Table1. Signal Names... ...... ....... ...... ....... ...... ....... ...... ...... .....5
Figure3. TSOP Connections..... ....... ...... ....... ...... ....... ...... ...... .....6
Figure4. TFBGA Connections (Top view through package). ...... ....... ...... ...... .....7
Figure 5.Block Addresses. ...... ....... ...... ....... ...... ....... ...... ...... .....8
SIGNAL DESCRIPTIONS .... ...... ....... ...... ....... ...... ....... ...... ...... .....9Address Inputs (A0-A18).. ...... ....... ...... ....... ...... ....... ...... ...... .....9
Data Input/Output (DQ0-DQ15)... ....... ...... ....... ...... ....... ...... ...... .....9
Chip Enable (E)... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Output Enable (G). ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Write Enable (W).. ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Write Protect (WP). ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Reset(RP). ...... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
VDD Supply Voltage...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
VDDQ Supply Voltage..... ...... ....... ...... ....... ...... ....... ...... ...... .....9
VPP Program Supply Voltage .... ....... ...... ....... ...... ....... ...... ...... .....9
VSS Ground. ..... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
BUS OPERATIONS... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10Read. .... ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Write. .... ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Output Disable. ... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Standby.. ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Automatic Standby. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Reset. ... ....... ...... ...... ....... ...... ....... ...... ....... ...... ... ... ....10
Table 2.Bus Operations.. ...... ....... ...... ....... ...... ....... ...... ...... ....10
COMMANDINTERFACE .... ...... ....... ...... ....... ...... ....... ...... ...... ....11Read Memory Array command ... ....... ...... ....... ...... ....... ...... ...... ....11
Read Status Register Command.. ....... ...... ....... ...... ....... ...... ...... ....11
Read Electronic Signature Command ..... ...... ....... ...... ....... ...... ...... ....11
Read CFIQueryCommand...... ....... ...... ....... ...... ....... ...... ...... ....11
Block Erase Command ... ...... ....... ...... ....... ...... ....... ...... ...... ....11
Program Command ...... ...... ....... ...... ....... ...... ....... ...... ...... ....11
Double Word Program Command. ....... ...... ....... ...... ....... ...... ...... ....12
Clear Status Register Command.. ....... ...... ....... ...... ....... ...... ...... ....12
Program/Erase Suspend Command ...... ...... ....... ...... ....... ...... ...... ....12
Program/Erase Resume Command ...... ...... ....... ...... ....... ...... ...... ....12
Block Protection... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....12
Table 3.Commands ..... ...... ....... ...... ....... ...... ....... ...... ...... ....13
Table 4.Read ElectronicSignature....... ...... ....... ...... ....... ...... ...... ....13
Table 5.MemoryBlocks Protection Truth Table ... ....... ...... ....... ...... ...... ....13
3/42
M28W800BT, M28W800BBTable 6.Program,Erase Times and Program/Erase Endurance Cycles .... ...... ...... ....14
STATUS REGISTER.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....15Program/Erase Controller Status (Bit7) ... ...... ....... ...... ....... ...... ...... ....15
Erase Suspend Status (Bit6) .... ....... ...... ....... ...... ....... ...... ...... ....15
Erase Status(Bit5) ...... ...... ....... ...... ....... ...... ....... ...... ...... ....15
Program Status (Bit4) .... ...... ....... ...... ....... ...... ....... ...... ...... ....15
VPP Status (Bit 3).. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....15
Program Suspend Status (Bit2).. ....... ...... ....... ...... ....... ...... ...... ....15
Block Protection Status (Bit 1).... ....... ...... ....... ...... ....... ...... ...... ....16
Reserved (Bit 0)... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....16
Table 7.StatusRegister Bits ..... ....... ...... ....... ...... ....... ...... ...... ....16
MAXIMUM RATING... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....17Table 8.Absolute Maximum Ratings...... ...... ....... ...... ....... ...... ...... ....17
and AC PARAMETERS.. ...... ....... ...... ....... ...... ....... ...... ...... ....18Table9. Operating and AC Measurement Conditions...... ...... ....... ...... ...... ....18
Figure 6.AC Measurement I/O Waveform. ...... ....... ...... ....... ...... ...... ....18
Figure7. AC Measurement Load Circuit... ...... ....... ...... ....... ...... ...... ....18
Table 10. Device Capacitance.... ....... ...... ....... ...... ....... ...... ...... ....18
Table 11. DC Characteristics..... ....... ...... ....... ...... ....... ...... ...... ....19
Figure 8.Read AC Waveforms ... ....... ...... ....... ...... ....... ...... ...... ....20
Table 12. Read AC Characteristics ....... ...... ....... ...... ....... ...... ...... ....20
Figure9. Write AC Waveforms, Write Enable Controlled... ...... ....... ...... ...... ....21
Table 13. Write AC Characteristics, Write Enable Controlled ...... ....... ...... ...... ....22
Figure 10. Write AC Waveforms, Chip Enable Controlled... ...... ....... ...... ...... ....23
Table 14. Write AC Characteristics, Chip Enable Controlled ...... ....... ...... ...... ....24
Figure 11. Power-Up and Reset AC Waveforms... ....... ...... ....... ...... ...... ....25
Table 15. Power-Up and ResetACCharacteristics ....... ...... ....... ...... ...... ....25
PACKAGE MECHANICAL... ...... ....... ...... ....... ...... ....... ...... ...... ....26Figure 12. TSOP48-48 lead Plastic Thin Small Outline,12 x20mm, Package Outline .... ....26
Table 16. TSOP48-48 lead Plastic Thin Small Outline,12x 20mm, Package Mechanical Data.26
Figure 13. TFBGA46 6.39x6.37mm- 8x6 ball array, 0.75mm pitch, Bottom View Package Outline27
Table 17. TFBGA46 6.39x6.37mm- 8x6 ball array, 0.75mm pitch,Package Mechanical Data ...27
Figure 14. TFBGA46 Daisy Chain- Package Connections (Top view through package) .... ....28
Figure 15. TFBGA46 Daisy Chain- PCB Connections proposal (Top view through package) ....28
PART NUMBERING.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....29Table 18. Ordering Information Scheme ... ...... ....... ...... ....... ...... ...... ....29
Table 19. DaisyChain Ordering Scheme.. ...... ....... ...... ....... ...... ...... ....29
REVISION HISTORY.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....30Table 20. Document Revision History ..... ...... ....... ...... ....... ...... ...... ....30
M28W800BT, M28W800BB4/42
APPENDIXA. BLOCK ADDRESS TABLES.. ...... ....... ...... ....... ...... ...... ....31Table 21. Top Boot Block Addresses, M28W800BT ....... ...... ....... ...... ...... ....31
Table 22. Bottom Boot Block Addresses, M28W800BB .... ...... ....... ...... ...... ....31
APPENDIXB. COMMONFLASH INTERFACE (CFI). ....... ...... ....... ...... ...... ....32Table 23. Query Structure Overview ...... ...... ....... ...... ....... ...... ...... ....32
Table 24. CFI Query Identification String.. ...... ....... ...... ....... ...... ...... ....32
Table 25. CFIQuerySystem Interface Information. ....... ...... ....... ...... ...... ....33
Table 26. Device Geometry Definition ..... ...... ....... ...... ....... ...... ...... ....34
Table 27. Primary Algorithm-Specific Extended Query Table ...... ....... ...... ...... ....35
Table 28. Security Code Area .... ....... ...... ....... ...... ....... ...... ...... ....35
APPENDIXC. FLOWCHARTS AND PSEUDO CODES....... ...... ....... ...... ...... ....36Figure 16. Program Flowchart and Pseudo Code.. ....... ...... ....... ...... ...... ....36
Figure 17. Double Word Program Flowchart and Pseudo Code .... ....... ...... ...... ....37
Figure 18. Program Suspend& Resume Flowchart and Pseudo Code ..... ...... ...... ....38
Figure 19. Erase Flowchart and Pseudo Code .... ....... ...... ....... ...... ...... ....39
Figure 20. Erase Suspend& Resume Flowchart and Pseudo Code. ....... ...... ...... ....40
APPENDIXD. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE ... ....41Table 29. Write State Machine Current/Next...... ....... ...... ....... ...... ...... ....41
5/42
M28W800BT, M28W800BB
SUMMARY DESCRIPTIONThe M28W800Bisa8 Mbit (512Kbitx 16) non-vol-
atileFlash memory that canbeerasedelectrically the block level and programmed in-systemona
Word-by-Word basis. These operations can be
performed usinga single low voltage (2.7to 3.6V)
supply. VDDQ allowsto drive the I/O pin downto
1.65V. An optional 12V VPP power supplyis pro-
videdto speedup customer programming.
The device featuresan asymmetrical blocked ar-
chitecture. The M28W800B has an arrayof 23
blocks:8 Parameter Blocksof4 KWord and 15
Main Blocksof 32 KWord. M28W800BT has the
Parameter Blocksat the topof the memory ad-
dress space while the M28W800BB locates the
Parameter Blocks starting from the bottom. The
memory maps are shownin Figure5, Block Ad-
dresses.
Parameter blocks0 and1 can be protected from
accidental programmingor erasure. Each block
canbe erased separately. Erase canbe suspend-in orderto perform either reador programin
any other block and then resumed. Program can suspendedto read datain any other block and
then resumed. Each block can be programmed
and erased over 100,000 cycles.
Program and Erase commands are writtento the
Command Interfaceof the memory. An on-chip
Program/Erase Controller takes careof the tim-
ings necessary for program and erase operations.
The endofa programor erase operation canbe
detected and any error conditions identified. The
command set requiredto control the memoryis
consistent with JEDEC standards.
The memoryis offeredin TSOP48 (10X 20mm),
and TFBGA46 (6.39x 6.37mm, 0.75mm pitch)
packages andis supplied withall the bits erased
(setto ’1’).
M28W800BT, M28W800BB6/42
7/42
M28W800BT, M28W800BB
M28W800BT, M28W800BB8/42
9/42
M28W800BT, M28W800BB
SIGNAL DESCRIPTIONSSee Figure2 Logic Diagram and Table 1,Signal
Names,fora brief overviewof the signals connect-to this device.
Address Inputs (A0-A18). The Address Inputs
select the cellsin the memory arrayto access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interfaceof the internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data storedat the selected address
duringa Bus Read operationor inputsa command datatobe programmed duringa Write Bus op-
eration.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enableis VILand Resetisat VIH the deviceisin active
mode. When Chip Enableisat VIH the memoryis
deselected, the outputs are high impedance and
the power consumptionis reducedto the stand-by
level.
Output Enable (G). The Output Enable controls
data outputs during the Bus Read operationof the
memory.
WriteEnable(W). The Write Enable controls the
Bus Write operationof the memory’s Command
Interface. The data and address inputs are latched therisingedgeof ChipEnable,E, orWrite En-
able, W, whichever occurs first.
Write Protect (WP). Write Protectis an inputto
protector unprotect the two lockable parameter
blocks. When Write Protectisat VIL, the lockable
blocks are protected and Programor Erase oper-
ations are not possible. When Write Protectisat
VIH, the lockable blocks are unprotected and can programmedor erased (referto Table4, Mem-
ory Blocks Protection Truth).
Reset (RP). The Reset input providesa hard-
ware resetofthe memory. When ResetisatVIL,
the memoryisin reset mode: the outputs are high
impedance and the current consumptionis mini-
mized. When Resetisat VIH, the deviceisin nor-
mal operation. Exiting reset mode the device
enters read array mode, buta negative transition Chip Enableora changeof the addressis re-
quiredto ensure valid data outputs.
VDD Supply Voltage. VDD provides the power
supplyto the internal coreof the memory device.is the main power supply for all operations
(Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the
power supplyto the I/O pins and enablesall Out-
putstobe powered independently from VDD.VDDQ
canbetied toVDDor can usea separate supply.
VPP Program Supply Voltage. VPPis botha
control input anda power supply pin. The two
functions are selected by the voltage range ap-
pliedto the pin. The Supply Voltage VDD and the
Program Supply Voltage VPP canbe appliedin
any order. VPPis keptina low voltage range (0Vto 3.6V)
VPPis seenasa control input.In this casea volt-
age lower than VPPLK givesan absolute protection
against programor erase, while VPP >VPP1 en-
ables these functions (see Table 11, DC Charac-
teristics for the relevant values). VPPis only
sampledat the beginningofa programor erase;a
changeinits value after the operation has started
does not have any effect and programor erase op-
erations continue. VPPisin the range 11.4Vto 12.6Vit actsasa
power supply pin.In this condition VPP must be
stable until the Program/Erase algorithmis com-
pleted (see Table13 and 14).
VSS Ground. VSSis the reference forall voltage
measurements.
Note: Each deviceina system should have
VDD,VDDQ and VPP decoupled witha 0.1μF ca-
pacitor closeto the pin. See Figure7, AC Mea-
surement Load Circuit. The PCB trace widths
should be sufficientto carry the required VPP
Program and Erase currents.
M28W800BT, M28W800BB10/42
BUS OPERATIONSThere are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and Re-
set. See Table2, Bus Operations,fora summary.
Typically glitchesof less than 5nson Chip Enable Write Enable are ignoredby the memory anddo
not affect bus operations.
Read. Read Bus operations are usedto output
the contentsof the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output En-
ablemust beat VILin orderto performa read op-
eration. The Chip Enable input shouldbe usedto
enable the device. Output Enable shouldbe used gate data onto the output. The data read de-
pends on the previous command writtento the
memory (see Command Interface section). See
Figure8, Read Mode AC Waveforms, and Table
12, Read AC Characteristics, for detailsof when
the output becomes valid.
Read modeis the default stateof the device when
exiting Resetor after power-up.
Write. Bus Write operations write Commandsto
the memoryor latch Input Datatobe programmed. write operationis initiated when Chip Enable
and Write Enable areat VIL with Output Enableat
VIH. Commands, Input Data and Addresses are
latchedon the rising edgeof Write Enableor Chip
Enable, whichever occurs first.
See Figures9 and 10, Write AC Waveforms, and
Tables 13 and 14, Write AC Characteristics, for
detailsof the timing requirements.
Output Disable. The data outputs are high im-
pedance when the Output Enableisat VIH.
Standby. Standby disables mostof the internal
circuitry allowinga substantial reductionof the cur-
rent consumption. The memoryisin stand-by
when Chip Enableisat VIH and thedeviceisin
read mode. The power consumptionis reducedto
the stand-by level and the outputs are setto high
impedance, independently from the Output Enable Write Enable inputs.If Chip Enable switchesto
VIH duringa programor erase operation, the de-
vice enters Standby mode when finished.
Automatic Standby. Automatic Standby pro-
videsa low power consumption state during Read
mode. Followinga read operation, the device en-
ters Automatic Standby after 150nsof bus inactiv-
ity, evenif Chip Enableis low, VIL, and the supply
currentis reducedto IDD1. The data Inputs/Out-
puts will still output data.
Reset. During Reset mode, when Output Enable low, VIL, the memoryis deselected and the out-
puts are high impedance. The memoryisin Reset
mode when Resetisat VIL. The power consump-
tionis reducedto the Standby level, independently
from the Chip Enable, Output Enableor Write En-
able inputs.If Resetis pulledto VSS duringa Pro-
gramor Erase, this operationis aborted and the
memory contentisno longer valid.
Table2. Bus OperationsNote:X= VILor VIH,VPPH =12V± 5%.
11/42
M28W800BT, M28W800BB
COMMAND INTERFACEAll Bus Write operationsto the memory are inter-
preted by the Command Interface. Commands
consistof oneor more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dlesall timings and verifies the correct execution the Program and Erase commands. The Pro-
gram/Erase Controller providesa Status Register
whose output maybe readat any time,to monitor
the progressof an operation,or the Program/
Erase states. See Appendix D, Table 29, Write
State Machine Current/Next, fora summaryof the
Command Interface.
The Command Interfaceis resetto Read mode
when poweris first applied, when exiting from Re-
setor whenever VDDis lower than VLKO.Com-
mand sequences must be followed exactly. Any
invalid combinationof commands will reset the de-
viceto Read mode. Referto Table3, Commands, conjunction with the text descriptions below.
Read Memory Array commandTheReadcommand returns the memoryto its
Read mode. One Bus Write cycleis requiredtois-
sue the Read Memory Array command and return
the memoryto Read mode. Subsequent read op-
erations will read the addressed location and out-
put the data. Whena device Reset occurs, the
memory defaultsto Read mode.
Read Status Register CommandThe Status Register indicates whena programor
erase operationis complete and the successor
failureof the operation itself. Issuea Read Status
Register commandto read the Status Register’s
contents. Subsequent Bus Read operations read
the Status Register,at any address, until another
commandis issued. See Table7, Status Register
Bits,for detailson the definitionsof the bits.
The Read Status Register command may beis-
suedat any time, even duringa Program/Erase
operation. Any Read attempt duringa Program/
Erase operation will automatically output the con-
tentof the Status Register.
Read Electronic Signature CommandThe Read Electronic Signature command reads
the Manufacturer and Device Codes.
The Read Electronic Signature command consists one write cycle,a subsequent read will output
the Manufactureror the Device Code depending the levelsof A0. The Manufacturer Codeis out-
put when the address line A0isat VIL, the Device
Codeis output when A0isat VIH. Addresses A1- must be keptto VIL, other addresses are ig-
nored. The codes are output on DQ0-DQ7 with
DQ8-DQ15at 00h. (see Table4)
Read CFI Query CommandThe Read Query Commandis usedto read data
from theCommonFlash Interface(CFI) Memory
Area, allowing programming equipmentor appli-
cationsto automatically match their interfaceto
the characteristicsof the device.
One Bus Write cycleis requiredto issue the Read
Query Command. Once the commandis issued
subsequent Bus Read operations read from the
Common Flash Interface Memory Area. See Ap-
pendixB, Common Flash Interface, Tables 23, 24,
25, 26, 27 and 28 for details on the information
containedin the Common Flash Interface memory
area.
Block Erase CommandTheBlock Erase command can beusedtoerase block.It setsall the bits within the selected block ’1’. All previous datain the blockis lost.If the
blockis protected then the Erase operation will
abort, the datain the block will notbe changed and
the Status Register will output the error.
Two Bus Write cycles are requiredto issue the
command. The first bus cycle setsup the Erase command. The second latches the block addressin the
internal state machine and starts the Program/
Erase Controller. the second bus cycleis not Write Erase Confirm
(D0h), Status Register bitsb4 and b5 are set and
the command aborts.
Erase abortsif Reset turnsto VIL.As data integrity
cannotbe guaranteed when the Erase operationis
aborted, the block mustbe erased again.
During Erase operations the memory will only ac-
cept the Read Status Register command and the
Program/Erase Suspend command,all other com-
mands will be ignored. Typical Erase times are
givenin Table6, Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
See AppendixC, Figure 19, Erase Flowchart and
Pseudo Code,for the flowchartfor using the Erase
command.
Program CommandThe memory array can be programmed word-by-
word. Two bus write cycles are requiredto issue
the Program command. The first bus cycle setsup the Program
command. The secondlatches the Address and the Datato written and starts the Program/Erase
Controller.
During Program operations the memory will only
accept the Read Status Register command and
the Program/Erase Suspend command. All other
M28W800BT, M28W800BB12/42
commands willbe ignored. Typical Program times
are givenin Table6, Program, Erase Times and
Program/Erase Endurance Cycles.
Programming abortsif Reset goesto VIL. As data
integrity cannotbe guaranteed when the program
operationis aborted, the block containing the
memory location must be erased and repro-
grammed.
See Appendix C, Figure 16, Program Flowchart
and Pseudo Code, for the flowchart for using the
Program command.
Double Word Program CommandThis featureis offeredto improve the programming
throughput, writinga pageof two adjacent words parallel.The two words must differ only for the
address A0. Programming should not be attempt- when VPPis notat VPPH. The command canbe
executedif VPPis below VPPH but the resultis not
guaranteed.
Three bus write cycles are necessaryto issue the
Double Word Program command. The first bus cycle setsup the Double Word
Program command. The second bus cycle latches the Address and
the Dataof the first wordtobe written. The third bus cycle latches the Address and the
Dataof the second wordtobe written and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started. Program-
ming abortsif Reset goesto VIL. As data integrity
cannot be guaranteed when the program opera-
tionis aborted, the block containing the memory
location mustbe erased and reprogrammed.
See Appendix C, Figure 17, Double Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Double Word Program
command.
Clear Status Register CommandThe Clear Status Register command canbe used reset bits1,3,4 and5in the Status Registerto
‘0’. One bus write cycleis requiredto issue the
Clear Status Register command.
The bitsin the Status Registerdo not automatical- returnto‘0’ whena new Programor Erase com-
mandis issued. The error bitsin the Status
Register should be cleared before attemptinga
new Programor Erase command.
Program/Erase Suspend CommandThe Program/Erase Suspend commandis usedto
pausea Programor Erase operation. One bus
write cycleis requiredto issue the Program/Erase
command and pause the Program/Erase control-
ler.
During Program/Erase Suspend the CommandIn-
terface will accept the Program/Erase Resume,
Read Array, Read Status Register, Read Electron- Signature and Read CFI Query commands. Ad-
ditionally,if the suspend operation was Erase then
the Program command will alsobe accepted. Only
the blocks not being erased may be reador pro-
grammed correctly.
Duringa Program/Erase Suspend, the device can placedina pseudo-standby mode by taking
Chip Enableto VIH. Program/Eraseis abortedif
Reset turnsto VIL.
See AppendixC, Figure 18, Program Suspend&
Resume Flowchart and Pseudo Code, and Figure
20, Erase Suspend& Resume Flowchart and
Pseudo Codefor flowchartsfor using the Program/
Erase Suspend command.
Program/Erase Resume CommandThe Program/Erase Resume command can be
usedto restart the Program/Erase Controller after Program/Erase Suspend operation has paused
it. One Bus Write cycleis requiredto issue the
command. Once the commandis issued subse-
quent Bus Read operations read the Status Reg-
ister.
See AppendixC, Figure 18, Programor Double
Word Program Suspend& Resume Flowchart and
Pseudo Code, and Figure 20, Erase Suspend&
Resume Flowchart and Pseudo Code for flow-
chartsfor using the Program/Erase Resume com-
mand.
Block ProtectionTwo parameter/lockable blocks (blocks#0 and #1)
canbe protected against Programor Erase oper-
ations. Unprotected blocks canbe programmedor
erased. protect the two lockable blocks set Write Pro-
tectto VIL. When VPPis below VPPLKall blocks are
protected. Any attemptto Programor Erase pro-
tected blocks will abort, the datain the block will
not be changed and the Status Register outputs
the error.
Table5, Memory Blocks Protection Truth Table,
defines the protection methods.
13/42
M28W800BT, M28W800BB
Table3. CommandsNote:1.X= Don't Care. A0=VIL outputs Manufacturer code, A0=VIH outputs Device code. Address A7-A1 mustbeVIL. Addr1 and Addr2 mustbe consecutive Addresses differing onlyforA0.
Table4. Read Electronic SignatureNote: RP =VIH.
Table5. Memory Blocks Protection Truth TableNote:1.X= Don't Care VPPmust alsobe greater thanthe Program Voltage Lock Out VPPLK.
M28W800BT, M28W800BB14/42
Table6. Program, Erase Times and Program/Erase Endurance Cycles
15/42
M28W800BT, M28W800BB
STATUS REGISTERThe Status Register provides information on the
currentor previous Programor Erase operation.
The various bits convey information and errorson
the operation. To read the Status register the
Read Status Register command canbe issued,re-
ferto the Read Status Register Command section. output the contents, the Status Registeris
latchedon the falling edgeof the Chip Enableor
Output Enable signals, and canbe read until Chip
Enableor Output Enable returnsto VIH. Either
Chip Enableor Output Enable mustbe toggledto
update the latched data.
Bus Read operations from any address always
read the Status Register during Program and
Erase operations.
The bitsin the Status Register are summarizedin
Table7, Status Register Bits. Referto Table7in
conjunction with the following text descriptions.
Program/Erase Controller Status (Bit7). The Pro-
gram/Erase Controller Statusbit indicates whether
the Program/Erase Controlleris activeor inactive.
When the Program/Erase Controller Statusbitis
Low (setto ‘0’), the Program/Erase Controlleris
active; when the bitis High (setto ‘1’), the Pro-
gram/Erase Controlleris inactive, and the device readyto processa new command.
The Program/Erase Controller Statusis Low im-
mediately aftera Program/Erase Suspend com-
mandis issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus- thebitis High.
During Program, Erase, operations the Program/
EraseControllerStatusbit canbepolledtofindthe
endof the operation. Other bitsin the Status Reg-
ister should notbe tested until the Program/Erase
Controller completes the operation and thebitis
High.
After the Program/Erase Controller completesits
operation the Erase Status, Program Status, VPP
Status and Block Protection Status bits shouldbe
testedfor errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Statusbit (setto ‘1’) indicates thatan Erase
operation has been suspendedoris goingto be
suspended.
The Erase Suspend Status should onlybe consid-
ered valid when the Program/Erase Controller Sta-
tusbitis High (Program/Erase Controller inactive).
Bit7is set within 30μsof the Program/Erase Sus-
pend command being issued therefore the memo- may still complete the operation rather than
entering the Suspend mode.
Whena Program/Erase Resume commandisis-
sued the Erase Suspend Statusbit returns Low.
Erase Status (Bit5). The Erase Statusbit canbe
usedto identifyif the memory has failedto verify
that the block has erased correctly. When the
Erase Statusbitis High (setto ‘1’), the Program/
Erase Controller has applied the maximum num-
berof pulsesto the block and still failedto verify
that the block has erased correctly. The Erase Sta-
tus bit should be read once the Program/Erase
Controller Statusbitis High (Program/Erase Con-
troller inactive).
Once set High, the Erase Statusbit can onlybere-
set Lowbya Clear Status Register commandora
hardware reset.If set Highit should be reset be-
forea new Programor Erase commandis issued,
otherwise the new command will appearto fail.
Program Status (Bit 4). The Program Statusbit usedto identifya Program failure. When the
Program Status bitis High (setto ‘1’), the Pro-
gram/Erase Controller has applied the maximum
numberof pulsesto the byte and still failedto ver-
ify thatit has programmed correctly. The Program
Statusbit shouldbe read once the Program/Erase
Controller Statusbitis High (Program/Erase Con-
troller inactive).
Once set High, the Program Statusbit can onlybe
reset Lowbya Clear Status Register commandor hardware reset.If set Highit shouldbe reset be-
forea new commandis issued, otherwise the new
command will appearto fail.
VPP Status (Bit3). The VPP Status bit can be
usedto identifyan invalid voltageon the VPP pin
during Program and Erase operations. The VPP
pinis only sampledat the beginningofa Program Erase operation. Indeterminate results can oc-
curif VPP becomes invalid duringan operation.
When the VPP Statusbitis Low (setto ‘0’), the volt-
ageon the VPP pin was sampledata valid voltage;
when the VPP Statusbitis High (setto ‘1’), the VPP
pin hasa voltage thatis below the VPP Lockout
Voltage, VPPLK, the memoryis protected and Pro-
gram and Erase operations cannotbe performed.
Once set High, the VPP Statusbit can onlybe reset
Low bya Clear Status Register commandora
hardware reset.If set Highit shouldbe reset be-
forea new Programor Erase commandis issued,
otherwise the new command will appearto fail.
Program Suspend Status (Bit 2). The Program
Suspend Statusbit (setto ‘1’) indicates thata Pro-
gram operation has been suspendedoris goingto suspended.
The Program Suspend Status should onlybe con-
sidered valid when the Program/Erase Controller
Statusbitis High (Program/Erase Controller inac-
tive). Bit2is set within 5μsof the Program/Erase
Suspend command being issued therefore the
M28W800BT, M28W800BB16/42
memory may still complete the operation rather
than entering the Suspend mode.
Whena Program/Erase Resume commandisis-
sued the Program Suspend Statusbit returns Low.
Block Protection Status (Bit1). The Block Pro-
tectionStatusbit canbeusedtoidentifyifa Pro-
gramor Erase operation has triedto modify the
contentsofa protected block.
When the Block Protection Statusbitis High (set ‘1’),a Programor Erase operation has beenat-
temptedona protected block.
Once set High, the Block Protection Statusbit can
onlybe reset Lowbya Clear Status Register com-
mandora hardware reset.If set Highit shouldbe
reset beforea new commandis issued, otherwise
the new command will appear to fail.
Reserved (Bit 0). Bit0of the Status Registeris
reserved.Its value mustbe masked.
Note: Refer to Appendix C, Flowcharts and
Pseudo Codes, for using the Status Register.
Table7. Status Register BitsNote: Logic level'1'is High,'0'is Low.
17/42
M28W800BT, M28W800BB
MAXIMUM RATINGStressing the deviceabove therating listedinthe
Absolute Maximum Ratings table may cause per-
manent damageto the device. Exposureto Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operationof the deviceat
theseor any other conditions above those indicat-in the Operating sectionsof this specificationis
not implied. Refer alsoto the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table8. Absolute Maximum RatingsNote:1. Dependson range.
M28W800BT, M28W800BB18/42
AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristicsof the device. The parametersin the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 9,
Operating and AC Measurement Conditions. De-
signers should check that the operating conditions their circuit match the measurement conditions
when relyingon the quoted parameters.
Table9. Operating and AC Measurement Conditions
Table 10. Device CapacitanceNote: Sampled only,not 100% tested.
19/42
M28W800BT, M28W800BB
Table 11. DC Characteristics
M28W800BT, M28W800BB20/42
21/42
M28W800BT, M28W800BB
