M28W640 ,64 Mbit 4Mb x16/ Boot Block 3V Supply Flash MemoryTABLE OF CONTENTSSUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... ..
M28W640ECB70N6 ,64 Mbit 4Mb x16/ Boot Block 3V Supply Flash MemoryAbsolute Maximum Ratings . . . . . . . 21DC and AC PARAMETERS . 22Table 13. Operating an ..
M28W640ECB-70N6 ,64 Mbit 4Mb x16/ Boot Block 3V Supply Flash MemoryLogic Diagram . . 5Table 1. Signal Names . . . 5Figure 3. TSOP Connections . . . ..
M28W640ECT70N6 ,64 MBIT (4MB X16, BOOT BLOCK)3V SUPPLY FLASH MEMORYLogic Diagram . . 5Table 1. Signal Names . . 5Figure 3. TSOP Connections . . . ..
M28W640ECT-70N6 ,64 MBIT (4MB X16, BOOT BLOCK)3V SUPPLY FLASH MEMORYFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Packages–V = 2.7V to 3.6V Core Power SupplyDD–V = 1.65V ..
M28W640ECT70ZB6 ,64 Mbit 4Mb x16, Boot Block 3V Supply Flash MemoryAbsolute Maximum Ratings . . . . . . . 20DC and AC PARAMETERS . 21Table 13. Operating an ..
M4T28-BR12SH ,TIMEKEEPER SNAPHAT Battery & CrystalAbsolute Maximum Ratings . 7DC and AC PARAMETERS . . 8Table 3. DC and AC Measurement Co ..
M4T28-BR12SH1 ,TIMEKEEPER SNAPHAT (BATTERY & CRYSTAL)M4T28-BR12SHM4T32-BR12SH® ®TIMEKEEPER SNAPHAT (Battery & Crystal)
M4T32-BR12SH1 ,TIMEKEEPER SNAPHAT (BATTERY & CRYSTAL)Logic Diagram Table 1. Signal NamesX1 Crystal InputX2 Crystal OutputX1 X2V Negative VoltageBAT–V Po ..
M4T32-BR12SH6 ,TIMEKEEPER SNAPHAT (BATTERY & CRYSTAL)TABLE OF CONTENTSSUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... ..
M4Z28-BR00SH1 ,ZEROPOWER SNAPHAT (BATTERY)FEATURES SUMMARY■ PROVIDES BATTERY BACKUP POWER FOR Figure 1. SNAPHAT Top PackageNON-VOLATILE ZEROP ..
M4Z32-BR00SH1 ,ZEROPOWER SNAPHAT (BATTERY)Absolute Maximum Ratings(Table2.) .... ...... ....... ...... ....... ...... ...... .....4DC AND AC ..
M28W640
64 Mbit 4Mb x16/ Boot Block 3V Supply Flash Memory
1/54
PRELIMINARY DATANovember 2001
M28W640CT
M28W640CB Mbit (4Mb x16, Boot Block) Supply Flash Memory
FEATURES SUMMARY SUPPLY VOLTAGE
–VDD= 2.7Vto 3.6V Core Power Supply
–VDDQ= 1.65Vto 3.3Vfor Input/Output
–VPP= 12Vfor fast Program (optional) ACCESS TIME 3.0Vto 3.6V: 80ns 2.7Vto 3.6V: 90ns PROGRAMMING TIME: 10μs typical Double Word Programming Option Quadruple Word Programming Option COMMON FLASH INTERFACE MEMORY BLOCKS Parameter Blocks (Topor Bottom location) Main Blocks BLOCK LOCKINGAll blocks lockedat PowerUp Any combinationof blocks canbe locked
–WPfor Block Lock-Down SECURITY 128bit user Programmable OTP cells64bit unique device identifier One Parameter Block Permanently Lockable AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLESper
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M28W640CT: 8848h Bottom Device Code, M28W640CB: 8849h
M28W640CT, M28W640CB2/54
TABLEOF CONTENTS
SUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... .....5Figure 2.LogicDiagram.. ...... ....... ...... ....... ...... ....... ...... ...... .....5
Table1. Signal Names... ...... ....... ...... ....... ...... ....... ...... ...... .....5
Figure3. TSOP Connections..... ....... ...... ....... ...... ....... ...... ...... .....6
Figure4. TFBGA Connections (Top view through package). ...... ....... ...... ...... .....7
Figure 5.Block Addresses. ...... ....... ...... ....... ...... ....... ...... ...... .....8
Figure 6.SecurityBlock Memory Map..... ...... ....... ...... ....... ...... ...... .....8
SIGNAL DESCRIPTIONS .... ...... ....... ...... ....... ...... ....... ...... ...... .....9Address Inputs (A0-A21).. ...... ....... ...... ....... ...... ....... ...... ...... .....9
Data Input/Output (DQ0-DQ15)... ....... ...... ....... ...... ....... ...... ...... .....9
Chip Enable (E)... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Output Enable (G). ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Write Enable (W).. ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Write Protect (WP). ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Reset(RP). ...... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
VDD Supply Voltage (2.7Vto 3.6V) ....... ...... ....... ...... ....... ...... ...... .....9
VDDQ Supply Voltage (1.65Vto VDD). ..... ...... ....... ...... ....... ...... ...... .....9
VPP Program Supply Voltage .... ....... ...... ....... ...... ....... ...... ...... .....9
VSS Ground. ..... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
BUS OPERATIONS... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10Read. .... ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Write. .... ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Output Disable.... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Standby.. ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Automatic Standby. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Reset. ... ....... ...... ...... ....... ...... ....... ...... ....... ............ ....10
Read Electronic Signature Command ..... ...... ....... ...... ....... ...... ...... ....11
Table 2.Bus Operations.. ...... ....... ...... ....... ...... ....... ...... ...... ....10
COMMANDINTERFACE .... ...... ....... ...... ....... ...... ....... ...... ...... ....11Read Memory Array Command... ....... ...... ....... ...... ....... ...... ...... ....11
Read Status Register Command.. ....... ...... ....... ...... ....... ...... ...... ....11
Read Electronic Signature Command ..... ...... ....... ...... ....... ...... ...... ....11
Read CFIQueryCommand...... ....... ...... ....... ...... ....... ...... ...... ....11
Block Erase Command... ...... ....... ...... ....... ...... ....... ...... ...... ....11
Program Command ...... ...... ....... ...... ....... ...... ....... ...... ...... ....11
Double Word Program Command. ....... ...... ....... ...... ....... ...... ...... ....12
Clear Status Register Command.. ....... ...... ....... ...... ....... ...... ...... ....12
Program/Erase Suspend Command ...... ...... ....... ...... ....... ...... ...... ....12
Program/Erase Resume Command ...... ...... ....... ...... ....... ...... ...... ....12
Protection Register Program Command... ...... ....... ...... ....... ...... ...... ....13
Block Lock-Down Command ..... ....... ...... ....... ...... ....... ...... ...... ....13
3/54
M28W640CT, M28W640CBTable 3.Commands ..... ...... ....... ...... ....... ...... ....... ...... ...... ....14
Table 4.Read ElectronicSignature....... ...... ....... ...... ....... ...... ...... ....14
Table5. Read Block Lock Signature ...... ...... ....... ...... ....... ...... ...... ....15
Table 6.Read Protection Register and Lock Register ..... ...... ....... ...... ...... ....15
Table 7.Program,Erase Times and Program/Erase Endurance Cycles .... ...... ...... ....16
BLOCKLOCKING.... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....16Locked State ..... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....16
Unlocked State ... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....16
Lock-Down State.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....17
Readinga Block’s Lock Status... ....... ...... ....... ...... ....... ...... ...... ....16
Locking Operations During Erase Suspend ...... ....... ...... ....... ...... ...... ....17
Table 8.Block LockStatus ...... ....... ...... ....... ...... ....... ...... ...... ....17
Table 9.Protection Status. ...... ....... ...... ....... ...... ....... ...... ...... ....18
STATUS REGISTER.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....19Program/Erase Controller Status(Bit7)... ...... ....... ...... ....... ...... ...... ....19
Erase Suspend Status(Bit6) .... ....... ...... ....... ...... ....... ...... ...... ....19
Erase Status(Bit5) ...... ...... ....... ...... ....... ...... ....... ...... ...... ....19
Program Status(Bit4) .... ...... ....... ...... ....... ...... ....... ...... ...... ....19
VPP Status(Bit 3).. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....19
Program Suspend Status(Bit2).. ....... ...... ....... ...... ....... ...... ...... ....19
Block Protection Status(Bit 1).... ....... ...... ....... ...... ....... ...... ...... ....20
Reserved(Bit 0)... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....20
Table10. Status Register Bits.... ....... ...... ....... ...... ....... ...... ...... ....20
MAXIMUM RATING... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....21Table11. Absolute Maximum Ratings ..... ...... ....... ...... ....... ...... ...... ....21
andAC PARAMETERS.. ...... ....... ...... ....... ...... ....... ...... ...... ....22Table12. Operating andAC Measurement Conditions..... ...... ....... ...... ...... ....22
Figure 7.AC MeasurementI/O Waveform. ...... ....... ...... ....... ...... ...... ....22
Figure8.AC Measurement Load Circuit... ...... ....... ...... ....... ...... ...... ....22
Table13. Capacitance.... ...... ....... ...... ....... ...... ....... ...... ...... ....22
Table14.DC Characteristics..... ....... ...... ....... ...... ....... ...... ...... ....23
Figure 9.ReadAC Waveforms... ....... ...... ....... ...... ....... ...... ...... ....24
Table15. ReadAC Characteristics ....... ...... ....... ...... ....... ...... ...... ....24
Figure10. WriteAC Waveforms, Write Enable Controlled.. ...... ....... ...... ...... ....25
Table16. WriteAC Characteristics, Write Enable Controlled ...... ....... ...... ...... ....26
Figure11. WriteAC Waveforms, Chip Enable Controlled... ...... ....... ...... ...... ....27
Table17. WriteAC Characteristics, Chip Enable Controlled ...... ....... ...... ...... ....28
Figure12. Power-Up and ResetAC Waveforms... ....... ...... ....... ...... ...... ....29
Table18. Power-Up and ResetACCharacteristics ....... ...... ....... ...... ...... ....29
PACKAGE MECHANICAL... ...... ....... ...... ....... ...... ....... ...... ...... ....30
M28W640CT, M28W640CB4/54
Figure13. TSOP48-48 lead Plastic Thin Small Outline,12 x20mm, Package Outline .... ....30
Table19. TSOP48-48 lead Plastic Thin Small Outline,12x 20mm, Package Mechanical Data.30
Figure14. TFBGA48-8x6ball array, 0.75 mm pitch, Bottom View Package Outline ..... ....31
Table20. TFBGA48-8x6ball array, 0.75 mm pitch, Package Mechanical Data... ...... ....31
Figure15. TFBGA48 Daisy Chain- Package Connections (Top view through package) .... ....32
Figure16. TFBGA48 Daisy Chain- PCB Connections proposal (Top view through package) ....32
PART NUMBERING.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....33Table21. Ordering Information Scheme... ...... ....... ...... ....... ...... ...... ....33
Table22. DaisyChain Ordering Scheme.. ...... ....... ...... ....... ...... ...... ....33
REVISION HISTORY.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....34Table23. Document Revision History ..... ...... ....... ...... ....... ...... ...... ....34
APPENDIXA. BLOCK ADDRESS TABLES.. ...... ....... ...... ....... ...... ...... ....35Table24. Top Boot Block Addresses, M28W640CT ....... ...... ....... ...... ...... ....35
Table25. Bottom Boot Block Addresses, M28W640CB .... ...... ....... ...... ...... ....37
APPENDIXB. COMMONFLASH INTERFACE (CFI). ....... ...... ....... ...... ...... ....39Table26. Query Structure Overview ...... ...... ....... ...... ....... ...... ...... ....39
Table27. CFI Query Identification String.. ...... ....... ...... ....... ...... ...... ....39
Table28. CFIQuerySystem Interface Information. ....... ...... ....... ...... ...... ....40
Table29. Device Geometry Definition ..... ...... ....... ...... ....... ...... ...... ....41
Table30. Primary Algorithm-Specific Extended Query Table ...... ....... ...... ...... ....42
Table31. Security Code Area .... ....... ...... ....... ...... ....... ...... ...... ....43
APPENDIXC. FLOWCHARTS AND PSEUDO CODES....... ...... ....... ...... ...... ....44Figure17. Program Flowchart and Pseudo Code.. ....... ...... ....... ...... ...... ....44
Figure18. Double Word Program Flowchart and Pseudo Code .... ....... ...... ...... ....45
Figure19. Quadruple Word Program Flowchart and Pseudo Code. ....... ...... ...... ....46
Figure20. Program Suspend& Resume Flowchart and Pseudo Code ..... ...... ...... ....47
Figure21. Erase Flowchart and Pseudo Code .... ....... ...... ....... ...... ...... ....48
Figure22. Erase Suspend& Resume Flowchart and Pseudo Code. ....... ...... ...... ....49
Figure23. Locking Operations Flowchart and Pseudo Code ...... ....... ...... ...... ....50
APPENDIXD. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE... ....52Table32. Write State Machine Current/Next, sheet1of 2... ...... ....... ...... ...... ....52
Table33. Write State Machine Current/Next, sheet2of 2... ...... ....... ...... ...... ....53
5/54
M28W640CT, M28W640CB
SUMMARY DESCRIPTIONThe M28W640Cisa64 Mbit(4 Mbitx16) non-vol-
atileFlash memory that canbeerasedelectricallythe block level and programmed in-systemona
Word-by-Word basis. These operations canbe
performed usinga singlelow voltage (2.7to 3.6V)
supply. VDDQ allowsto drivetheI/Opin downto
1.65V.An optional 12V VPP power supplyis pro-
videdto speedup customer programming.
The device featuresan asymmetrical blockedar-
chitecture. The M28W640C hasan arrayof 135
blocks:8 Parameter Blocksof4 KWord and 127
Main Blocksof32 KWord. M28W640CT hasthe
Parameter Blocksatthetopofthe memory ad-
dress space while the M28W640CB locatesthe
Parameter Blocks starting fromthe bottom. The
memory mapsare shownin Figure5, Block Ad-
dresses.
The M28W640C featuresan instant, individual
block locking scheme that allows any blocktobe
lockedor unlocked withno latency, enablingin-
stant code and data protection.All blocks have
three levelsof protection. Theycanbe locked and
locked-down individually preventing any acciden-
tal programmingor erasure. Thereisan additional
hardware protection against program and erase.
When VPP ≤ VPPLKall blocksare protected against
programor erase.All blocksare lockedat Power
Up.
Each block canbe erased separately. Erase can suspendedin orderto perform either reador
programin any other block and then resumed.
Program canbe suspendedto read datain any
other block and then resumed. Each block canbe
programmed and erased over 100,000 cycles.
The device includesa 192bit Protection Register
anda Security Blockto increasethe protectionof system design. The Protection Registeris divid- intoa64bit segment anda 128bit segment.
The64bit segment containsa unique device num-
ber writtenby ST, whilethe second oneis one-
time-programmableby the user. The user pro-
grammable segment canbe permanently protect-
ed. The Security Block, parameter block0, canbe
permanently protectedby the user. Figure6,
showsthe Security Block Memory Map.
Program and Erase commandsare writtentothe
Command Interfaceof the memory.An on-chip
Program/Erase Controller takes careofthe tim-
ings necessaryfor program and erase operations.
The endofa programor erase operation canbe
detected and any error conditions identified. The
commandset requiredto controlthe memoryis
consistent with JEDEC standards.
M28W640CT, M28W640CB6/54
7/54
M28W640CT, M28W640CB
M28W640CT, M28W640CB8/54
9/54
M28W640CT, M28W640CB
SIGNAL DESCRIPTIONSSee Figure2 Logic Diagram and Table 1,Signal
Names,fora brief overviewofthe signals connect-tothis device.
Address Inputs (A0-A21). The Address Inputs
selectthe cellsinthe memory arrayto access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sentto the
Command Interfaceofthe internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data storedat the selected address
duringa Bus Read operationor inputsa command thedatatobeprogrammedduringa WriteBus
operation.
Chip Enable (E). The Chip Enable input acti-
vatesthe memory control logic, input buffers,de-
codersand sense amplifiers. When Chip Enableis VILand ResetisatVIHthe deviceisin active
mode. When Chip EnableisatVIHthe memoryis
deselected,the outputsare high impedance and
the power consumptionis reducedtothe stand-by
level.
Output Enable (G). The Output Enable controls
data outputs duringthe Bus Read operationofthe
memory.
WriteEnable(W). The Write Enable controlsthe
Bus Write operationofthe memory’s Command
Interface. The data and address inputsare latched therisingedgeof ChipEnable,E, orWriteEn-
able,W, whichever occurs first.
Write Protect (WP). Write Protectisan input
that givesan additional hardware protectionfor
each block. When Write ProtectisatVIL,the Lock-
Downis enabled andthe protection statusofthe
block cannotbe changed. When Write Protectisat
VIH,the Lock-Downis disabled andthe block can lockedor unlocked. (referto Table6, Read Pro-
tection Register and Protection Register Lock).
Reset (RP). The Reset input providesa hard-
ware resetofthe memory. When ResetisatVIL,
the memoryisin reset mode:the outputsare high
impedance andthe current consumptionis mini-
mized. After Resetall blocks arein the Locked
state. When Resetisat VIH,the deviceisin normal
operation. Exiting reset modethe device enters
read array mode,buta negative transitionof Chip
Enableora changeofthe addressis requiredto
ensure valid data outputs.
VDD Supply Voltage (2.7Vto 3.6V). VDD pro-
videsthe power supplytothe internal coreofthe
memory device.Itisthe main power supplyforall
operations (Read, Program and Erase).
VDDQ Supply Voltage (1.65Vto VDD). VDDQ
providesthe power supplytotheI/O pins anden-
ablesall Outputstobe powered independently
from VDD.VDDQ canbetiedto VDDor can usea
separate supply.
VPP Program Supply Voltage. VPPis botha
control input anda power supply pin. The two
functions are selectedbythe voltage range ap-
pliedtothe pin. The Supply Voltage VDD andthe
Program Supply Voltage VPP canbe appliedin
any order. VPPis keptinalow voltage range (0Vto 3.6V)
VPPis seenasa control input.Inthis casea volt-
age lower than VPPLK givesan absolute protection
against programor erase, while VPP >VPP1en-
ables these functions (see Table14,DC Charac-
teristics for the relevant values). VPPis only
sampledatthe beginningofa programor erase;a
changeinits value afterthe operation has started
doesnot have any effecton Programor Erase,
howeverfor Doubleor Quadruple Word Program
the resultsare uncertain. VPPisinthe range 11.4Vto 12.6Vit actsasa
power supply pin.In this condition VPP mustbe
stable untilthe Program/Erase algorithmis com-
pleted (see Table16 and 17).
VSS Ground. VSSisthe referenceforall voltage
measurements.
Note: Each deviceina system should have
VDD,VDDQ and VPP decoupled witha 0.1μFca-
pacitor closetothe pin. See Figure8,AC Mea-
surement Load Circuit. The PCB trace widths
shouldbe sufficientto carry the required VPP
program and erase currents.
M28W640CT, M28W640CB10/54
BUS OPERATIONSTherearesix standard bus operations that control
the device. Theseare Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and Re-
set. See Table2, Bus Operations,fora summary.
Typically glitchesof less than 5nson Chip Enable Write Enableare ignoredbythe memory anddo
not affect bus operations.
Read. Read Bus operationsare usedto output
the contentsofthe Memory Array,the Electronic
Signature,the Status Register andthe Common
Flash Interface. Both Chip Enable and OutputEn-
ablemust beatVILin orderto performa readop-
eration. The Chip Enable input shouldbe usedto
enablethe device. Output Enable shouldbe used gate data ontothe output. The data readde-
pendson the previous command writtentothe
memory (see Command Interface section). See
Figure9, Read ModeAC Waveforms, and Table
15, ReadAC Characteristics,for detailsof when
the output becomes valid.
Read modeisthe default stateofthe device when
exiting Resetor after power-up.
Write. Bus Write operations write Commandsto
the memoryor latch Input Datatobe programmed. write operationis initiated when Chip Enable
and Write EnableareatVIL with Output Enableat
VIH. Commands, Input Data and Addresses are
latchedonthe rising edgeof Write Enableor Chip
Enable, whichever occurs first.
See Figures10 and11, WriteAC Waveforms, and
Tables16 and17, WriteAC Characteristics,for
detailsofthe timing requirements.
Output Disable. The data outputs are highim-
pedance whenthe Output Enableisat VIH.
Standby. Standby disables mostofthe internal
circuitry allowinga substantial reductionofthe cur-
rent consumption. The memoryisin stand-by
when Chip Enableisat VIH and thedeviceisin
read mode. The power consumptionis reducedto
the stand-by level andthe outputsaresetto high
impedance, independently fromthe Output Enable Write Enable inputs.If Chip Enable switchesto
VIH duringa programor erase operation,thede-
vice enters Standby mode when finished.
Automatic Standby. Automatic Standby pro-
videsalow power consumption state during Read
mode. Followinga read operation,the deviceen-
ters Automatic Standby after 150nsof bus inactiv-
ity evenif Chip Enableis Low, VIL, andthe supply
currentis reducedto IDD1. The data Inputs/Out-
putswillstill output dataifa bus Read operationis progress.
Reset. During Reset mode when Output Enable Low, VIL,the memoryis deselected andthe out-
putsare high impedance. The memoryisin Reset
mode when Resetisat VIL. The power consump-
tionis reducedtothe Standby level, independently
fromthe Chip Enable, Output Enableor WriteEn-
able inputs.If Resetis pulledto VSS duringa Pro-
gramor Erase, this operationis aborted andthe
memory contentisno longer valid.
Table2. Bus OperationsNote:X= VILor VIH,VPPH =12V±5%.
11/54
M28W640CT, M28W640CB
COMMAND INTERFACEAll Bus Write operationstothe memoryare inter-
pretedby the Command Interface. Commands
consistof oneor more sequential Bus Write oper-
ations.An internal Program/Erase Controller han-
dlesall timings and verifiesthe correct executionthe Program and Erase commands. The Pro-
gram/Erase Controller providesa Status Register
whose output maybe readat any time during,to
monitorthe progressofthe operation,orthe Pro-
gram/Erase states. See Appendix 22, Table32,
Write State Machine Current/Next,fora summarythe Command Interface.
The Command Interfaceis resetto Read mode
when poweris first applied, when exiting from Re-
setor whenever VDDis lower than VLKO.Com-
mand sequences mustbe followed exactly. Any
invalid combinationof commandswill resetthede-
viceto Read mode. Referto Table3, Commands, conjunction withthe text descriptions below.
Read Memory Array CommandTheReadcommand returns the memorytoits
Read mode. One Bus Write cycleis requiredtois-
suethe Read Memory Array command and return
the memoryto Read mode. Subsequent readop-
erationswill readthe addressed location and out-
put the data. Whena device Reset occurs,the
memory defaultsto Read mode.
Read Status Register CommandThe Status Register indicates whena programor
erase operationis complete and the successor
failureofthe operation itself. Issuea Read Status
Register commandto readthe Status Register’s
contents. Subsequent Bus Read operations read
the Status Registerat any address, until another
commandis issued. See Table10, Status Register
Bits,for detailsonthe definitionsofthe bits.
The Read Status Register command maybeis-
suedat any time, even duringa Program/Erase
operation. Any Read attempt duringa Program/
Erase operationwill automatically outputthe con-
tentofthe Status Register.
Read Electronic Signature CommandThe Read Electronic Signature command reads
the Manufacturer and Device Codes andthe Block
Locking Status,orthe Protection Register.
The Read Electronic Signature command consists one write cycle,a subsequent readwill output
the Manufacturer Code, the Device Code, the
Block Lock and Lock-Down Status,orthe Protec-
tion and Lock Register. See Tables4,5 and6for
the valid address.
Read CFI Query CommandThe Read Query Commandis usedto read data
fromthe Common Flash Interface (CFI) Memory
Area, allowing programming equipmentor appli-
cationsto automatically match their interfaceto
the characteristicsofthe device. One Bus Write
cycleis requiredto issuethe Read Query Com-
mand. Oncethe commandis issued subsequent
Bus Read operations read from the Common
Flash Interface Memory Area. See AppendixB,
Common Flash Interface, Tables26,27,28,29, and31for detailsonthe information containedthe Common Flash Interface memory area.
Block Erase CommandTheBlock Erase command can beusedtoerase block.It setsallthebits withinthe selected block’1’.All previous datainthe blockis lost.Ifthe
blockis protected then the Erase operationwill
abort,the datainthe blockwillnotbe changed and
the Status Registerwill outputthe error.
Two Bus Write cycles are requiredto issuethe
command. The firstbus cycle setsupthe Erase command. The second latchesthe block addressinthe
internal state machine and startsthe Program/
Erase Controller.the second bus cycleisnot Write Erase Confirm
(D0h), Status Register bitsb4 andb5areset and
the command aborts.
Erase abortsif Reset turnstoVIL.As data integrity
cannotbe guaranteed whenthe Erase operationis
aborted,the block mustbe erased again.
During Erase operationsthe memorywill accept
the Read Status Register command andthe Pro-
gram/Erase Suspend command,all other com-
mandswillbe ignored. Typical Erase times are
givenin Table7, Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
See AppendixC, Figure21, Erase Flowchart and
Pseudo Code,fora suggested flowchartfor using
the Erase command.
Program CommandThe memory array canbe programmed word-by-
word. Two bus write cyclesare requiredto issue
the Program Command. The first bus cycle setsupthe Program
command. The secondlatchesthe Address andthe Datato written and startsthe Program/Erase
Controller.
During Program operations the memory willac-
ceptthe Read Status Register command andthe
Program/Erase Suspend command. Typical Pro-
gram timesare givenin Table7, Program, Erase
Times and Program/Erase Endurance Cycles.
Programming abortsif Reset goesto VIL.As data
integrity cannotbe guaranteed whenthe program
operationis aborted, the block containing the
M28W640CT, M28W640CB12/54
memory location mustbe erased and repro-
grammed.
See AppendixC, Figure17, Program Flowchart
and Pseudo Code,forthe flowchartfor usingthe
Program command.
Double Word Program CommandThis featureis offeredto improvethe programming
throughput, writinga pageof two adjacent words parallel.The two words must differ onlyforthe
addressA0. Programming shouldnotbe attempt- when VPPisnotat VPPH. The command canbe
executedif VPPis below VPPHbutthe resultisnot
guaranteed.
Three bus write cyclesare necessaryto issuethe
Double Word Program command. The first bus cycle setsupthe Double Word
Program Command. The second bus cycle latchesthe Address and
the Dataofthe first wordtobe written. The third bus cycle latchesthe Address andthe
Dataofthe second wordtobe written and starts
the Program/Erase Controller.
Read operations outputthe Status Register con-
tent afterthe programming has started. Program-
ming abortsif Reset goesto VIL.As data integrity
cannotbe guaranteed whenthe program opera-
tionis aborted,the block containingthe memory
location mustbe erased and reprogrammed.
See AppendixC, Figure18, Double Word Pro-
gram Flowchart and Pseudo Code,forthe flow-
chart for using the Double Word Program
command.
Quadruple Word Program CommandThis featureis offeredto improvethe programming
throughput, writinga pageof four adjacent words parallel.The four words must differ onlyforthe
addressesA0 andA1. Programming shouldnotbe
attempted when VPPis notatVPPH. The command
canbe executedif VPPis below VPPHbutthe resultnot guaranteed.
Five bus write cyclesare necessaryto issuethe
Quadruple Word Program command. The first bus cycle setsupthe Double Word
Program Command. The second bus cycle latchesthe Address and
the Dataofthe first wordtobe written. The third bus cycle latchesthe Address andthe
Dataofthe second wordtobe written. The fourth bus cycle latchesthe Address and
theDataofthe thirdword tobewritten. The fifth bus cycle latchesthe Address andthe
Dataofthe fourth wordtobe written and starts
the Program/Erase Controller.
Read operations outputthe Status Register con-
tent afterthe programming has started. Program-
ming abortsif Reset goesto VIL.As data integrity
cannotbe guaranteed whenthe program opera-
tionis aborted,the block containingthe memory
location mustbe erased and reprogrammed.
See AppendixC, Figure19, Quadruple Word Pro-
gram Flowchart and Pseudo Code,forthe flow-
chartfor using the Quadruple Word Program
command.
Clear Status Register CommandThe Clear Status Register command canbe used resetbits1,3,4 and5inthe Status Registerto
‘0’. One bus write cycleis requiredto issuethe
Clear Status Register command.
Thebitsinthe Status Registerdonot automatical- returnto‘0’ whena new Programor Erase com-
mandis issued. The error bitsin the Status
Register shouldbe cleared before attemptinga
new Programor Erase command.
Program/Erase Suspend CommandThe Program/Erase Suspend commandis usedto
pausea Programor Erase operation. One bus
write cycleis requiredto issuethe Program/Erase
command and pausethe Program/Erase control-
ler.
During Program/Erase Suspendthe CommandIn-
terface will accept the Program/Erase Resume,
Read Array, Read Status Register, Read Electron- Signature and Read CFI Query commands.Ad-
ditionally,ifthe suspend operation was Erase then
the Program, Double Word Program, Quadruple
Word Program, Block Lock, Block Lock-Downor
Protection Program commands will alsobe ac-
cepted. The block being erased maybe protected issuingthe Block Protect, Block Lockor Protec-
tion Program commands. When the Program/
Erase Resume commandis issuedthe operation
will complete. Onlythe blocksnot being erased
maybe reador programmed correctly.
Duringa Program/Erase Suspend,the device can placedina pseudo-standby modeby taking
Chip Enableto VIH. Program/Eraseis abortedif
Reset turnsto VIL.
See AppendixC, Figure20, Program Suspend&
Resume Flowchart and Pseudo Code, and Figure
22, Erase Suspend& Resume Flowchart and
Pseudo Codefor flowchartsfor usingthe Program/
Erase Suspend command.
Program/Erase Resume CommandThe Program/Erase Resume command canbe
usedto restartthe Program/Erase Controller after Program/Erase Suspend operation has paused
it. One Bus Write cycleis requiredto issuethe
command. Oncethe commandis issued subse-
13/54
M28W640CT, M28W640CBquent Bus Read operations readthe Status Reg-
ister.
See AppendixC, Figure20, Program Suspend&
Resume Flowchart and Pseudo Code, and Figure
22, Erase Suspend& Resume Flowchart and
Pseudo Codefor flowchartsfor usingthe Program/
Erase Resume command.
Protection Register Program CommandThe Protection Register Program commandis
usedto Programthe 128bit user One-Time-Pro-
grammable (OTP) segmentofthe Protection Reg-
ister. The segmentis programmed16 bitsata
time. When shippedallbitsinthe segmentareset‘1’. The user can only programthe bitsto‘0’.
Two write cyclesare requiredto issuethe Protec-
tion Register Program command. The first bus cycle setsupthe Protection
Register Program command. The second latchesthe Addressandthe Datato writtentothe Protection Register and starts
the Program/Erase Controller.
Read operations outputthe Status Register con-
tent afterthe programming has started.
The segmentcanbe protectedby programmingbitofthe Protection Lock Register.Bit1ofthe Pro-
tection Lock Register protectsbit2ofthe Protec-
tion Lock Register. Programmingbit2of the
Protection Lock Registerwill resultina permanent
protectionofthe Security Block (see Figure6,Se-
curity Block Memory Map). Attemptingto program previously protected Protection Registerwillre-
sultina Status Register error. The protectionof
the Protection Register and/orthe Security Blocknot reversible.
The Protection Register Program cannotbe sus-
pended.
Block Lock CommandThe Block Lock commandis usedto locka block
and prevent Programor Erase operations from
changingthe datainit.All blocksare lockedat
power-upor reset.
Two Bus Write cycles are requiredto issuethe
Block Lock command. The first bus cycle setsupthe Block Lock
command. The second Bus Write cycle latchesthe block
address.
The lock status canbe monitoredfor each block
using the Read Electronic Signature command.
Table.9 showsthe protection status after issuing Block Lock command.
The Block Lock bitsare volatile, onceset theyre-
mainset untila hardware resetor power-down/
power-up. They are clearedbya Blocks Unlock
command. Refertothe section, Block Locking,for detailed explanation.
Block Unlock CommandThe Blocks Unlock commandis usedto unlocka
block, allowing the blocktobe programmedor
erased. Two Bus Write cyclesare requiredtois-
suethe Blocks Unlock command. The first bus cycle setsupthe Block Unlock
command. The second Bus Write cycle latchesthe block
address.
The lock status canbe monitoredfor each block
using the Read Electronic Signature command.
Table.9 showsthe protection status after issuing Block Unlock command. Refertothe section,
Block Locking,fora detailed explanation.
Block Lock-Down Command locked block cannotbe Programmedor Erased, haveits protection status changed when WPis
low, VIL.When WPis high, VIH,the Lock-Down
functionis disabled andthe locked blocks canbe
individually unlockedbythe Block Unlock com-
mand.
Two Bus Write cycles are requiredto issuethe
Block Lock-Down command. The first bus cycle setsupthe Block Lock
command. The second Bus Write cycle latchesthe block
address.
The lock status canbe monitoredfor each block
using the Read Electronic Signature command.
Locked-Down blocks reverttothe locked (andnot
locked-down) state when the deviceis reseton
power-down. Table.9 showsthe protection status
after issuinga Block Lock-Down command. Referthe section, Block Locking,fora detailed expla-
nation.
M28W640CT, M28W640CB14/54
Table3. CommandsNote:1.X= Don't Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufactureand Device Code),
QA=Query Address, QD=Query Data,BA=Block Address, PA=Program Address, PD=ProgramData, PRA=Protection RegisterAd-
dress, PRD=Protection Register Data.The signature addressesare listedin Tables4,5and6. Program Addresses1and2mustbe consecutive Addresses differingonlyforA0. Program Addresses1,2,3and4mustbe consecutive Addresses differingonlyforA0andA1.
Table4. Read Electronic SignatureNote: RP =VIH.
15/54
M28W640CT, M28W640CB
Table5. Read Block Lock SignatureNote:1.A Locked-Down Blockcanbe locked "DQ0=1"or unlocked "DQ0=0";see Block Locking section.
Table6. Read Protection Register and Lock Register
M28W640CT, M28W640CB16/54
Table7. Program, Erase Times and Program/Erase Endurance CyclesNote:1. Typicaltimeto programaMainor Parameter Block usingthe Double Word Programandthe Quadruple Word Program commands
respectively.
BLOCK LOCKINGThe M28W640C featuresan instant, individual
block locking scheme that allows any blocktobe
lockedorunlockedwithnolatency. This locking
scheme has three levelsof protection. Lock/Unlock-this first level allows software-
only controlof block locking. Lock-Down- this second level requires
hardware interaction before locking canbe
changed. VPP ≤ VPPLK-the third level offersa complete
hardware protection against program and eraseall blocks.
Theprotectionstatusof eachblock canbesetto
Locked, Unlocked, and Lock-Down. Table9,de-
finesallof the possible protection states (WP,
DQ1, DQ0), and AppendixC, Figure23, showsa
flowchartforthe locking operations.
Readinga Block’sLockStatusThe lock statusof every block canbe readinthe
Read Electronic Signature modeofthe device.To
enter this mode write 90htothe device. Subse-
quent readsatthe address specifiedin Table5,
will outputthe protection statusof that block. The
lock statusis representedby DQ0 and DQ1. DQ0
indicatesthe Block Lock/Unlock status andissetthe Lock command and clearedbythe Unlock
command.Itis also automaticallyset when enter-
ing Lock-Down. DQ1 indicatesthe Lock-Down sta-
tus andis setby the Lock-Down command.It
cannotbe clearedby software, onlybya hardware
resetor power-down.
The following sections explainthe operationofthe
locking system.
Locked StateThe default statusofall blockson power-uporaf-
tera hardware resetis Locked (states (0,0,1)or
(1,0,1)). Locked blocks are fully protected from
any programor erase. Any programor erase oper-
ations attemptedona locked blockwill returnan
errorin the Status Register. The Statusofa
Locked block canbe changedto Unlockedor
Lock-Down usingthe appropriate software com-
mands.An Unlocked block canbe Lockedby issu-
ingthe Lock command.
Unlocked StateUnlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
canbe programmedor erased.All unlocked
blocks returntothe Locked state aftera hardware
resetor whenthe deviceis powered-down. The
statusofan unlocked block canbe changedto
Lockedor Locked-Down using the appropriate
software commands.A locked block canbe un-
lockedby issuingthe Unlock command.
17/54
M28W640CT, M28W640CB
Lock-Down StateBlocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations(as
for Locked blocks)but their protection status can-
notbe changed using software commands alone. Lockedor Unlocked block canbe Locked-Down issuing the Lock-Down command. Locked-
Down blocks reverttothe Locked state whenthe
deviceis resetor powered-down.
The Lock-Down functionis dependentonthe WP
input pin. When WP=0 (VIL), the blocksin the
Lock-Down state (0,1,x) are protected from pro-
gram, erase and protection status changes. When
WP=1 (VIH)the Lock-Down functionis disabled
(1,1,1) and Locked-Down blocks canbe individu-
ally unlockedtothe (1,1,0) stateby issuingthe
software command, where they canbe erased and
programmed. These blocks can thenbe relocked
(1,1,1) and unlocked (1,1,0)as desired while WP
remains high. When WPislow, blocks that were
previously Locked-Down returntothe Lock-Down
state regardlessof any changes made
while WP was high. Device resetor power-down
resetsall blocks, including thosein Lock-Down,to
the Locked state.
Locking Operations During Erase SuspendChangesto block lock status canbe performed
duringan erase suspendby using the standard
locking command sequencesto unlock, lockor
lock-downa block. Thisis usefulinthe case when
another block needstobe updated whilean erase
operationisin progress. change block locking duringan erase opera-
tion, first writethe Erase Suspend command, then
checkthe status register untilit indicates thatthe
erase operation has been suspended. Next write
the desired Lock command sequencetoa block
andthe lock statuswillbe changed. After complet-
ing any desired lock, read,or program operations,
resumethe erase operation with the Erase Re-
sume command.a blockis lockedor locked-down duringan erase
suspendofthe same block,the locking statusbits
willbe changed immediately,but whenthe erase resumed,the erase operationwill complete.
Locking operations cannotbe performed duringa
program suspend. Referto AppendixD, Com-
mand Interface and Program/Erase Controller
State,for detailed informationon which com-
mandsare valid during erase suspend.
Table8. Block Lock Status
M28W640CT, M28W640CB18/54
Table9. Protection StatusNote:1.Thelock statusis definedby thewrite protectpinandbyDQ1(‘1’fora locked-down block)and DQ0(‘1’fora lockedblock)asreadthe Read Electronic Signature commandwithA1=VIH andA0=VIL.All blocksare lockedat power-up,sothe default configurationis001or101 accordingtoWP status.AWP transitiontoVIHona locked blockwill restorethe previousDQ0 value, givinga111or110.
19/54
M28W640CT, M28W640CB
STATUS REGISTERThe Status Register provides informationonthe
currentor previous Programor Erase operation.
The variousbits convey information and errorson
the operation.To read the Status register the
Read Status Register command canbe issued,re-
ferto Read Status Register Command section.To
outputthe contents,the Status Registeris latchedthe falling edgeofthe Chip Enableor Output
Enable signals, and canbe read until Chip Enable Output Enable returnsto VIH. Either Chip En-
ableor Output Enable mustbe toggledto update
the latched data.
Bus Read operations from any address always
read the Status Register during Program and
Erase operations.
Thebitsinthe Status Registerare summarizedin
Table10, Status Register Bits. Referto Table10 conjunction withthe followingtext descriptions.
Program/Erase Controller Status(Bit7). The Pro-
gram/Erase Controller Statusbit indicates whether
the Program/Erase Controlleris activeor inactive.
Whenthe Program/Erase Controller Statusbitis
Low (setto ‘0’),the Program/Erase Controlleris
active; whenthebitis High (setto ‘1’),the Pro-
gram/Erase Controlleris inactive, andthe device readyto processa new command.
The Program/Erase Controller Statusis Lowim-
mediately aftera Program/Erase Suspend com-
mandis issued untilthe Program/Erase Controller
pauses. Afterthe Program/Erase Controller paus-thebitis High.
During Program, Erase, operationsthe Program/
EraseControllerStatusbit canbepolledtofindthe
endofthe operation. Otherbitsinthe Status Reg-
ister shouldnotbe tested untilthe Program/Erase
Controller completesthe operation andthebitis
High.
Afterthe Program/Erase Controller completesits
operationthe Erase Status, Program Status, VPP
Status and Block Lock Statusbits shouldbe tested
for errors.
Erase Suspend Status (Bit6). The Erase Sus-
pend Statusbit indicates thatan Erase operation
has been suspendedoris goingtobe suspended.
Whenthe Erase Suspend Statusbitis High (setto
‘1’),a Program/Erase Suspend command has
been issued andthe memoryis waitingfora Pro-
gram/Erase Resume command.
The Erase Suspend Status should onlybe consid-
ered valid whenthe Program/Erase Controller Sta-
tusbitis High (Program/Erase Controller inactive).
Bit7isset within 30μsofthe Program/Erase Sus-
pend command being issued thereforethe memo- may still complete the operation rather than
enteringthe Suspend mode.
Whena Program/Erase Resume commandisis-
suedthe Erase Suspend Statusbit returns Low.
Erase Status (Bit5). The Erase Statusbitcanbe
usedto identifyifthe memory has failedto verify
that the block has erased correctly. When the
Erase Statusbitis High (setto ‘1’),the Program/
Erase Controller has appliedthe maximum num-
berof pulsestothe block and still failedto verify
thatthe blockhas erased correctly. The Erase Sta-
tusbit shouldbe read oncethe Program/Erase
Controller Statusbitis High (Program/Erase Con-
troller inactive).
Onceset High,the Erase Statusbit can onlybere-
set Lowbya Clear Status Register commandora
hardware reset.Ifset Highit shouldbe resetbe-
forea new Programor Erase commandis issued,
otherwisethe new commandwill appearto fail.
Program Status (Bit4). The Program Statusbit usedto identifya Program failure. Whenthe
Program Statusbitis High (setto ‘1’), the Pro-
gram/Erase Controller has appliedthe maximum
numberof pulsestothe byte andstill failedto ver-
ify thatithas programmed correctly. The Program
Statusbit shouldbe read oncethe Program/Erase
Controller Statusbitis High (Program/Erase Con-
troller inactive).
Onceset High,the Program Statusbit can onlybe
reset Lowbya Clear Status Register commandor hardware reset.Ifset Highit shouldbe resetbe-
forea new commandis issued, otherwisethe new
commandwill appeartofail.
VPP Status (Bit3). The VPP Statusbit canbe
usedto identifyan invalid voltageonthe VPPpin
during Program and Erase operations. The VPP
pinis only sampledatthe beginningofa Program Erase operation. Indeterminate results canoc-
curif VPP becomes invalid duringan operation.
Whenthe VPP Statusbitis Low (setto‘0’),the volt-
ageonthe VPPpin was sampledata valid voltage;
whenthe VPP Statusbitis High (setto‘1’),the VPP
pin hasa voltage thatis belowthe VPP Lockout
Voltage, VPPLK,the memoryis protected and Pro-
gram and Erase operations cannotbe performed.
Onceset High,the VPP Statusbitcan onlybe reset
Lowbya Clear Status Register commandora
hardware reset.Ifset Highit shouldbe resetbe-
forea new Programor Erase commandis issued,
otherwisethe new commandwill appearto fail.
Program Suspend Status (Bit2). The Program
Suspend Statusbit indicates thata Program oper-
ation has been suspended. When the Program
Suspend Statusbitis High (setto ‘1’),a Program/
Erase Suspend command has been issued and
the memoryis waitingfora Program/Erase Re-
sume command. The Program Suspend Status
should onlybe considered valid when the Pro-
M28W640CT, M28W640CB20/54
gram/Erase Controller Statusbitis High (Program/
Erase Controller inactive).Bit2isset within5μsof
the Program/Erase Suspend command beingis-
sued thereforethe memory maystill completethe
operation rather than enteringthe Suspend mode.
Whena Program/Erase Resume commandisis-
suedthe Program Suspend Statusbit returns Low.
Block Protection Status (Bit1). The Block Pro-
tectionStatusbit canbeusedtoidentifyifa Pro-
gramor Erase operation has triedto modifythe
contentsofa locked block.
Whenthe Block Protection Statusbitis High (set ‘1’),a Programor Erase operation has beenat-
temptedona locked block.
Onceset High,the Block Protection Statusbitcan
onlybe reset Lowbya Clear Status Register com-
mandora hardware reset.Ifset Highit shouldbe
reset beforea new commandis issued, otherwise
the new command will appear to fail.
Reserved (Bit0).Bit0ofthe Status Registeris
reserved.Its value mustbe masked.
Note: Referto AppendixC, Flowcharts and
Pseudo Codes,for usingthe Status Register.
Table10. Status Register BitsNote: Logiclevel'1'is High,'0'isLow.
21/54
M28W640CT, M28W640CB
MAXIMUM RATINGStressingthe deviceabove therating listedinthe
Absolute Maximum Ratings table may cause per-
manent damagetothe device. These are stress
ratings only and operationofthe deviceat theseor
any other conditions above those indicatedinthe
Operating sectionsof this specificationisnotim-
plied. Exposureto Absolute Maximum Rating con-
ditionsfor extended periods may affect device
reliability. Refer alsoto the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table11. Absolute Maximum RatingsNote:1. Dependson range.
M28W640CT, M28W640CB22/54
ANDAC PARAMETERSThis section summarizesthe operating and mea-
surement conditions, andtheDC andAC charac-
teristicsofthe device. The parametersintheDC
andAC characteristics Tables that follow,arede-
rived from tests performed under the Measure-
ment Conditions summarizedin Table 12,
Operating andAC Measurement Conditions. De-
signers should check thatthe operating conditions their circuit matchthe measurement conditions
when relyingonthe quoted parameters.
Table12. Operating andAC Measurement Conditions
Table13. CapacitanceNote: Sampledonly,not 100% tested.
23/54
M28W640CT, M28W640CB
Table14.DC Characteristics
M28W640CT, M28W640CB24/54
25/54
M28W640CT, M28W640CB
M28W640CT, M28W640CB26/54
Table16. WriteAC Characteristics, Write Enable ControlledNote:1. Sampledonly,not 100% tested. ApplicableifVPPis seenasalogic input(VPP <3.6V).
27/54
M28W640CT, M28W640CB
