M28W640FSU70ZA6 ,32Mbit (2Mb x16) and 64Mbit (4Mb x16) 3V Supply, Uniform Block, Secure Flash MemoriesFEATURES . . . . 11COMMAND INTERFACE . . . 12Read Memory Array Command . . 12Re ..
M28W640HCB70N6E , 64 Mbit (4 Mb x 16, boot block) 3 V supply Flash memory
M28W640HCB70N6F , 64 Mbit (4 Mb x 16, boot block) 3 V supply Flash memory
M28W800BT100N6T ,8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYTABLE OF CONTENTSSUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... ..
M28W800CB90N6 ,8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYM28W800CTM28W800CB8 Mbit (512Kb x16, Boot Block)3V Supply Flash Memory
M28W800CT70N6 ,8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYTABLE OF CONTENTSSUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... ..
M500000010 , 64 Megabit (4 M x 16-Bit) and 32 Megabit (2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories, and 8 Mbit
M50224FP , 1.5 Channel Motor Driver·with DC/DC Control
M50427FP , CD PLAYER DIGITAL SIGNAL PROCESSOR
M50427FP , CD PLAYER DIGITAL SIGNAL PROCESSOR
M50436-689SP , SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
M50734SP-10 , 8-BIT CMOS MICROCOMPUTER
M28W320FSU70ZA6-M28W640FSU70ZA6
32Mbit (2Mb x16) and 64Mbit (4Mb x16) 3V Supply, Uniform Block, Secure Flash Memories
1/49May 2005
M28W320FSU
M28W640FSU32Mbit (2Mb x16) and 64Mbit (4Mb x16)
3V Supply, Uniform Block, Secure Flash Memories
FEATURES SUMMARY SUPPLY VOLTAGE
–VDD = 2.7V to 3.6V Core Power Supply
–VDDQ= 2.7V to 3.6V for Input/Output
–VPP = 12V for fast Program (optional) ACCESS TIME: 70ns PROGRAMMING TIME: 10µs typical Double Word Programming Option Quadruple Word Programming Option COMMON FLASH INTERFACE UNIFORM BLOCKS 64-KWord UNIFORM MEMORY BLOCKS M28W320FSU: 32 Blocks M28W640FSU: 64 Blocks HARDWARE PROTECTION
–VPP Pin for Write protect of All Blocks SECURITY FEATURES 128 bit User-programmable OTP segment 64 bit Unique Device Identifier KRYPTO Features:
Modify Protection,
Read Protection,
Device Authentication AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Codes:
M28W320FSU: 880Ch,
M28W640FSU: 8857h PACKAGE Compliant with Lead-Free Soldering
Processes Lead-Free Version
M28W320FSU, M28W640FSU
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Figure 2. M28W320FSU Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 3. M28W640FSU Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 4. TBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 5. M28W320FSU and M28W640FSU Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 6. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Address Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
VDD Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
HARDWARE PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11VPP ≤ VPPLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SECURITY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 3. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3/49
M28W320FSU, M28W640FSU
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Protection Register Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 5. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 6. Read Protection Register and Protection Register Lock . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 7. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . .17
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 10. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 11. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 12. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 9. Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 10.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 14. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 11.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 15. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 12.Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 16. Power-Up and Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Figure 13.TBGA64 - 10x13 active ball array, 1mm pitch, Bottom View Package Outline . . . . . . . .29
Table 17. TBGA64 - 10x13 active ball array, 1mm pitch, Package Mechanical Data . . . . . . . . . . .29
M28W320FSU, M28W640FSU
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 19. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Table 20. Block Addresses, M28W320FSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 21. Block Addresses, M28W640FSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Table 22. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 23. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 24. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 25. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 26. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 27. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39Figure 14.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 15.Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 16.Quadruple Word Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 17.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . .42
Figure 18.Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 19.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 20.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . .45
APPENDIX D.COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE. . . . . . . .46Table 28. Write State Machine Current/Next, sheet 1 of 2.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 29. Write State Machine Current/Next, sheet 2 of 2.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
5/49
M28W320FSU, M28W640FSU
SUMMARY DESCRIPTIONThe M28W320FSU and the M28W640FSU are 32
Mbit (2Mbit x 16) and 64 Mbit (4Mbit x 16) Secure
Flash memories. The devices can be erased elec-
trically at block level and programmed in-system
on a Word-by-Word basis using a 2.7V to 3.6V
VDD supply for the circuitry and a 2.7V to 3.6V
VDDQ supply for the Input/Output pins. An optional
12V VPP power supply is provided to speed up
customer programming.
The M28W320FSU and M28W640FSU feature 32
Mbits and 64 Mbits respectively and are divided
into thirty-two and sixty-four 64-KWord Uniform
blocks, respectively. Refer to Figure 5. for a de-
tailed description of the devices memory architec-
ture and map.
All devices are equipped with hardware and soft-
ware block protection features to avoid unwanted
program/erase (modify) or read of the Flash mem-
ory content: Hardware Protection: When VPP ≤ VPPLK all blocks are
protected against program or erase. Software Protection thanks to KRYPTO
Security Features: Modify Protection: volatile and non-
volatile. Read Protection.
The KRYPTO Security features are described in a
dedicated Application Note. Please contact STMi-
croelectronics for further details.
Two registers are available for protection purpose: The Protection Register The KRYPTO Protection Register.
The Protection Register is a 192 bit Protection
Register to increase the protection of a system de-
sign. The Protection Register is divided into a 64
bit segment and a 128 bit segment. The 64 bit seg-
ment contains a unique device number written by
ST, while the second one is one-time-programma-
ble by the user. The user programmable segment
can be permanently protected. Figure 6., shows
the Protection Register Memory Map.
The KRYPTO Protection Register is used to man-
age the Modify and Read protection modes. It also
features a Device Authentication mechanism. The
KRYPTO Protection Register is described in a
dedicated Application Note. Please contact STMi-
croelectronics for further details.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
All the devices are offered in a TBGA64 (10 x
13mm) package. In addition to the standard ver-
sion, the package is also available in Lead-free
version, in compliance with JEDEC Std J-STD-
020B, the ST ECOPACK 7191395 Specification,
and the RoHS (Restriction of Hazardous Sub-
stances) directive. The package is compliant with
Lead-free soldering processes.
All devices are supplied with all the bits erased
(set to ’1’).
M28W320FSU, M28W640FSU
Table 1. Signal Names
7/49
M28W320FSU, M28W640FSU
M28W320FSU, M28W640FSU
9/49
M28W320FSU, M28W640FSU
SIGNAL DESCRIPTIONSSee Figures 2 and 3, Logic Diagrams and Table
1., Signal Names, for a brief overview of the sig-
nals connected to this device.
Address Inputs. The Address Inputs select the
cells in the memory array to access during Bus
Read operations. Address Inputs range from A0 to
A20 for the M28W320FSU. The M28W640FSU
has an additional A21 address line. During Bus
Write operations they control the commands sent
to the Command Interface of the internal state ma-
chine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable controls
data outputs during the Bus Read operation of the
memory.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable, E, or Write En-
able, W, whichever occurs first.
Reset (RP). The Reset input provides a hard-
ware reset of the memory. When Reset is at VIL,
the memory is in reset mode: the outputs are high
impedance and the current consumption is mini-
mized. After Reset all blocks are in the Locked
state. When Reset is at VIH, the device is in normal
operation. Exiting reset mode the device enters
read array mode, but a negative transition of Chip
Enable or a change of the address is required to
ensure valid data outputs.
VDD Supply Voltage. VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from VDD. VDDQ can be
tied to VDD or can use a separate supply.
VPP Program Supply Voltage. VPP is both a
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin. The Supply Voltage VDD and the
Program Supply Voltage VPP can be applied in
any order.
If VPP is kept in a low voltage range (0V to 3.6V)
VPP is seen as a control input. In this case a volt-
age lower than VPPLK gives an absolute protection
against program or erase, while VPP > VPP1 en-
ables these functions (see Table 12., DC Charac-
teristics, for the relevant values). VPP is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect on Program or Erase.
If VPP is set to VPPH, it acts as a power supply pin.
In this condition VPP must be stable until the Pro-
gram/Erase algorithm is completed (see Table 14.
and Table 15.). A Quadruple Word Program com-
mand will be ignored if VPP is not set to VPPH while
a Double Word Program can be performed even if
VPP is set to VDD.
VSS Ground. VSS is the reference for all voltage
measurements.
Note: Each device in a system should have
VDD, VDDQ and VPP decoupled with a 0.1µF ca-
pacitor close to the pin. See Figure 8., AC Mea-
surement Load Circuit. The PCB track widths
should be sufficient to carry the required VPP
program and erase currents.
M28W320FSU, M28W640FSU
BUS OPERATIONSThere are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and Re-
set. See Table 2., Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Read. Read Bus operations are used to output
the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output En-
able must be at VIL in order to perform a read op-
eration. The Chip Enable input should be used to
enable the device. Output Enable should be used
to gate data onto the output. The data read de-
pends on the previous command written to the
memory (see Command Interface section). See
Figure 9., Read AC Waveforms, and Table
13., Read AC Characteristics, for details of when
the output becomes valid.
Read mode is the default state of the device when
exiting Reset or after power-up.
Write. Bus Write operations write Commands to
the memory or latch Input Data to be programmed.
A write operation is initiated when Chip Enable
and Write Enable are at VIL with Output Enable at
VIH. Commands, Input Data and Addresses are
latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.
See Figure 10. and Figure 11., Write AC Wave-
forms, and Table 14. and Table 15., Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The data outputs are high im-
pedance when the Output Enable is at VIH.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
when Chip Enable is at VIH and the device is in
read mode. The power consumption is reduced to
the stand-by level and the outputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
VIH during a program or erase operation, the de-
vice enters Standby mode when finished.
Automatic Standby. Automatic Standby pro-
vides a low power consumption state during Read
mode. Following a read operation, the device en-
ters Automatic Standby after 150ns of bus inactiv-
ity even if Chip Enable is Low, VIL, and the supply
current is reduced to IDD1. The data Inputs/Out-
puts will still output data if a bus Read operation is
in progress.
Reset. During Reset mode when Output Enable
is Low, VIL, the memory is deselected and the out-
puts are high impedance. The memory is in Reset
mode when Reset is at VIL. The power consump-
tion is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write En-
able inputs. If Reset is pulled to VSS during a Pro-
gram or Erase, this operation is aborted and the
memory content is no longer valid.
Table 2. Bus Operations Note: X = VIL or VIH, VPPH = 12V ± 5%.
11/49
M28W320FSU, M28W640FSU
HARDWARE PROTECTIONAll devices feature hardware protection. Refer to
SIGNAL DESCRIPTIONS section for a detailed
description of these signals.
VPP ≤ VPPLK. The VPP pin protects all the memo-
ry blocks from program and erase operations. Re-
fer to SIGNAL DESCRIPTIONS section for a
detailed description of these signals.
SECURITY FEATURESThe M28W320FSU and M28W640FSU are
equipped with KRYPTO Security features per-
forming software protection. They allow any block
to be protected from program/erase or read oper-
ations: Modify Protection including Volatile Block
Lock/Unlock, Non-Volatile Block Modify
Protection, Non-Volatile Password Modify
Protection and Irreversible Protection. Read Protection.
The KRYPTO features (Modify Protection mode,
Read Protection mode and Device Authentication
mechanism) are not described in this Datasheet.
For further details concerning these additional pro-
tection modes please contact ST Sales Offices.
The devices also feature a 64 bit Unique Device
Identifier and a 128 bit user-programmable OTP
segment (see Figure 6., Protection Register Mem-
ory Map and Protection Register Program Com-
mand).
M28W320FSU, M28W640FSU
COMMAND INTERFACEAll Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time, to monitor
the progress of the operation, or the Program/
Erase states. See Table 3., Command Codes, for
a summary of the commands and see APPENDIX
D., Table 28., Write State Machine Current/Next,
sheet 1 of 2., for a summary of the Command In-
terface.
The Command Interface is reset to Read mode
when power is first applied, when exiting from Re-
set or whenever VDD is lower than VLKO. Com-
mand sequences must be followed exactly. Any
invalid combination of commands will reset the de-
vice to Read mode. Refer to Table 4., Commands,
in conjunction with the text descriptions below.
Read Memory Array Command The Read command returns the memory to its
Read mode. One Bus Write cycle is required to is-
sue the Read Memory Array command and return
the memory to Read mode. Subsequent read op-
erations will read the addressed location and out-
put the data. When a device Reset occurs, the
memory defaults to Read mode.
Read Status Register CommandThe Status Register indicates when a program or
erase operation is complete and the success or
failure of the operation itself. Issue a Read Status
Register command to read the Status Register’s
contents. Subsequent Bus Read operations read
the Status Register at any address, until another
command is issued. See Table 8., Status Register
Bits, for details on the definitions of the bits.
The Read Status Register command may be is-
sued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will automatically output the con-
tent of the Status Register.
Read Electronic Signature Command The Read Electronic Signature command reads
the Manufacturer and Device Codes, and the Pro-
tection Register.
The Read Electronic Signature command consists
of one write cycle, a subsequent read will output
the Manufacturer Code, the Device Code and the
Protection Register. See Tables 5, and 6 for the
valid address.
Table 3. Command Codes
Read CFI Query Command The Read Query Command is used to read data
from the Common Flash Interface (CFI) Memory
Area, allowing programming equipment or appli-
cations to automatically match their interface to
the characteristics of the device. One Bus Write
cycle is required to issue the Read Query Com-
mand. Once the command is issued subsequent
Bus Read operations read from the Common
Flash Interface Memory Area. See APPENDIX
B., COMMON FLASH INTERFACE (CFI), Tables
22, 23, 24, 25, 26 and 27 for details on the infor-
mation contained in the Common Flash Interface
memory area.
Block Erase Command The Block Erase command can be used to erase
a block. It sets all the bits within the selected block
to ’1’. All previous data in the block is lost. If the
block is protected then the Erase operation will
abort, the data in the block will not be changed and
the Status Register will output the error.
Two Bus Write cycles are required to issue the
command. The first bus cycle sets up the Erase
command. The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
13/49
M28W320FSU, M28W640FSUIf the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 are set and
the command aborts.
Erase aborts if Reset turns to VIL. As data integrity
cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.
During Erase operations the memory will accept
the Read Status Register command and the Pro-
gram/Erase Suspend command, all other com-
mands will be ignored. Typical Erase times are
given in Table 7., Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
See APPENDIX C., Figure 18., Erase Flowchart
and Pseudo Code, for a suggested flowchart for
using the Erase command.
Program Command The memory array can be programmed word-by-
word. Two bus write cycles are required to issue
the Program Command. The first bus cycle sets up the Program
command. The second latches the Address and the Data
to be written and starts the Program/Erase
Controller.
During Program operations the memory will ac-
cept the Read Status Register command and the
Program/Erase Suspend command. Typical Pro-
gram times are given in Table 7., Program, Erase
Times and Program/Erase Endurance Cycles.
Programming aborts if Reset goes to VIL. As data
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed.
See APPENDIX C., Figure 14., Program Flow-
chart and Pseudo Code, for the flowchart for using
the Program command.
Double Word Program Command This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel.The two words must differ only for the
address A0.
The Double Word Program command can be is-
sued either with VPP set to VPPH or to VDD.
Three bus write cycles are necessary to issue the
Double Word Program command. The first bus cycle sets up the Double Word
Program Command. The second bus cycle latches the Address and
the Data of the first word to be written. The third bus cycle latches the Address and
the Data of the second word to be written and
starts the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started. Program-
ming aborts if Reset goes to VIL. As data integrity
cannot be guaranteed when the program opera-
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See APPENDIX C., Figure 15., Double Word Pro-
gram Flowchart and Pseudo Code for the flow-
chart for using the Double Word Program
command.
Quadruple Word Program Command This feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel.The four words must differ only for the
addresses A0 and A1.
A Quadruple word Program command will be ig-
nored if VPP is not set to VPPH.
Five bus write cycles are necessary to issue the
Quadruple Word Program command. The first bus cycle sets up the Quadruple
Word Program Command. The second bus cycle latches the Address and
the Data of the first word to be written. The third bus cycle latches the Address and
the Data of the second word to be written. The fourth bus cycle latches the Address and
the Data of the third word to be written. The fifth bus cycle latches the Address and the
Data of the fourth word to be written and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started. Program-
ming aborts if Reset goes to VIL. As data integrity
cannot be guaranteed when the program opera-
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See APPENDIX C., Figure 16., Quadruple Word
Program Flowchart and Pseudo Code, for the
flowchart for using the Quadruple Word Program
command.
Clear Status Register Command The Clear Status Register command can be used
to reset bits 1, 3, 4 and 5 in the Status Register to
‘0’. One bus write cycle is required to issue the
Clear Status Register command.
The bits in the Status Register do not automatical-
ly return to ‘0’ when a new Program or Erase com-
mand is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.
Program/Erase Suspend Command The Program/Erase Suspend command is used to
pause a Program or Erase operation. One bus
write cycle is required to issue the Program/Erase
M28W320FSU, M28W640FSUcommand and pause the Program/Erase control-
ler.
During Program/Erase Suspend the Command In-
terface will accept the Program/Erase Resume,
Read Array, Read Status Register, Read Electron-
ic Signature and Read CFI Query commands. Ad-
ditionally, if the suspend operation was Erase then
the Program, Double Word Program, Quadruple
Word Program, Block Lock, or Protection Program
commands will also be accepted. The block being
erased may be protected by issuing the Block Pro-
tect, Block Lock or Protection Program com-
mands. When the Program/Erase Resume
command is issued the operation will complete.
Only the blocks not being erased may be read or
programmed correctly.
During a Program/Erase Suspend, the device can
be placed in a pseudo-standby mode by taking
Chip Enable to VIH. Program/Erase is aborted if
Reset turns to VIL.
See APPENDIX C., Figure 17., Program Suspend
& Resume Flowchart and Pseudo Code, and Fig-
ure 19., Erase Suspend & Resume Flowchart and
Pseudo Code, for flowcharts for using the Pro-
gram/Erase Suspend command.
Program/Erase Resume Command The Program/Erase Resume command can be
used to restart the Program/Erase Controller after
a Program/Erase Suspend operation has paused
it. One Bus Write cycle is required to issue the
command. Once the command is issued subse-
quent Bus Read operations read the Status Reg-
ister.
See APPENDIX C., Figure 17., Program Suspend
& Resume Flowchart and Pseudo Code, and Fig-
ure 19., Erase Suspend & Resume Flowchart and
Pseudo Code, for flowcharts for using the Pro-
gram/Erase Resume command.
Protection Register Program CommandThe Protection Register Program command is
used to Program the 128 bit user One-Time-Pro-
grammable (OTP) segment of the Protection Reg-
ister. The segment is programmed 16 bits at a
time. When shipped all bits in the segment are set
to ‘1’. The user can only program the bits to ‘0’.
Two write cycles are required to issue the Protec-
tion Register Program command. The first bus cycle sets up the Protection
Register Program command. The second latches the Address and the Data
to be written to the Protection Register and
starts the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started.
The segment can be protected by programming bit of the Protection Lock Register (see Figure
6., Protection Register Memory Map). Attempting
to program a previously protected Protection Reg-
ister will result in a Status Register error. The pro-
tection of the Protection Register is not reversible.
The Protection Register Program cannot be sus-
pended.
15/49
M28W320FSU, M28W640FSU
Table 4. CommandsNote:1. X = Don't Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device Code),
QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Ad-
dress, PRD=Protection Register Data. The signature addresses are listed in Tables 5 and 6. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
Table 5. Read Electronic Signature Note:1. RP = VIH. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU.
M28W320FSU, M28W640FSU
Table 6. Read Protection Register and Protection Register LockNote:1. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU.
17/49
M28W320FSU, M28W640FSU
Table 7. Program, Erase Times and Program/Erase Endurance Cycles
M28W320FSU, M28W640FSU
STATUS REGISTERThe Status Register provides information on the
current or previous Program or Erase operation.
The various bits convey information and errors on
the operation. To read the Status register the
Read Status Register command can be issued, re-
fer to Read Status Register Command section. To
output the contents, the Status Register is latched
on the falling edge of the Chip Enable or Output
Enable signals, and can be read until Chip Enable
or Output Enable returns to VIH. Either Chip En-
able or Output Enable must be toggled to update
the latched data.
Bus Read operations from any address always
read the Status Register during Program and
Erase operations.
The bits in the Status Register are summarized in
Table 8., Status Register Bits. Refer to Table 8. in
conjunction with the following text descriptions.
Program/Erase Controller Status (Bit 7). The
Program/Erase Controller Status bit indicates
whether the Program/Erase Controller is active or
inactive. When the Program/Erase Controller Sta-
tus bit is Low (set to ‘0’), the Program/Erase Con-
troller is active; when the bit is High (set to ‘1’), the
Program/Erase Controller is inactive, and the de-
vice is ready to process a new command.
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
During Program, Erase, operations the Program/
Erase Controller Status bit can be polled to find the
end of the operation. Other bits in the Status Reg-
ister should not be tested until the Program/Erase
Controller completes the operation and the bit is
High.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, VPP
Status and Block Lock Status bits should be tested
for errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that an Erase operation
has been suspended or is going to be suspended.
When the Erase Suspend Status bit is High (set to
‘1’), a Program/Erase Suspend command has
been issued and the memory is waiting for a Pro-
gram/Erase Resume command.
The Erase Suspend Status should only be consid-
ered valid when the Program/Erase Controller Sta-
tus bit is High (Program/Erase Controller inactive).
Bit 7 is set within 30µs of the Program/Erase Sus-
pend command being issued therefore the memo-
ry may still complete the operation rather than
entering the Suspend mode.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has failed to verify
that the block has erased correctly. When the
Erase Status bit is High (set to ‘1’), the Program/
Erase Controller has applied the maximum num-
ber of pulses to the block and still failed to verify
that the block has erased correctly. The Erase Sta-
tus bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive).
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status (Bit 4). The Program Status bit
is used to identify a Program failure. When the
Program Status bit is High (set to ‘1’), the Pro-
gram/Erase Controller has applied the maximum
number of pulses to the byte and still failed to ver-
ify that it has programmed correctly. The Program
Status bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive).
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be-
fore a new command is issued, otherwise the new
command will appear to fail.
VPP Status (Bit 3). The VPP Status bit can be
used to identify an invalid voltage on the VPP pin
during Program and Erase operations. The VPP
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can oc-
cur if VPP becomes invalid during an operation.
When the VPP Status bit is Low (set to ‘0’), the volt-
age on the VPP pin was sampled at a valid voltage;
when the VPP Status bit is High (set to ‘1’), the VPP
pin has a voltage that is below the VPP Lockout
Voltage, VPPLK, the memory is protected and Pro-
gram and Erase operations cannot be performed.
Once set High, the VPP Status bit can only be reset
Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended. When the Program
Suspend Status bit is High (set to ‘1’), a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command. The Program Suspend Status
should only be considered valid when the Pro-
19/49
M28W320FSU, M28W640FSUgram/Erase Controller Status bit is High (Program/
Erase Controller inactive). Bit 2 is set within 5µs of
the Program/Erase Suspend command being is-
sued therefore the memory may still complete the
operation rather than entering the Suspend mode.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if a Pro-
gram or Erase operation has tried to modify the
contents of a locked block.
When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been at-
tempted on a locked block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the new command will appear to fail.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value must be masked.
Note: Refer to APPENDIX C., FLOWCHARTS
AND PSEUDO CODES, for using the Status
Register.
Table 8. Status Register BitsNote: Logic level '1' is High, '0' is Low.
M28W320FSU, M28W640FSU
MAXIMUM RATINGStressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 9. Absolute Maximum RatingsNote:1. Depends on range. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
21/49
M28W320FSU, M28W640FSU
DC AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table
10., Operating and AC Measurement Conditions.
Designers should check that the operating condi-
tions in their circuit match the measurement condi-
tions when relying on the quoted parameters.
Table 10. Operating and AC Measurement Conditions
Table 11. CapacitanceNote: Sampled only, not 100% tested.
M28W320FSU, M28W640FSU
Table 12. DC Characteristics
23/49
M28W320FSU, M28W640FSU
M28W320FSU, M28W640FSU
25/49
M28W320FSU, M28W640FSU
Table 14. Write AC Characteristics, Write Enable Controlled Note:1. Sampled only, not 100% tested. Applicable if VPP is seen as a logic input (VPP < 3.6V).
