M27W102-80K6 ,1 MBIT (64KB X16) LOW VOLTAGE UV EPROM AND OTP EPROMAbsolute Maximum Ratings" maycause permanent damage to the device. These are stress ratings only an ..
M27W201-80B6 ,2 MBIT (256KB X8) LOW VOLTAGE OTP EPROMLogic Diagramprogram storage and is organised as 262,144 by 8bits.V VCC PPThe M27W201 operates in t ..
M27W201-80F6 ,2 MBIT (256KB X8) LOW VOLTAGE OTP EPROMAbsolute Maximum Ratings" maycause permanent damage to the device. These are stress ratings only an ..
M27W20180K6 ,2 MBIT (256KB X8) LOW VOLTAGE OTP EPROMM27W2012 Mbit (256Kb x 8) Low Voltage UV EPROM and OTP EPROM■ 2.7V to 3.6V LOW VOLTAGE in READOPERA ..
M27W201-80K6 ,2 MBIT (256KB X8) LOW VOLTAGE OTP EPROMAbsolute Maximum RatingsSymbol Parameter Value Unit(3)T –40 to 125 °CA Ambient Operating Temperatur ..
M27W401 ,4 MBIT (512KB X8) LOW VOLTAGE UV EPROM AND OTP EPROM
M48T37Y-70MH1 ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. SOIC Connections . . . . ..
M48T37Y-70MH1E ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMFEATURES SUMMARY . . . . . 1Figure 1. Package . . . . . . . 1SUMMARY DESCRIPTION ..
M48T37Y-70MH6E ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. SOIC Connections . . . . ..
M48T512Y-70PM1 ,3.3V-5V 4 MB (512K X 8) TIMEKEEPER SRAMAbsolute Maximum Ratings . . . . . . . 14DC AND AC PARAMETERS . 15Table 7. Operating and ..
M48T559Y-MH1 ,64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXEDAbsolute Maximum Ratings" may cause permanent damage to the device. This is a stressrating only and ..
M48T559Y-MH1TR ,64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXEDLogic Diagram■ WRITE PROTECT VOLTAGE(V = Power-fail Deselect Voltage):PFD– M48T559Y: 4.2V ≤ V ≤ 4.5 ..
M27W102-80K6
1 MBIT (64KB X16) LOW VOLTAGE UV EPROM AND OTP EPROM
1/15April 2000
M27W1021 Mbit (64Kb x16) Low Voltage UV EPROM and OTP EPROM 2.7V to 3.6V LOW VOLTAGE in READ
OPERATION READ ACCESS TIME:
–70ns at VCC = 3.0V to 3.6V
–80ns at VCC = 2.7V to 3.6V PIN COMPATIBLE with M27C1024 LOW POWER CONSUMPTION: 15μA max Standby Current 15mA max Active Current at 5MHz PROGRAMMING TIME 100μs/word HIGH RELIABILITY CMOS TECHNOLOGY 2,000V ESD Protection 200mA Latchup Protection Immunity ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code: 008Ch
DESCRIPTIONThe M27W102 is a low voltage 1 Mbit EPROM of-
fered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage and is organized as 65,536
words by 16 bits.
The M27W102 operates in the read mode with a
supply voltage as low as 2.7V at –40 to 85°C tem-
perature range. The decrease in operating power
allows either a reduction of the size of the battery
or an increase in the time between battery re-
charges.
The FDIP40W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For application where the content is programmed
only one time and erasure is not required, the
M27w102 is offered in PDIP40, PLCC44 and
TSOP40 (10x14 mm) packages.
M27W102
Table 1. Signal Names
3/15
M27W102
Table 2. Absolute Maximum Ratings (1)Note:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. Depends on range.
Table 3. Operating ModesNote: X = VIH or VIL, VID = 12V ± 0.5V.
Table 4. Electronic SignatureNote: Outputs Q15-Q8 are set to '0'.
M27W102
DEVICE OPERATION The operating modes of the M27W102 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for VPP and 12V on A9 for Electronic
Signature.
Read Mode The M27W102 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(tAVQV) is equal to the delay from E to output
(tELQV). Data is available at the output after a delay
of tOE from the falling edge of G, assuming that E
has been low and the addresses have been stable
for at least tAVQV-tGLQV.
Standby Mode The M27W102 has a standby mode which reduc-
es the supply current from 15mA to 15μA with low
voltage operation VCC ≤ 3.6V, see Read Mode DC
Characteristics table for details. The M27W102 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
Table 5. AC Measurement Conditions
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Note: Sampled only, not 100% tested.
5/15
M27W102
Table 7. Read Mode DC Characteristics (1)(TA = –40 to 85°C; VCC = 2.7V to 3.6V; VPP = VCC)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Maximum DC voltage on Output is VCC +0.5V.
Two Line Output Control Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows: the lowest possible memory power dissipation, complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device at the
output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1μF ceram-
ic capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7μF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
M27W102
Table 8. Read Mode AC Characteristics (1)(TA = –40 to 85°C; VCC = 2.7V to 3.6V; VPP = VCC)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Sampled only, not 100% tested. Speed obtained with High Speed AC measurement conditions.
7/15
M27W102
Table 9. Programming Mode AC Characteristics (1)(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics (1)(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Sampled only, not 100% tested.
Programming The M27W102 has been designed to be fully com-
patible with the M27C1024 and has the same elec-
tronic signature. As a result the M27W102 can be
programmed as the M27C1024 on the same pro-
gramming equipment applying 12.75V on VPP and
6.25V on VCC by the use of the same PRESTO II
algorithm. When delivered (and after each ‘1’s era-
sure for UV EPROM), all bits of the M27W102 are
in the '1' state. Data is introduced by selectively
programming '0's into the desired bit locations. Al-
though only '0's will be programmed, both '1's and
'0's can be present in the data word. The only way
to change a ‘0’ to a ‘1’ is by die exopsure to ultra-
violet light (UV EPROM). The M27W102 is in the
programming mode when VPP input is at 12.75V,
E is at VIL and P is pulsed to VIL. The data to be
programmed is applied to 16 bits in parallel to the
data output pins. The levels required for the ad-
dress and data inputs are TTL. VCC is specified to
be 6.25V ± 0.25V.
M27W102
PRESTO II Programming AlgorithmPRESTO II Programming Algorithm allows pro-
gramming of the whole array with a guaranteed
margin, in a typical time of 6.5 seconds. Program-
ming with PRESTO II consists of applying a se-
quence of 100μs program pulses to each word
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE at VCC much
higher than 3.6V, provides necessary margin to
each programmed cell.
Program Inhibit Programming of multiple M27W102s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27W102 may be common. A TTL low level pulse
applied to a M27W102's P input, with E low and
VPP at 12.75V, will program that M27W102. A high
level E input inhibits the other M27W102s from be-
ing programmed.
Program Verify A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
and G at VIL, P at VIH, VPP at 12.75V and VCC at
6.25V.
