M27C512 ,512 KBIT (64KB X8) UV EPROM AND OTP EPROMM27C512512 Kbit (64Kb x8) UV EPROM and OTP EPROM■ 5V ± 10% SUPPLY VOLTAGE in READ OPERATION■ ACCESS ..
M27C512-10 F1 ,512 Kbit (64Kb x 8) EPROM, 5V, 100nsFEATURES SUMMARY■ 5V ± 10% SUPPLY VOLTAGE in READ Figure 1. PackagesOPERATION■ ACCESS TIME: 45ns■ L ..
M27C512-10C1 ,512 Kbit (64Kb x 8) EPROM, 5V, 100nsAbsolute Maximum Ratings 9DC and AC PARAMETERS . 10Table 5. AC Measurement Conditions ..
M27C512-10C6 ,512 Kbit (64Kb x 8) EPROM, 5V, 100nsLogic Diagramtwo ranges UV (ultra violet erase) and OTP (onetime programmable). It is ideally suite ..
M27C512-10F1 ,512 Kbit (64Kb x 8) EPROM, 5V, 100nsLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. DIP Connections 5Figur ..
M27C512-10F3 ,512 Kbit (64K x8) UV EPROM and OTP EPROMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. DIP Connections 5Figur ..
M45026 , 145026 COMPATIBLE 3 STATE 19,683 CODES
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M45PE10-VMN6G ,1 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 25 MHz SPI Bus InterfaceFEATURES SUMMARY . . . . . 1SUMMARY DESCRIPTION . . . 4SIGNAL DESCRIPTION . . . ..
M45PE10VMN6P ,1 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 25 MHz SPI Bus InterfaceFEATURES SUMMARY■ 1Mbit of Page-Erasable Flash Memory Figure 1. Packages■ Page Write (up to 256 Byt ..
M45PE10-VMN6P ,1 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 25 MHz SPI Bus InterfaceFEATURES SUMMARY . . . . . 1Figure 1. Packages . . . . . . 1SUMMARY DESCRIPTION ..
M45PE10-VMN6TG ,1 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 25 MHz SPI Bus InterfaceFEATURES SUMMARY■ 1Mbit of Page-Erasable Flash Memory Figure 1. Packages■ Page Write (up to 256 Byt ..
M27C512
512 KBIT (64KB X8) UV EPROM AND OTP EPROM
1/18August 2002
M27C512512 Kbit (64Kb x8) UV EPROM and OTP EPROM 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION ACCESS TIME: 45ns LOW POWER “CMOS” CONSUMPTION: Active Current 30mA Standby Current 100μA PROGRAMMING VOLTAGE: 12.75V ± 0.25V PROGRAMMING TIMES of AROUND 6sec. ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: 3Dh
DESCRIPTIONThe M27C512 is a 512 Kbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for applica-
tions where fast turn-around and pattern experi-
mentation are important requirements and is
organized as 65,536 by 8 bits.
The FDIP28W (window ceramic frit-seal package)
has transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C512 is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages.
M27C5122/18
Table 1. Signal Names
3/18
M27C512
Table 2. Absolute Maximum Ratings (1)Note:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. Depends on range.
Table 3. Operating ModesNote: X = VIH or VIL, VID = 12V ± 0.5V.
Table 4. Electronic Signature
M27C5124/18
DEVICE OPERATION The modes of operations of the M27C512 are list-
ed in the Operating Modes table. A single power
supply is required in the read mode. All inputs are
TTL levels except for GVPP and 12V on A9 for
Electronic Signature.
Read Mode The M27C512 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(tAVQV) is equal to the delay from E to output
(tELQV). Data is available at the output after a delay
of tGLQV from the falling edge of G, assuming that
E has been low and the addresses have been sta-
ble for at least tAVQV-tGLQV.
Standby Mode The M27C512 has a standby mode which reduces
the active current from 30mA to 100μA The
M27C512 is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high imped-
ance state, independent of the GVPP input.
Table 5. AC Measurement Conditions
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Note:1. Sampled only, not 100% tested.
5/18
M27C512
Table 7. Read Mode DC Characteristics (1)(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1)(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Sampled only, not 100% tested. Speed obtained with High Speed AC measurement conditions.
M27C5126/18
Table 8B. Read Mode AC Characteristics (1)(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Sampled only, not 100% tested.
7/18
M27C512
Table 9. Programming Mode DC Characteristics (1)(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Two Line Output Control Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows: the lowest possible memory power dissipation, complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1μF ceram-
ic capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7μF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
M27C5128/18
Table 10. MARGIN MODE AC Characteristics (1)(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
9/18
M27C512
Table 11. Programming Mode AC Characteristics (1)(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Sampled only, not 100% tested.
E is pulsed to VIL. The data to be programmed is
applied to 8 bits in parallel to the data output pins.
The levels required for the address and data in-
puts are TTL. VCC is specified to be 6.25V ±
0.25V. The M27C512 can use PRESTO IIB Pro-
gramming Algorithm that drastically reduces the
programming time (typically less than 6 seconds).
Nevertheless to achieve compatibility with all pro-
gramming equipments, PRESTO Programming
Algorithm can be used as well.
ProgrammingWhen delivered (and after each erasure for UV
EPROM), all bits of the M27C512 are in the '1'
state. Data is introduced by selectively program-
ming '0's into the desired bit locations. Although
only '0's will be programmed, both '1's and '0's can
be present in the data word. The only way to
change a '0' to a '1' is by die exposure to ultraviolet
light (UV EPROM). The M27C512 is in the pro-
gramming mode when VPP input is at 12.75V and
