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M27C256B-15C1TR-M27C256B15F1-M27C256B-15F1-M27C256B-15F1.-M27C256B-15F6
256 Kbit (32Kb x 8) UV EPROM and OTP EPROM
M27C256B256 Kbit (32Kbx 8) UV EPROM and OTP EPROM
July 1998 1/15
AI00755B
A0-A14 Q0-Q7
VPPVCC
M27C256B
VSS
Figure1. Logic Diagram± 10% SUPPLY VOLTAGEin READ
OPERATION
FASTACCESS TIME: 45ns
LOW POWER CONSUMPTION: Active Current 30mAat 5MHz Standby Current 100μA
PROGRAMMING VOLTAGE: 12.75V± 0.25V
PROGRAMMING TIME: 100μs/byte
(PRESTOII ALGORITHM)
ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: 8Dh
DESCRIPTIONTheM27C256Bisa 256KbitEPROMofferedin the
two ranges UV (ultra violet erase) and OTP (one
time programmable).Itis ideally suitedfor micro-
processor systems andis organizedas 32,768by bits.
The FDIP28W (window ceramic frit-seal package)
hasa transparentlid which allows the userto
expose the chipto ultraviolet lightto erase thebit
pattern.A new pattern can thenbe writtento the
deviceby following the programming procedure.
Forapplications where the contentis programmed
only one time and erasureis not required, the
M27C256Bis offeredin PDIP32, PLCC32 and
TSOP28(8x 13.4 mm) packages.
A0-A14 Address Inputs
Q0-Q7 Data Outputs Chip Enable Output Enable
VPP Program Supply
VCC Supply Voltage
VSS Ground
Table1. SignalNamesTSOP28 (N)x 13.4mn
PLCC32 (C)
PDIP28 (B)
FDIP28W (F)
Warning: NC= Not Connected, DU= Dont’t Use.
DEVICE OPERATIONThe operating modesof the M27C256B are listed the Operating Modes.A single power supplyis
requiredin the read mode. AllinputsareTTLlevels
exceptfor VPP and 12Von A9for ElectronicSigna-
ture.
Read ModeThe M27C256B has two control functions, bothof
which must be logically activein orderto obtain
dataat the outputs. Chip Enable (E)is the power
control and shouldbe used for device selection.
OutputEnable(G)is the output control and should usedto gate datato the output pins, inde-
pendentof device selection. Assuming that the
addresses are stable, the address access time
(tAVQV)isequalto the delayfrom Etooutput (tELQV).
Datais availableat the output after delayof tGLQV
from the falling edgeof G, assuming thatE has
been low and the addresses have been stablefor least tAVQV-tGLQV.
Standby ModeThe M27C256B hasa standby mode which re-
ducesthe supplycurrentfrom30 mAto 100μA. The
M27C256Bis placedin the standby modeby ap-
plyinga CMOS high signalto theE input. Whenin
the standby mode, theoutputs areina high imped-
ance state, independentof theG input.
AI00757
A13
A10Q2
A14
A11V
M27C256B
A12
Figure 2B. LCC Pin ConnectionsA13
A10
A14
A11Q1VSS
A12
VPP VCC
AI00756
M27C256B8
Figure 2A. DIP Pin ConnectionsA11
A13
A14
A12PPCC
AI00614B
M27C256B28SS
A10
Figure 2C. TSOP Pin Connections2/15
M27C256B
Symbol Parameter Value Unit Ambient Operating Temperature(3) –40to 125 °C
TBIAS Temperature Under Bias –50to 125 °C
TSTG Storage Temperature –65to 150 °C
VIO(2) Inputor Output Voltages(except A9) –2to7 V
VCC Supply Voltage –2to7 V
VA9(2) A9 Voltage –2to 13.5 V
VPP Program Supply Voltage –2to14 V
Notes:1. Exceptforthe rating ”OperatingTemperature Range”, stresses above those listedinthe Table ”Absolute Maximum Ratings”
may causepermanent damagetothe device. Theseare stress ratingsonly and operationofthe deviceat theseorany other
conditions above thoseindicatedinthe Operating sectionsofthis specificationis notimplied. Exposureto AbsoluteMaximum
Rating conditionsfor extendedperiods may affectdevice reliability.Refer alsotothe STMicroelectronics SURE Programand other
relevant quality documents. MinimumDC voltageon Inputor Outputis –0.5V with possible undershootto –2.0Vfora period less than 20ns. MaximumDC
voltageon Outputis VCC+0.5V with possible overshoottoVCC +2Vfora period less than 20ns. Dependson range.
Table2. Absolute MaximumRatings(1)
Mode E G A9 VPP Q0-Q7Read VIL VIL XVCC Data Out
Output Disable VIL VIH XVCC Hi-Z
Program VIL Pulse VIH XVPP DataIn
Verify VIH VIL XVPP Data Out
Program Inhibit VIH VIH XVPP Hi-Z
Standby VIH XX VCC Hi-Z
Electronic Signature VIL VIL VID VCC Codes
Note:X =VIHor VIL,VID= 12V± 0.5V
Table3. Operating Modes
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex DataManufacturer’s Code VIL 001 0 000 0 20h
Device Code VIH 100 0 110 1 8Dh
Table4. Electronic Signature
Two Line Output ControlBecauseEPROMsare usuallyusedin larger mem-
ory arrays, this product featuresa2 line control
function which accommodates the useof multiple
memory connection. The two line control function
allows: the lowest possible memory power dissipation, complete assurance that output bus contention
will not occur.
For the mostefficientuseof thesetwo controllines, should be decoded and used as the primary
device selecting function, whileG shouldbe made common connectiontoall devicesin the array
and connectedto the READ line from the system
controlbus. This ensures thatall deselectedmem-
ory devices arein their low power standby mode
and that the output pins are only active when data desired froma particular memory device.
3/15
M27C256B
AI01822
High Speed
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure3. AC TestingInput Output WaveformAI01823B
1.3V
OUT= 30pF forHigh Speed= 100pFfor Standard includes JIGcapacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Figure4. AC Testing Load Circuit
High Speed StandardInput Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0to3V 0.4Vto 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and2V
Table5. AC Measurement Conditions
Symbol Parameter Test Condition Min Max UnitCIN Input Capacitance VIN =0V 6 pF
COUT Output Capacitance VOUT =0V 12 pF
Note:1. Sampled only,not 100%tested.
Table6. Capacitance(1) (TA =25 °C,f=1 MHz)
System ConsiderationsThe power switching characteristicsof Advance
CMOS EPROMs require careful decouplingof the
devices. The supply current, ICC, has three seg-
ments that areof interestto the system designer:
the standby current level, the active current level,
and transient current peaks that are producedby
thefalling and rising edgesofE. The magnitudeof
this transient current peaksis dependenton the
capacitiveand inductiveloadingofthe deviceat the
output.
The associated transient voltage peaks can be
suppressedby complying with the two line output
control and by properly selected decoupling ca-
pacitors.Itis recommended thata 0.1μF ceramic
capacitorbe used on every device between VCC
and VSS. Thisshouldbea highfrequencycapacitor low inherent inductance and shouldbe placed closeto the deviceas possible.In addition,a
4.7μF bulk electrolytic capacitor should be used
betweenVCC and VSS for every eight devices.The
bulk capacitor should be located near the power
supply connection point. The purposeof the bulk
capacitoristo overcome the voltage drop caused the inductive effectsof PCB traces.
4/15
M27C256B
Symbol Parameter Test Condition Min Max UnitILI Input Leakage Current 0V≤ VIN≤ VCC ±10 μA
ILO Output Leakage Current 0V≤ VOUT≤ VCC ±10 μA
ICC Supply Current E= VIL,G= VIL,
IOUT= 0mA,f= 5MHz 30 mA
ICC1 Supply Current (Standby) TTL E=VIH 1mA
ICC2 Supply Current (Standby) CMOS E> VCC– 0.2V 100 μA
IPP Program Current VPP =VCC 100 μA
VIL Input Low Voltage –0.3 0.8 V
VIH(2) Input High Voltage 2 VCC +1 V
VOL Output Low Voltage IOL= 2.1mA 0.4 V
VOH Output HighVoltage TTL IOH= –1mA 3.6 V
Output High Voltage CMOS IOH= –100μAVCC– 0.7 V
Notes:1.VCC mustbe applied simultaneously withor beforeVPP and removed simultaneouslyor after VPP. MaximumDC voltageon OutputisVCC +0.5V.
Table7. Read Mode DC Characteristics(1)(TA=0to 70°C, –40to 85°C, –40to 105°Cor –40 to125°C; VCC =5V± 5%or 5V± 10%;VPP =VCC)
Symbol Alt Parameter Test Condition
M27C256B
Unit-45(3) -60 -70 -80
Min Max Min Max Min Max Min MaxtAVQV tACC Address Validto
Output Valid E=VIL,G=VIL 45 60 70 80 ns
tELQV tCE Chip Enable Lowto
Output Valid G=VIL 45 60 70 80 ns
tGLQV tOE Output Enable Low Output Valid E=VIL 25 30 35 40 ns
tEHQZ(2) tDF Chip Enable Highto
Output Hi-Z G=VIL 0 25 0 30 0 30 0 30 ns
tGHQZ(2) tDF Output Enable High Output Hi-Z E=VIL 0 25 0 30 0 30 0 30 ns
tAXQX tOH Address Transitionto
Output Transition E=VIL,G=VIL 000 0 ns
Notes:1.VCC mustbe appliedsimultaneously withor beforeVPPand removed simultaneouslyor after VPP.
2.Sampled only,not 100%tested.In caseof 45ns speedsee High Speed ACmeasurement conditions.
Table 8A. ReadMode AC Characteristics(1)(TA=0to 70°C, –40to 85°C, –40to 105°Cor –40 to125°C; VCC =5V± 5%or 5V± 10%;VPP =VCC)
5/15
M27C256B
Symbol Alt Parameter Test Condition
M27C256B
Unit-90 -10 -12 -15/-20/-25
Min Max Min Max Min Max Min MaxtAVQV tACC Address Validto
Output Valid E=VIL,G=VIL 90 100 120 150 ns
tELQV tCE Chip Enable Lowto
Output Valid G=VIL 90 100 120 150 ns
tGLQV tOE Output Enable Lowto
Output Valid E=VIL 40 50 60 65 ns
tEHQZ(2) tDF Chip Enable Highto
Output Hi-Z G=VIL 0 30 0 30 0 40 0 50 ns
tGHQZ(2) tDF Output Enable High Output Hi-Z E=VIL 0 30 0 30 0 40 0 50 ns
tAXQX tOH Address Transitionto
Output Transition E=VIL,G=VIL 000 0 ns
Notes:1.VCC mustbe appliedsimultaneously withor beforeVPPand removed simultaneouslyor after VPP.
2.Sampled only,not 100%tested.
Table 8B. Read Mode AC Characteristics(1)(TA=0to 70°C, –40to 85°C, –40to 105°Cor –40 to125°C; VCC =5V± 5%or 5V± 10%;VPP =VCC)
AI00758B
tAXQX
tEHQZ
A0-A14
Q0-Q7
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
Figure5. Read Mode AC Waveforms
ProgrammingWhen delivered (and after each erasure for UV
EPROM),all bitsof the M27C256B arein the ”1”
state. Datais introducedby selectively program-
ming ”0”s into the desiredbit locations. Although
only ”0”s willbe programmed, both ”1”s and ”0”s
canbe presentin the data word. The only wayto
changea ’0’toa ’1’is bydie expositionto ultraviolet
light (UV EPROM). The M27C256Bisin the pro-
gramming mode when VPP inputisat 12.75V,Gis VIH andEis pulsedto VIL. The datato be
programmedis appliedto8 bitsin parallelto the
data output pins. The levels requiredfor the ad-
dress and data inputs are TTL. VCCis specifiedto 6.25V± 0.25V.
6/15
M27C256B
Symbol Parameter TestCondition Min Max UnitILI Input Leakage Current VIL≤ VIN≤VIH ±10 μA
ICC Supply Current 50 mA
IPP Program Current E=VIL 50 mA
VIL Input Low Voltage –0.3 0.8 V
VIH Input High Voltage 2 VCC+ 0.5 V
VOL Output Low Voltage IOL= 2.1mA 0.4 V
VOH Output High Voltage TTL IOH= –1mA 3.6 V
VID A9 Voltage 11.5 12.5 V
Note:1.VCC mustbe applied simultaneously withor beforeVPP and removed simultaneouslyor after VPP.
Table9. ProgrammingMode DC Characteristics(1)(TA =25 °C; VCC= 6.25V± 0.25V;VPP= 12.75V± 0.25V)
Symbol Alt Parameter Test Condition Min Max UnittAVEL tAS Address Validto Chip Enable Low 2 μs
tQVEL tDS Input Validto Chip Enable Low 2 μs
tVPHEL tVPS VPP Highto Chip Enable Low 2 μs
tVCHEL tVCS VCC Highto Chip Enable Low 2 μs
tELEH tPW Chip Enable Program Pulse Width 95 105 μs
tEHQX tDH Chip Enable Highto Input Transition 2 μs
tQXGL tOES Input Transitionto Output Enable Low 2 μs
tGLQV tOE Output Enable Lowto Output Valid 100 ns
tGHQZ tDFP Output Enable Highto Output Hi-Z 0 130 ns
tGHAX tAH Output Enable Highto Address Transition 0 ns
Note:1.VCC mustbe applied simultaneously withor beforeVPP and removed simultaneouslyor after VPP.
Table 10. ProgrammingMode AC Characteristics(1)(TA =25 °C; VCC= 6.25V± 0.25V;VPP= 12.75V± 0.25V)
7/15
M27C256B
tAVEL
VALID
AI00759
A0-A14
Q0-Q7
VPP
VCC
DATAIN DATA OUT
tQVEL
tVPHEL
tVCHEL
tEHQX
tELEH
tGLQV
tQXGL
tGHQZ
tGHAX
PROGRAM VERIFY
Figure6. Programmingand Verify Modes AC WaveformsAI00760B0
Last
Addr
VERIFY= 100μs Pulse
++n
=25 ++ Addr
VCC= 6.25V, VPP= 12.75V
FAIL
CHECK ALL BYTES
1st: VCC =6V
2nd: VCC= 4.2V
YES
YES
YES
Figure7. ProgrammingFlowchart PRESTOII ProgrammingAlgorithmPRESTOII ProgrammingAlgorithm allowsto pro-
gram the wholearray witha guaranteedmargin,in typical timeof 3.5 seconds. Programming with
PRESTOII involves the applicationofa sequence
of100μs programpulsesto eachbyte untilacorrect
verify occurs (see Figure7). During programming
and verify operation,a MARGIN MODE circuitis
automatically activatedin orderto guarantee that
each cellis programmed with enough margin. No
overprogram pulseis applied since the verifyin
MARGIN MODE provides necessary marginto
each programmed cell.
Program InhibitProgrammingof multiple M27C256Bsin parallel
with different datais also easily accomplished.
Except for E, all like inputs includingGof the
parallel M27C256B maybe common.A TTL low
level pulse appliedtoa M27C256B’sE input, with
VPPat 12.75V, will program that M27C256B.A
high levelE input inhibits the other M27C256Bs
from being programmed.
Program Verify verify (read) should be performed on the pro-
grammed bitsto determinethat theywere correctly
programmed. The verifyis accomplished withGat
VIL,Eat VIH,VPPat 12.75Vand VCCat 6.25V.
8/15
M27C256B
