M27C202-80F1 ,2 MBIT (128KB X16) UV EPROM AND OTP EPROMapplications where the content is programmedonly one time and erasure is not required, theA0-A16 Q0 ..
M27C256B ,256 KBIT (32KB X8) UV EPROM AND OTP EPROMapplications where the content is programmedonly one time and erasure is not required, theM27C256B ..
M27C256B ,256 KBIT (32KB X8) UV EPROM AND OTP EPROMAbsolute Maximum Ratings" maycause permanent damage to the device. These are stress ratings only an ..
M27C256B- - 12F6 ,256 Kbit (32Kb x 8) EPROM, 5V, 120nsLogic DiagramThe FDIP28W (window ceramic frit-seal package)has a transparent lid which allows the u ..
M27C256B-10 F1 ,256 Kbit (32Kb x 8) EPROM, 5V, 100nsapplications where the content is programmedonly one time and erasure is not required, theM27C256B ..
M27C256B-10B6 ,256 Kbit (32Kb x 8) EPROM, 5V, 100nsAbsolute Maximum Ratings" maycause permanent damage to the device. These are stress ratings only an ..
M40SZ100WMQ6F ,3 V NVRAM supervisor for LPSRAMBlock diagram . . . . 6Figure 4. Hardware hookup . 7Figure 5. Power-down timing ..
M40SZ100WMQ6F ,3 V NVRAM supervisor for LPSRAMFeaturesSRAM. During a power failure, the SRAM is switched from the V pin to the external battery C ..
M40Z111MH6 ,NVRAM CONTROLLER FOR UP TO TWO LPSRAMLogic Diagram Table 1. Signal NamesTHS Threshold Select InputVCCE Chip Enable InputEConditioned Chi ..
M40Z111MH6 ,NVRAM CONTROLLER FOR UP TO TWO LPSRAMAbsolute Maximum Ratings(Table2.) .... ...... ....... ...... ....... ...... ...... .....4DC AND AC ..
M40Z111WMH6 ,NVRAM CONTROLLER FOR UP TO TWO LPSRAMLogic Diagram(Figure 2.) . ...... ....... ...... ....... ...... ....... ...... ...... .....3Signal ..
M40Z111WMH6TR ,NVRAM CONTROLLER FOR UP TO TWO LPSRAMFEATURES SUMMARY■ CONVERT LOW POWER SRAMs INTO Figure 1. 28-pin SOIC PackageNVRAMs■ PRECISION POWER ..
M27C202-80F1
2 MBIT (128KB X16) UV EPROM AND OTP EPROM
1/17September 2000
M27C2022 Mbit (128Kb x16) UV EPROM and OTP EPROM 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION ACCESS TIME: 45ns LOW POWER CONSUMPTION: Active Current 50mA at 5MHz Standby Current 100μA PROGRAMMING VOLTAGE: 12.75V ± 0.25V PROGRAMMING TIME: 100μs/word ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: 1Ch
DESCRIPTIONThe M27C202 is a 2 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large programs, in
the application where the contents is stable and
needs to be programmed only one time, and is or-
ganised as 131,072 by 16 bits.
The FDIP40W (window ceramic frit-seal package)
has a transparent lids which allow the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C202 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 14 mm) packages.
M27C202
Table 1. Signal Names
3/17
M27C202
Table 2. Absolute Maximum Ratings (1)Note:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. Depends on range.
Table 3. Operating ModesNote: X = VIH or VIL, VID = 12V ± 0.5V.
Table 4. Electronic SignatureNote: Outputs Q15-Q8 are set to '0'.
M27C202
Table 5. AC Measurement Conditions
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Note:1. Sampled only, not 100% tested.
DEVICE OPERATION The operating modes of the M27C202 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for VPP and 12V on A9 for Electronic
Signature.
Read Mode The M27C202 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(tAVQV) is equal to the delay from E to output
(tELQV). Data is available at the output after a delay
of tOE from the falling edge of G, assuming that E
has been low and the addresses have been stable
for at least tAVQV-tGLQV.
Standby Mode The M27C202 has a standby mode which reduces
the supply current from 50mA to 100μA.
The M27C202 is placed in the standby mode by
applying a TTL high signal to the E input. When in
the standby mode, the outputs are in a high imped-
ance state, independent of the G input.
5/17
M27C202
Table 7. Read Mode DC Characteristics (1)(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10%; VPP = VCC)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Maximum DC voltage on Output is VCC +0.5V.
Two Line Output Control Because OTP EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows: the lowest possible memory power dissipation, complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device at the
output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1μF ceram-
ic capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7μF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
M27C202
Table 8A. Read Mode AC Characteristics (1)(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10%; VPP = VCC)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Sampled only, not 100% tested. Speed obtained with High Speed AC measurement conditions.
Table 8B. Read Mode AC Characteristics (1)(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10%; VPP = VCC)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Sampled only, not 100% tested.
7/17
M27C202
M27C202
Table 9. Programming Mode DC Characteristics (1)(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics (1)(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Sampled only, not 100% tested.
Programming When delivered (and after each ‘1’s erasure for UV
EPROM), all bits of the M27C202 are in the '1'
state. Data is introduced by selectively program-
ming '0's into the desired bit locations. Although
only '0's will be programmed, both '1's and '0's can
be present in the data word. The only way to
change a ‘0’ to a ‘1’ is by die exposure to ultraviolet
light (UV EPROM). The M27C202 is in the pro-
gramming mode when VPP input is at 12.75V, E is
at VIL and P is pulsed to VIL. The data to be pro-
grammed is applied to 16 bits in parallel, to the
data output pins. The levels required for the ad-
dress and data inputs are TTL. VCC is specified to
be 6.25V ± 0.25V.
9/17
M27C202
PRESTO II Programming AlgorithmPRESTO II Programming Algorithm allows pro-
gramming of the whole array with a guaranteed
margin, in a typical time of 13 seconds. Program-
ming with PRESTO II consists of applying a se-
quence of 100μs program pulses to each word
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE provides nec-
essary margin to each programmed cell.
Program Inhibit Programming of multiple M27C202s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C202 may be common. A TTL low level pulse
applied to a M27C202's P input, with E low and
VPP at 12.75V, will program that M27C202. A high
level E input inhibits the other M27C202s from be-
ing programmed.
Program Verify A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
and G at VIL, P at VIH, VPP at 12.75V and VCC at
6.25V.
