M27C160-100F1 ,16 MBIT (2MB X8 OR 1MB X16) UV EPROM AND OTP EPROMM27C16016 Mbit (2Mb x 8 or 1Mb x 16) UV EPROM and OTP EPROM■ 5V ± 10% SUPPLY VOLTAGE in READOPERATI ..
M27C160-100F1 ,16 MBIT (2MB X8 OR 1MB X16) UV EPROM AND OTP EPROMapplications where the content is programmedA0-A19only one time and erasure is not required, the15M ..
M27C160-100F1 ,16 MBIT (2MB X8 OR 1MB X16) UV EPROM AND OTP EPROMAbsolute Maximum RatingsSymbol Parameter Value Unit(3)T –40 to 125 °CA Ambient Operating Temperatur ..
M27C160-100F1 ,16 MBIT (2MB X8 OR 1MB X16) UV EPROM AND OTP EPROMLogic Diagramhas a transparent lid which allows the user to ex-pose the chip to ultraviolet light t ..
M27C160-100F6 , 16 Mbit (2 Mb x 8 or 1 Mb x 16) UV EPROM and OTP EPROM
M27C160-100F6 , 16 Mbit (2 Mb x 8 or 1 Mb x 16) UV EPROM and OTP EPROM
M4001 , 9x14 mm, 5.0 or 3.3 Volt, Sinewave, VCSO
M4002 , 9x14 mm, 5.0 or 3.3 Volt, Sinewave, VCSO
M40SZ100WMQ6F ,3 V NVRAM supervisor for LPSRAMBlock diagram . . . . 6Figure 4. Hardware hookup . 7Figure 5. Power-down timing ..
M40SZ100WMQ6F ,3 V NVRAM supervisor for LPSRAMFeaturesSRAM. During a power failure, the SRAM is switched from the V pin to the external battery C ..
M40Z111MH6 ,NVRAM CONTROLLER FOR UP TO TWO LPSRAMLogic Diagram Table 1. Signal NamesTHS Threshold Select InputVCCE Chip Enable InputEConditioned Chi ..
M40Z111MH6 ,NVRAM CONTROLLER FOR UP TO TWO LPSRAMAbsolute Maximum Ratings(Table2.) .... ...... ....... ...... ....... ...... ...... .....4DC AND AC ..
M27C160-100B1-M27C160-100B1.-M27C160100F1-M27C160-100F1
16 MBIT (2MB X8 OR 1MB X16) UV EPROM AND OTP EPROM
1/19January 2002
M27C160 Mbit (2Mbx8 or 1Mbx 16) UV EPROM and OTP EPROM 5V± 10% SUPPLY VOLTAGEin READ
OPERATION ACCESS TIME: 50ns BYTE-WIDEor WORD-WIDE
CONFIGURABLE 16 Mbit MASK ROM REPLACEMENT LOW POWER CONSUMPTION Active Current 70mAat 8MHz Standby Current 100μA PROGRAMMING VOLTAGE: 12.5V± 0.25V PROGRAMMING TIME: 50μs/word ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: B1h
DESCRIPTIONThe M27C160isa16 Mbit EPROM offeredin the
two ranges UV (ultra violet erase) and OTP (one
time programmable).Itis ideally suited for micro-
processor systems requiring large dataor program
storage andis organisedas either2 Mbit wordsofbitor1 Mbit wordsof16 bit. The pin-outis com-
patible witha16 Mbit Mask ROM.
The FDIP42W (window ceramic frit-seal package)
hasa transparentlid which allows the userto ex-
pose the chipto ultraviolet lightto erase thebit pat-
tern.A new pattern can thenbe written rapidlyto
the device by following the programming proce-
dure.
For applications where the contentis programmed
only one time and erasureis not required, the
M27C160is offeredin PDIP42, SDIP42, PLCC44
and SO44 packages.
M27C1602/19
Table1. Signal Names
3/19
M27C160
Table2. Absolute Maximum Ratings(1)Note:1. Exceptforthe rating "Operating Temperature Range", stresses above those listedinthe Table "Absolute Maximum Ratings" may
cause permanent damagetothe device. Theseare stress ratings only and operationofthe deviceat theseorany otherconditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposureto Absolute Maximum Rating condi-
tions forextended periods may affect device reliability.Referalsotothe STMicroelectronics SUREProgramand otherrelevant qual-
ity documents. MinimumDC voltageon Inputor Outputis –0.5V with possible undershootto –2.0Vfora period less than 20ns. MaximumDC
voltageon Outputis VCC +0.5V withpossibleovershoot toVCC +2Vfora period less than 20ns. Dependson range.
Table3. Operating ModesNote:X= VIHor VIL,VID= 12V ±0.5V.
Table4. Electronic SignatureNote: Outputs Q15-Q8aresetto'0'.
M27C1604/19
DEVICE OPERATIONThe operating modesof the M27C160 are listedin
the Operating Modes Table.A single power supply requiredin the read mode. All inputs are TTL
compatible except for VPP and 12Von A9 for the
Electronic Signature.
Read ModeThe M27C160 has two organisations, Word-wide
and Byte-wide. The organisationis selectedby the
signal levelon the BYTEVPP pin. When BYTEVPPat VIH the Word-wide organisationis selected
and the Q15A–1 pinis used for Q15 Data Output.
When the BYTEVPP pinisat VIL the Byte-wide or-
ganisationis selected and the Q15A–1 pinis used
for the Address Input A–1. When the memoryis
logically regardedas 16bit wide, but readin the
Byte-wide organisation, then with A–1at VIL the
lower8 bitsof the16bit data are selected and with
A–1at VIH the upper8 bitsof the16 bit data are
selected.
The M27C160 has two control functions, bothof
which must be logically activein orderto obtain
dataat the outputs.In addition the Word-wideor
Byte- wide organisation mustbe selected.
Chip Enable (E)is the power control and shouldbe
usedfor device selection. Output Enable (G)isthe
output control and shouldbe usedto gate datato
the output pins independentof device selection.
Assuming that the addresses are stable, the ad-
dress access time (tAVQV)is equalto the delay
fromEto output (tELQV). Datais availableat the
output aftera delayof tGLQV from the falling edgeG, assuming thatE has been low and the ad-
dresses have been stableforat least tAVQV-tGLQV.
Table5. AC Measurement Conditions
Table6. Capacitance(1) (TA=25 °C,f=1 MHz)
Note:1. Sampled only,not 100% tested.
5/19
M27C160
Table7. Read Mode DC Characteristics(1)(TA =0to70°Cor –40to85°C; VCC= 5V± 5%or 5V± 10%; VPP =VCC)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP. MaximumDC voltageon Outputis VCC +0.5V.
Standby ModeThe M27C160 hasa standby mode which reduces
the active current from 50mA to 100μA. The
M27C160is placedin the standby modeby apply-
inga CMOS high signalto theE input. Whenin the
standby mode, the outputs areina high imped-
ance state, independentof theG input.
Two Line Output ControlBecause EPROMs are usually usedin larger
memory arrays, this product featuresa2 line con-
trol function which accommodates the useof mul-
tiple memory connection. The two line control
function allows: the lowest possible memory power dissipation, complete assurance that output bus contention
will not occur.
For the most efficient useof these two control
lines,E shouldbe decoded and usedas the prima- device selecting function, whileG should be
madea common connectiontoall devicesin the
array and connectedto the READ line from the
system control bus. This ensures thatall deselect- memory devices arein their low power standby
mode and that the output pins are only active
when datais required froma particular memory
device.
System ConsiderationsThe power switching characteristicsof Advanced
CMOS EPROMs require careful decouplingof the
suppliesto the devices. The supply current ICC
has three segmentsof importanceto the system
designer: the standby current, the active current
and the transient peaks that are producedby the
falling and rising edgesofE.
The magnitudeof the transient current peaksis
dependenton the capacitive and inductive loading the device outputs. The associated transient
voltage peaks can be suppressed by complying
with the two line output control andby properly se-
lected decoupling capacitors.Itis recommended
thata 0.1μF ceramic capacitoris used on every
device between VCC and VSS. This should bea
high frequency typeof low inherent inductance
and shouldbe placedas closeas possibleto the
device.In addition,a 4.7μF electrolytic capacitor
should be used between VCC and VSS for every
eight devices.
This capacitor shouldbe mounted near the power
supply connection point. The purposeof this ca-
pacitoristo overcome the voltage drop causedby
the inductive effectsof PCB traces.
M27C1606/19
Table8. Read Mode AC Characteristics(1)(TA =0to70°Cor –40to85°C; VCC= 5V± 5%or 5V± 10%; VPP =VCC)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP. Sampled only,not 100% tested. Speed obtained with High SpeedAC measurement conditions.
7/19
M27C160
Table9. Read Mode AC Characteristics(1)(TA =0to70°Cor –40to85°C; VCC= 5V± 5%or 5V± 10%; VPP =VCC)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP. Sampled only,not 100% tested. Speed obtained with High SpeedAC measurement conditions.
M27C1608/19
9/19
M27C160
Table 10. Programming Mode DC Characteristics(1)(TA =25°C; VCC= 6.25V± 0.25V; VPP= 12.5V± 0.25V)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP.
Table 11. Programming Mode AC Characteristics(1)(TA =25°C; VCC= 6.25V± 0.25V; VPP= 12.5V± 0.25V)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP. Sampled only,not 100% tested.
ProgrammingWhen delivered (and after each erasure for UV
EPROM), all bitsof the M27C160 arein the'1'
state. Datais introducedby selectively program-
ming '0's into the desiredbit locations. Although
only '0's willbe programmed, both '1's and '0's can presentin the data word. The only wayto
changea'0'toa'1'isby die exposureto ultraviolet
light (UV EPROM). The M27C160isin the pro-
gramming mode when VPP inputisat 12.5V,Gis VIH andEis pulsedto VIL. The datatobepro-
grammedis appliedto16 bitsin parallelto the data
output pins. The levels required for the address
and data inputs are TTL. VCCis specifiedto be
6.25V± 0.25V.
M27C16010/19
PRESTOIII Programming AlgorithmThe PRESTOIII Programming Algorithm allows
the whole arrayto be programed witha guaran-
teed marginina typical timeof 52.5 seconds. Pro-
gramming with PRESTOIII consistsof applyinga
sequenceof 50μs program pulsesto each word
untila correct verify occurs (see Figure 11). During
programing and verify operationa MARGIN
MODE circuitis automatically activatedto guaran-
tee that each cellis programed with enough mar-
gin. No overprogram pulseis applied since the
verifyin MARGIN MODE provides the necessary
marginto each programmed cell.
Program InhibitProgramming of multiple M27C160sin parallel
with different datais also easily accomplished. Ex-
cept forE,all like inputs includingGof the parallel
M27C160 maybe common.A TTL low level pulse
appliedtoa M27C160'sE input and VPPat 12.5V,
will program that M27C160.A high levelE inputin-
hibits the other M27C160s from being pro-
grammed.
Program Verify verify (read) should be performed on the pro-
grammed bitsto determine that they were correct- programmed. The verifyis accomplished withE VIH andGat VIL,VPPat 12.5V and VCCat
6.25V.
