M27C1024-90C1 ,1 MBIT (64KB X16) UV EPROM AND OTP EPROMM27C10241 Mbit (64Kb x16) UV EPROM and OTP EPROM■ 5V ± 10% SUPPLY VOLTAGE in READOPERATION■ ACCESS ..
M27C160-100B1 ,16 MBIT (2MB X8 OR 1MB X16) UV EPROM AND OTP EPROMM27C16016 Mbit (2Mb x 8 or 1Mb x 16) UV EPROM and OTP EPROM■ 5V ± 10% SUPPLY VOLTAGE in READOPERATI ..
M27C160-100B1. ,16 MBIT (2MB X8 OR 1MB X16) UV EPROM AND OTP EPROMAbsolute Maximum Ratings" maycause permanent damage to the device. These are stress ratings only an ..
M27C160100F1 ,16 MBIT (2MB X8 OR 1MB X16) UV EPROM AND OTP EPROMapplications where the content is programmedA0-A19only one time and erasure is not required, the15M ..
M27C160-100F1 ,16 MBIT (2MB X8 OR 1MB X16) UV EPROM AND OTP EPROMM27C16016 Mbit (2Mb x 8 or 1Mb x 16) UV EPROM and OTP EPROM■ 5V ± 10% SUPPLY VOLTAGE in READOPERATI ..
M27C160-100F1 ,16 MBIT (2MB X8 OR 1MB X16) UV EPROM AND OTP EPROMapplications where the content is programmedA0-A19only one time and erasure is not required, the15M ..
M3F60 , Rectifier Diode
M3FL20U , Super Fast Recovery Diode
M3H-50 ,COM Technology Solutions, Inc. - Three-Way Power Dividers, 1 - 100 MHz and 50 - 300 MHz
M4001 , 9x14 mm, 5.0 or 3.3 Volt, Sinewave, VCSO
M4002 , 9x14 mm, 5.0 or 3.3 Volt, Sinewave, VCSO
M40SZ100WMQ6F ,3 V NVRAM supervisor for LPSRAMBlock diagram . . . . 6Figure 4. Hardware hookup . 7Figure 5. Power-down timing ..
M27C1024-10C1-M27C1024-10F1-M27C1024-12C1-M27C1024-12F1-M27C1024-35C1-M27C1024-55F1-M27C1024-80XF1-M27C1024-90C1
1 MBIT (64KB X16) UV EPROM AND OTP EPROM
1/16November 2001
M27C1024 Mbit (64Kb x16) UV EPROM and OTP EPROM 5V± 10% SUPPLY VOLTAGEin READ
OPERATION ACCESS TIME: 35ns LOW POWER CONSUMPTION: Active Current 35mAat 5MHz Standby Current 100μA PROGRAMMING VOLTAGE: 12.75V± 0.25V PROGRAMMING TIME: 100μs/word ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: 8Ch
DESCRIPTIONThe M27C1024isa1 Mbit EPROM offeredin the
two ranges UV (ultra violet erase) and OTP (one
time programmable).Itis ideally suited for micro-
processor systems requiring large dataor program
storage andis organized as 65,536 wordsof 16
bits.
The FDIP40W (window ceramic frit-seal package)
hasa transparentlid which allows the userto ex-
pose the chipto ultraviolet lightto erase thebit pat-
tern.A new pattern can then be writtento the
deviceby following the programming procedure.
For application where the contentis programmed
only one time and erasureis not required, the
M27C1024is offeredin PDIP40, PLCC44 and
TSOP40 (10x14 mm) packages.
M27C10242/16
Table1. Signal Names
3/16
M27C1024
Table2. Absolute Maximum Ratings(1)Note:1. Exceptforthe rating "Operating Temperature Range", stresses above those listedinthe Table "Absolute Maximum Ratings" may
cause permanent damagetothe device. Theseare stress ratings only and operationofthe deviceat theseorany otherconditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposureto Absolute Maximum Rating condi-
tions forextended periods may affect device reliability.Referalsotothe STMicroelectronics SUREProgramand otherrelevant qual-
ity documents. MinimumDC voltageon Inputor Outputis –0.5V with possible undershootto –2.0Vfora period less than 20ns. MaximumDC
voltageon Outputis VCC +0.5V withpossibleovershoot toVCC +2Vfora period less than 20ns. Dependson range.
Table3. Operating ModesNote:X= VIHor VIL,VID= 12V ±0.5V.
Table4. Electronic SignatureNote: Outputs Q15-Q8aresetto'0'.
M27C10244/16
DEVICE OPERATIONThe modesof operationsof the M27C1024 are
listedin the Operating Modes table.A single pow- supplyis requiredin the read mode.All inputs
are TTL levels except for VPP and 12V on A9 for
Electronic Signature.
Read ModeThe M27C1024 has two control functions, bothof
which must be logically activein orderto obtain
dataat the outputs. Chip Enable (E)is the power
control and should be used for device selection.
Output Enable (G)is the output control and should usedto gate datato the output pins, indepen-
Table5. AC Measurement Conditions
Table6. Capacitance(1) (TA=25 °C,f=1 MHz)
Note:1. Sampled only,not 100% tested.
dentof device selection. Assuming that the ad-
dresses are stable, the address access time
(tAVQV)is equalto the delay fromEto output
(tELQV). Datais availableat the output aftera delay tOE from the falling edgeofG, assuming thatE
has been low and the addresses have been stable
forat least tAVQV-tGLQV.
Standby ModeThe M27C1024 hasa standby mode which reduc- the active current from 35mAto 100μA.
The M27C1024is placedin the standby modeby
applyinga TTL high signalto theE input. Whenin
the standby mode, the outputs areina high imped-
ance state, independentof theG input.
5/16
M27C1024
Table7. Read Mode DC Characteristics(1)(TA=0to70 °C, –40to85 °C; –40to 105°Cor –40to 125 °C; VCC= 5V± 5%or 5V± 10%; VPP =VCC)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP. MaximumDC voltageon Outputis VCC +0.5V.
Table8. Read Mode AC Characteristics(1)(TA=0to70 °C, –40to85 °C; –40to 105°Cor –40to 125 °C; VCC= 5V± 5%or 5V± 10%; VPP =VCC)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP. Sampled only,not 100% tested. Speed obtained with High SpeedAC measurement conditions.
Two Line Output ControlBecause EPROMs are usually usedin larger
memory arrays, this product featuresa2 line con-
trol function which accommodates the useof mul-
tiple memory connection. The two line control
function allows: the lowest possible memory power dissipation, complete assurance that output bus contention
will not occur.
For the most efficient useof these two control
lines,E shouldbe decoded and usedas the prima- device selecting function, whileG should be
madea common connectiontoall devicesin the
array and connectedto the READ line from the
system control bus. This ensures thatall deselect- memory devices arein their low power standby
mode and that the output pins are only active
when datais required froma particular memory
device.
M27C10246/16
Table9. Read Mode AC Characteristics(1)(TA=0to70 °C, –40to85 °C; –40to 105°Cor –40to 125 °C; VCC= 5V± 5%or 5V± 10%; VPP =VCC)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP. Sampled only,not 100% tested.
System ConsiderationsThe power switching characteristicsof Advanced
CMOS EPROMs require careful decouplingof the
devices. The supply current, ICC, has three seg-
ments that areof interestto the system designer:
the standby current level, the active current level,
and transient current peaks that are producedby
the falling and rising edgesofE. The magnitudeof
transient current peaksis dependent on the ca-
pacitive and inductive loadingof the deviceat the
output. The associated transient voltage peaks
canbe suppressedby complying with the two line
output control andby properly selected decoupling
capacitors.Itis recommended thata 0.1μF ceram- capacitorbe usedon every device between VCC
and VSS. This shouldbea high frequency capaci-
tor of low inherent inductance and should be
placedas closeto the deviceas possible.In addi-
tion,a 4.7μF bulk electrolytic capacitor shouldbe
used between VCC and VSS for every eight devic-
es. The bulk capacitor shouldbe located near the
power supply connection point.The purposeof the
bulk capacitoristo overcome the voltage drop
causedby the inductive effectsof PCB traces.
7/16
M27C1024
Table 10. Programming Mode AC Characteristics(1)(TA =25°C; VCC= 6.25V± 0.25V; VPP= 12.75V± 0.25V)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP.
Table 11. Programming Mode AC Characteristics(1)(TA =25°C; VCC= 6.25V± 0.25V; VPP= 12.75V± 0.25V)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP. Sampled only,not 100% tested.
ProgrammingWhen delivered (and after each '1's erasurefor UV
EPROM),all bitsof the M27C1024 arein the'1'
state. Datais introducedby selectively program-
ming '0's into the desiredbit locations. Although
only '0's willbe programmed, both '1's and '0's can presentin the data word. The only wayto
changea'0'toa'1'isby die exposureto ultraviolet
light (UV EPROM). The M27C1024isin the pro-
gramming mode when VPP inputisat 12.75V,Eis VIL andPis pulsedtoVIL. The datatobepro-
grammedis appliedto16 bitsin parallelto the data
output pins. The levels required for the address
and data inputs are TTL. VCCis specifiedto be
6.25V± 0.25V.
M27C10248/16
PRESTOII Programming AlgorithmPRESTOII Programming Algorithm allows pro-
grammingof the whole array witha guaranteed
margin,ina typical timeof 6.5 seconds. Program-
ming with PRESTOII consistsof applyinga se-
quenceof 100μs program pulsesto each word
untila correct verify occurs (see Figure 9). During
programming and verify operation,a MARGIN
MODE circuitis automatically activatedin orderto
guarantee that each cellis programmed with
enough margin. No overprogram pulseis applied
since the verifyin MARGIN MODE provides nec-
essary marginto each programmed cell.
Program InhibitProgrammingof multiple M27C1024sin parallel
with different datais also easily accomplished. Ex-
cept forE,all like inputs includingGof the parallel
M27C1024 may be common.A TTL low level
pulse appliedtoa M27C1024'sP input, withE low
and VPPat 12.75V, will program that M27C1024. high levelE input inhibits the other M27C1024s
from being programmed.
Program Verify verify (read) should be performed on the pro-
grammed bitsto determine that they were correct- programmed. The verifyis accomplished withE
andGat VIL,Pat VIH,VPPat 12.75V and VCCat
6.25V.
