M25PE80VMW6TG ,8 Mbit, Low Voltage, Page-Erasable Serial Flash Memory with Byte-Alterability, 50MHz SPI Bus, Standard Pin-outAbsolute Maximum Ratings . . . . . . . 32DC and AC PARAMETERS . 33Table 12. Operating Co ..
M25PE80-VMW6TG ,8 Mbit, Low Voltage, Page-Erasable Serial Flash Memory with Byte-Alterability, 50MHz SPI Bus, Standard Pin-outBlock Diagram . 13INSTRUCTIONS . . 14Table 6. Instruction Set . 14Write Enabl ..
M25PX32-VMW6F , 32-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface
M25PX32-VMW6F , 32-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface
M268QAN , 5x7 mm, 3.3 Volt, HCMOS/TTL Compatible Output, Clock Oscillator
M27128A- - 2F6 ,NMOS 128K 16K x 8 UV EPROMAbsolute Maximum RatingsSymbol Parameter Value UnitT Ambient Operating Temperature grade 1 0 to 70A ..
M38507F8SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38507F8SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38507F8SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38510/00104BCA ,Quadruple 2-Input Positive-NAND Gates 14-CDIP -55 to 125Maximum Ratings.. 410 Power Supply Recommendations... 126.2 ESD Ratings: SN74LS00...... 411 Layout. ..
M38510/30001BCA ,Quadruple 2-Input Positive-NAND Gates 14-CDIP -55 to 125Features 3 DescriptionThe SNx4xx00 devices contain four independent,1• Package Options Include:2-in ..
M38510/30001SCA ,Quadruple 2-Input Positive-NAND Gates 14-CDIP -55 to 125Pin Functions (continued)PINI/O DESCRIPTIONCDIP, CFP, SOIC, SO CFPNAME LCCCPDIP, SO, SSOP (SN74xx00 ..
M25PE80-M25PE80--M25PE80VMW6-M25PE80-VMW6-M25PE80-VMW6G-M25PE80-VMW6P-M25PE80VMW6TG-M25PE80-VMW6TG
8 Mbit, Low Voltage, Page-Erasable Serial Flash Memory with Byte-Alterability, 50MHz SPI Bus, Standard Pin-out
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PRELIMINARY DATAAugust 2005
M25PE808 Mbit, Low Voltage, Page-Erasable Serial Flash Memory with
Byte-Alterability, 50MHz SPI Bus, Standard Pin-out
FEATURES SUMMARY Industrial Standard SPI Pin-out 8 Mbits of Page-Erasable Flash Memory Page Write (up to 256 Bytes) in 11ms (typical) Page Program (up to 256 Bytes) in 1.2ms
(typical) Page Erase (256 Bytes) in 10ms (typical) Sector Erase (512 Kbits) Bulk Erase (8 Mbits) 2.7 to 3.6V Single Supply Voltage SPI Bus Compatible Serial Interface 50MHz Clock Rate (maximum) Deep Power-down Mode 1µA (typical) Electronic Signature JEDEC Standard Two-Byte Signature
(8014h) More than 100,000 Write Cycles More than 20 Year Data Retention Hardware Write Protection of the Top Sector
(64KB) Software Write Protection on a 64KByte
Sector Basis Software Write Protection on a 4KByte Sub-
sector Basis for Sector 0 and Sector 15
Figure 1. Packages
M25PE80
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 3. VDFPN and SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Top Sector Lock (TSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
SPI MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 4. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 5. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Sharing the Overhead of Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
An Easy Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
A Fast Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . .8
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 2. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Table 3. Software Protection Truth Table (Sectors 1 to 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 4. Software Protection Scheme Truth Table (Sectors 0 and 15) . . . . . . . . . . . . . . . . . . . . .10
Figure 6. Software Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 5. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 6. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 8. Write Enable (WREN) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
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M25PE80Figure 9. Write Disable (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 7. Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 10.Read Identification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . .16
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 11.Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . .17
Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 12.Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence . . . . . . . . . . .18
Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Figure 13.Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence
and Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 8. Lock Register Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 14.Read Lock Register (RDLR) Instruction Sequence and Data-Out Sequence . . . . . . . . .20
Page Write (PW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Figure 15.Page Write (PW) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Figure 16.Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Figure 17.Write to Lock Register (WRLR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 9. Lock Register In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Page Erase (PE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Figure 18.Page Erase (PE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Figure 19.Sector Erase (SE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Figure 20.Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Figure 21.Deep Power-down (DP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Release from Deep Power-down (RDP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Figure 22.Release from Deep Power-down (RDP) Instruction Sequence. . . . . . . . . . . . . . . . . . . .29
POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Figure 23.Power-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 10. Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Table 11. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Table 12. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 13. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
M25PE80Figure 24.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 16. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 25.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 26.Top Sector Lock Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 27.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 17. Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 28.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39Figure 29.MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Outline . . . . . . .39
Table 18. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 30.SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, Package Outline. . . . . .40
Table 19. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, Mechanical Data. . . . . .40
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
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M25PE80
SUMMARY DESCRIPTIONThe M25PE80 is an 8 Mbit (1Mb x 8) Serial Paged
Flash Memory accessed by a high speed SPI-
compatible bus.
The memory can be written or programmed 1 to
256 Bytes at a time, using the Page Write or Page
Program instruction. The Page Write instruction
consists of an integrated Page Erase cycle fol-
lowed by a Page Program cycle.
The memory is organized as 16 sectors, each con-
taining 256 pages. Each page is 256 Bytes wide.
Thus, the whole memory can be viewed as con-
sisting of 4096 pages, or 1,048,576 Bytes.
The memory can be erased a page at a time, using
the Page Erase instruction, a sector at a time, us-
ing the Sector Erase instruction, or as a whole, us-
ing the Bulk Erase instruction.
The memory can be Write Protected by either
Hardware or Software, with a protection granulari-
ty of either 64 KBytes (sector granularity) or 4
KBytes (sub-sector granularity inside sector 0 and
sector 15 only).
Figure 2. Logic Diagram
Table 1. Signal Names
Figure 3. VDFPN and SO ConnectionsNote:1. There is an exposed die paddle on the underside of the
MLP8 package. This is pulled, internally, to VSS, and
must not be allowed to be connected to any other voltage
or signal line on the PCB. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
M25PE80
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be pro-
grammed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Read,
Program, Erase or Write cycle is in progress, the
device will be in the Standby mode (this is not the
Deep Power-down mode). Driving Chip Select (S)
Low selects the device, placing it in the Active
Power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Reset (Reset). The Reset (Reset) input provides
a hardware reset for the memory.
When Reset (Reset) is driven High, the memory is
in the normal operating mode. When Reset (Re-
set) is driven Low, the memory will enter the Reset
mode. In this mode, the output is high impedance.
Driving Reset (Reset) Low while an internal oper-
ation is in progress will affect this operation (write,
program or erase cycle) and data may be lost.
Top Sector Lock (TSL). This input signal puts
the device in the Hardware Protected mode, when
Top Sector Lock (TSL) is connected to VSS, caus-
ing the top 256 pages (upper addresses) of the
memory to become read-only (protected from
write, program and erase operations).
When Top Sector Lock (TSL) is connected to VCC,
the top 256 pages of memory behave like the other
pages of memory.
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M25PE80
SPI MODESThese devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. Bus Master and Memory Devices on the SPI BusNote: The Top Sector Lock (TSL) signal should be driven, High or Low as appropriate.
Figure 5. SPI Modes Supported
M25PE80
OPERATING FEATURES
Sharing the Overhead of Modifying DataTo write or program one (or more) data Bytes, two
instructions are required: Write Enable (WREN),
which is one Byte, and a Page Write (PW) or Page
Program (PP) sequence, which consists of four
Bytes plus data. This is followed by the internal cy-
cle (of duration tPW or tPP).
To share this overhead, the Page Write (PW) or
Page Program (PP) instruction allows up to 256
Bytes to be programmed (changing bits from 1 to
0) or written (changing bits to 0 or 1) at a time, pro-
vided that they lie in consecutive addresses on the
same page of memory.
An Easy Way to Modify DataThe Page Write (PW) instruction provides a con-
venient way of modifying data (up to 256 contigu-
ous Bytes at a time), and simply requires the start
address, and the new data in the instruction se-
quence.
The Page Write (PW) instruction is entered by
driving Chip Select (S) Low, and then transmitting
the instruction Byte, three address Bytes (A23-A0)
and at least one data Byte, and then driving Chip
Select (S) High. While Chip Select (S) is being
held Low, the data Bytes are written to the data
buffer, starting at the address given in the third ad-
dress Byte (A7-A0). When Chip Select (S) is driv-
en High, the Write cycle starts. The remaining,
unchanged, Bytes of the data buffer are automati-
cally loaded with the values of the corresponding
Bytes of the addressed memory page. The ad-
dressed memory page then automatically put into
an Erase cycle. Finally, the addressed memory
page is programmed with the contents of the data
buffer.
All of this buffer management is handled internally,
and is transparent to the user. The user is given
the facility of being able to alter the contents of the
memory on a Byte-by-Byte basis.
For optimized timings, it is recommended to use
the Page Write (PW) instruction to write all con-
secutive targeted Bytes in a single sequence ver-
sus using several Page Write (PW) sequences
with each containing only a few Bytes (see Page
Write (PW) section and Table 16., AC Character-
istics).
A Fast Way to Modify DataThe Page Program (PP) instruction provides a fast
way of modifying data (up to 256 contiguous Bytes
at a time), provided that it only involves resetting
bits to 0 that had previously been set to 1.
This might be: when the designer is programming the device
for the first time when the designer knows that the page has
already been erased by an earlier Page Erase
(PE), Sector Erase (SE) or Bulk Erase (BE)
instruction. This is useful, for example, when
storing a fast stream of data, having first
performed the erase cycle when time was
available when the designer knows that the only
changes involve resetting bits to 0 that are still
set to 1. When this method is possible, it has
the additional advantage of minimising the
number of unnecessary erase operations, and
the extra stress incurred by each page.
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) se-
quences with each containing only a few Bytes
(see Page Program (PP) section and Table
16., AC Characteristics).
Polling During a Write, Program or Erase CycleA further improvement in the write, program or
erase time can be achieved by not waiting for the
worst case delay (tPW, tPP, tPE, tSE or tBE). The
Write In Progress (WIP) bit is provided in the Sta-
tus Register so that the application program can
monitor its value, polling it to establish when the
previous cycle is complete.
ResetAn internal Power-On Reset circuit helps protect
against inadvertent data writes. Addition protec-
tion is provided by driving Reset (RESET) Low
during the Power-on process, and only driving it
High when VCC has reached the correct voltage
level, VCC(min).
Active Power, Standby Power and Deep
Power-Down ModesWhen Chip Select (S) is Low, the device is select-
ed, and in the Active Power mode.
When Chip Select (S) is High, the device is dese-
lected, but could remain in the Active Power mode
until all internal cycles have completed (Program,
Erase, Write). The device then goes in to the
Standby Power mode. The device consumption
drops to ICC1.
The Deep Power-down mode is entered when the
specific instruction (the Deep Power-down (DP) in-
9/43
M25PE80struction) is executed. The device consumption
drops further to ICC2. When in this mode, only the
Release from Deep Power-down instruction is ac-
cepted. All other instructions are ignored. The de-
vice remains in the Deep Power-down mode until
the Release from Deep Power-down instruction is
executed. This can be used as an extra software
protection mechanism, when the device is not in
active use, to protect the device from inadvertent
Write, Program or Erase instructions.
Status RegisterThe Status Register contains two status bits that
can be read by the Read Status Register (RDSR)
instruction.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write, Program
or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
Table 2. Status Register FormatNote: WEL and WIP are volatile read-only bits (WEL is set and re-
set by specific instructions; WIP is automatically set and re-
set by the internal logic of the device).
Protection ModesThe environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M25PE80 features
the following data protection mechanisms: Power On Reset and an internal timer (tPUW)
can provide protection against inadvertant
changes while the power supply is outside the
operating specification. Program, Erase and Write instructions are
checked that they consist of a number of clock
pulses that is a multiple of eight, before they
are accepted for execution. All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events: Power-up Reset (RESET) driven Low Write Disable (WRDI) instruction
completion Page Write (PW) instruction completion Page Program (PP) instruction completion Write to Lock Register (WRLR) instruction
completion Page Erase (PE) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion The Hardware Protected mode is entered
when Top Sector Lock (TSL) is driven Low,
causing the top 256 pages of memory to
become read-only. When Top Sector Lock
(TSL) is driven High, the top 256 pages of
memory behave like the other pages of
memory The Reset (Reset) signal can be driven Low to
protect the contents of the memory during any
critical time, not just during Power-up and
Power-down. In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions while
the device is not in active use. The Software Protection is managed by
specific Lock Registers assigned to each
sector and sub-sector as follows: each 64KB sector has a Lock Register inside sector 0 and sector 15, each 4KB
sub-sector also has a Lock Register (in
addition to the Lock Register at sector
level)
The Lock Registers can be read and written
using the Read Lock Register (RDLR) and
Write to Lock Register (WRLR) instructions.
In each Lock Register two bits control the
protection of each sector/sub-sector: the Write
Lock Bit and the Lock Down Bit.
–Write Lock Bit:The Write Lock Bit determines whether
the contents of the sector/sub-sector can
be modified (using the Write, Program or
Erase instructions). When the Write Lock
Bit is set, ‘1’, the sector/sub-sector is write
protected – any operations that attempt to
change the data in the sector/sub-sector
will fail. When the Write Lock Bit is reset to
‘0’, the sector/sub-sector is not write
protected by the Lock Register, and may
be modified, unless TSL is Low (in which
case the top sector will remain write
protected).
Lock Down Bit:The Lock Down Bit provides a mechanism
for protecting software data from simple
hacking and malicious attack. When the
Lock Down Bit is set, ‘1’, further
b7 b0
M25PE80modification to the Write Lock and Lock
Down Bits cannot be performed. A reset,
or power-up, is required before changes to
these bits can be made. When the Lock
Down Bit is reset, ‘0’, the Write Lock and
Lock Down Bits can be changed.
The Write Lock Bit and the Lock Down Bit are
volatile and their value is reset to ‘0’ after a
Power-Down or a Reset.
The definition of the Lock Register bits is given
in Table 8., Lock Register Out.
Refer to Table 3. and Table 4. for details on
the Software Protection for sectors 1 to 14 and
0 and 15, respectively. Figure 6.shows the the
Software Protection scheme.
Table 3. Software Protection Truth Table (Sectors 1 to 14)
Table 4. Software Protection Scheme Truth Table (Sectors 0 and 15)Note:1. All other bits combinations are not-applicable. For more details, refer to the description of the Write to Lock Register (WRLR) instruction.
11/43
M25PE80
Figure 6. Software Protection SchemeNote:1. LD Lock Down bit; WL Write Lock bit.
M25PE80
MEMORY ORGANIZATIONThe memory is organized as: 4096 pages (256 Bytes each). 1,048,576 Bytes (8 bits each) 16 sectors (512 Kbits, 65536 Bytes each)
Each page can be individually: programmed (bits are programmed from 1 to erased (bits are erased from 0 to 1) written (bits are changed to either 0 or 1)
The device is Page, Sector or Bulk Erasable (bits
are erased from 0 to 1).
Table 5. Memory Organization
13/43
M25PE80
Figure 7. Block Diagram
M25PE80
INSTRUCTIONSAll instructions, addresses and data are shifted in
and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-Byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 6.
Every instruction sequence starts with a one-Byte
instruction code. Depending on the instruction,
this might be followed by address Bytes, or by data
Bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Identification (RDID), Read Status Register (RD-
SR), or Read Lock Register (RDLR) instruction,
the shifted-in instruction sequence is followed by a
data-out sequence. Chip Select (S) can be driven
High after any bit of the data-out sequence is be-
ing shifted out.
In the case of a Page Write (PW), Page Program
(PP), Write to Lock Register (WRLR), Page Erase
(PE), Sector Erase (SE), Bulk Erase (BE), Write
Enable (WREN), Write Disable (WRDI), Deep
Power-down (DP) or Release from Deep Power-
down (RDP) instruction, Chip Select (S) must be
driven High exactly at a Byte boundary, otherwise
the instruction is rejected, and is not executed.
That is, Chip Select (S) must driven High when the
number of clock pulses after Chip Select (S) being
driven Low is an exact multiple of eight.
All attempts to access the memory array during a
Write cycle, Program cycle or Erase cycle are ig-
nored, and the internal Write cycle, Program cycle
or Erase cycle continues unaffected.
Table 6. Instruction Set
15/43
M25PE80
Write Enable (WREN)The Write Enable (WREN) instruction (Figure 8.)
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set pri-
or to every Page Write (PW), Page Program (PP),
Page Erase (PE), Sector Erase (SE), Bulk Erase
(BE) and Write to Lock Register (WRLR) instruc-
tions.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
Figure 8. Write Enable (WREN) Instruction Sequence
Write Disable (WRDI)The Write Disable (WRDI) instruction (Figure 9.)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions: Power-up Write Disable (WRDI) instruction completion Page Write (PW) instruction completion Page Program (PP) instruction completion Write to Lock Register (WRLR) instruction
completion Page Erase (PE) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion
Figure 9. Write Disable (WRDI) Instruction Sequence
M25PE80
Read Identification (RDID)The Read Identification (RDID) instruction allows
the 8-bit manufacturer identification to be read, fol-
lowed by two Bytes of device identification. The
manufacturer identification is assigned by JEDEC,
and has the value 20h for STMicroelectronics. The
device identification is assigned by the device
manufacturer, and indicates the memory type in
the first Byte (80h), and the memory capacity of
the device in the second Byte (14h).
Any Read Identification (RDID) instruction while
an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in
progress.
The device is first selected by driving Chip Select
(S) Low. Then, the 8-bit instruction code for the in-
struction is shifted in. This is followed by the 24-bit
device identification, stored in the memory, being
shifted out on Serial Data Output (Q), each bit be-
ing shifted out during the falling edge of Serial
Clock (C).
The instruction sequence is shown in Figure 10..
The Read Identification (RDID) instruction is termi-
nated by driving Chip Select (S) High at any time
during data output.
When Chip Select (S) is driven High, the device is
put in the Stand-by Power mode. Once in the
Stand-by Power mode, the device waits to be se-
lected, so that it can receive, decode and execute
instructions.
Table 7. Read Identification (RDID) Data-Out Sequence
Figure 10. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
17/43
M25PE80
Read Status Register (RDSR)The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write cycle is in progress.
When one of these cycles is in progress, it is rec-
ommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also possible to read the Status Register con-
tinuously, as shown in Figure 11..
The status bits of the Status Register are as fol-
lows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write, Program
or Erase cycle. When set to 1, such a cycle is in
progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write, Program or Erase instruction
is accepted.
Figure 11. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
M25PE80
Read Data Bytes (READ)The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-Byte
address (A23-A0), each bit being latched-in during
the rising edge of Serial Clock (C). Then the mem-
ory contents, at that address, is shifted out on Se-
rial Data Output (Q), each bit being shifted out, at
a maximum frequency fR, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 12..
The first Byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each Byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) instruction.
When the highest address is reached, the address
counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is termi-
nated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time during data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
the cycle that is in progress.
Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out SequenceNote: Address bits A23 to A19 are Don’t Care.
19/43
M25PE80
Read Data Bytes at Higher Speed
(FAST_READ)The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction
is followed by a 3-Byte address (A23-A0) and a
dummy Byte, each bit being latched-in during the
rising edge of Serial Clock (C). Then the memory
contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a
maximum frequency fC, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first Byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each Byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest ad-
dress is reached, the address counter rolls over to
000000h, allowing the read sequence to be contin-
ued indefinitely.
The Read Data Bytes at Higher Speed
(FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driv-
en High at any time during data output. Any Read
Data Bytes at Higher Speed (FAST_READ) in-
struction, while an Erase, Program or Write cycle
is in progress, is rejected without having any ef-
fects on the cycle that is in progress.
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence
and Data-Out SequenceNote: Address bits A23 to A19 are Don’t Care.
M25PE80
Read Lock Register (RDLR)The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Lock
Register (RDLR) instruction is followed by a 3-
Byte address (A23-A0) pointing to any location in-
side the concerned sector (or sub-sector). Each
address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the Lock Reg-
ister is shifted out on Serial Data Output (Q), each
bit being shifted out, at a maximum frequency fC,
during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The Read Lock Register (RDLR) instruction is ter-
minated by driving Chip Select (S) High at any
time during data output.
Any Read Lock Register (RDLR) instruction, while
an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle
that is in progress.
Table 8. Lock Register OutNote:1. Valid only for sector 0 and sector 15 (the value ‘0’ is returned for other sectors).
Figure 14. Read Lock Register (RDLR) Instruction Sequence and Data-Out Sequence
21/43
M25PE80
Page Write (PW)The Page Write (PW) instruction allows Bytes to
be written in the memory. Before it can be accept-
ed, a Write Enable (WREN) instruction must previ-
ously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device
sets the Write Enable Latch (WEL).
The Page Write (PW) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address Bytes and at least
one data Byte on Serial Data Input (D). The rest of
the page remains unchanged if no power failure
occurs during this write cycle.
The Page Write (PW) instruction performs a page
erase cycle even if only one Byte is updated.
If the 8 least significant address bits (A7-A0) are
not all zero, all transmitted data exceeding the ad-
dressed page boundary roll over, and are written
from the start address of the same page (the one
whose 8 least significant address bits (A7-A0) are
all zero). Chip Select (S) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
If more than 256 Bytes are sent to the device, pre-
viously latched data are discarded and the last 256
data Bytes are guaranteed to be written correctly
within the same page. If less than 256 Data Bytes
are sent to device, they are correctly written at the
requested addresses without having any effects
on the other Bytes of the same page.
For optimized timings, it is recommended to use
the Page Write (PW) instruction to write all con-
secutive targeted Bytes in a single sequence ver-
sus using several Page Write (PW) sequences
with each containing only a few Bytes
Chip Select (S) must be driven High after the
eighth bit of the last data Byte has been latched in,
otherwise the Page Write (PW) instruction is not
executed.
As soon as Chip Select (S) is driven High, the self-
timed Page Write cycle (whose duration is tPW) is
initiated. While the Page Write cycle is in progress,
the Status Register may be read to check the val-
ue of the Write In Progress (WIP) bit. The Write In
Progress (WIP) bit is 1 during the self-timed Page
Write cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the
Write Enable Latch (WEL) bit is reset.
A Page Write (PW) instruction applied to a page
that is Hardware or Software Protected is not exe-
cuted.
Any Page Write (PW) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
Note:1. Address bits A23 to A19 are Don’t Care1 ≤ n ≤ 256
M25PE80
Page Program (PP)The Page Program (PP) instruction allows Bytes
to be programmed in the memory (changing bits
from 1 to 0, only). Before it can be accepted, a
Write Enable (WREN) instruction must previously
have been executed. After the Write Enable
(WREN) instruction has been decoded, the device
sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address Bytes and at least
one data Byte on Serial Data Input (D). If the 8
least significant address bits (A7-A0) are not all
zero, all transmitted data exceeding the ad-
dressed page boundary roll over, and are pro-
grammed from the start address of the same page
(the one whose 8 least significant address bits
(A7-A0) are all zero). Chip Select (S) must be driv-
en Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 16.
If more than 256 Bytes are sent to the device, pre-
viously latched data are discarded and the last 256
data Bytes are guaranteed to be programmed cor-
rectly within the same page. If less than 256 Data
Bytes are sent to device, they are correctly pro-
grammed at the requested addresses without hav-
ing any effects on the other Bytes of the same
page.
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) se-
quences with each containing only a few Bytes
(see Table 16.,
AC Characteristics).Chip Select (S) must be driven High after the
eighth bit of the last data Byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed.
As soon as Chip Select (S) is driven High, the self-
timed Page Program cycle (whose duration is tPP)
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is complete, the Write Enable Latch (WEL)
bit is reset.
A Page Program (PP) instruction applied to a page
that is Hardware or software Protected is not exe-
cuted.
Any Page Program (PP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effects on the cycle that
is in progress.
Figure 16. Page Program (PP) Instruction SequenceNote:1. Address bits A23 to A19 are Don’t Care1 ≤ n ≤ 256
